GB2339931A - Microprocessor-based computer control unit - Google Patents

Description

2339931 j D D I G I T A L E L B C T R 0

SHEFFIELD ENGLAND

P L E A 5 E 0 R DER BY ANY OF TRE FOLLOWING 0 E A N 6 -1 3 C: 5 R E S C-1 1 4 1 4 Z 7 C, 7 N F E P T. N: Z P C T C: -1 i7 7.1 1 P, --- C T HIGHLIGHTS OF THE Z80 FOR PC DESCATOC CARD Z80 FOR PC DESCATOC CARD THE WAY AHEAD FOR PC COMMUNICATIONS The conception of this Card came about due to an ever icreasing demand for the PC to become 11 an electric efficient product. This is particularly the case with die ever increasing wastage of electric current as more and more private households and businesses assign the ever popular PC Computer to the task of looking after the telephone line/s for any type of digital incoming call.

The call may well be either a BBS call or it could be the reception of an important FAX document or maybe even a direct video conference call or if the PC is set up as a XNWWhost, a web call.

This is all verv well except that in order for the PC to take any of these calls the PC must be fully powered up.vith he necessary host software loaded, here is where the power wastage comes from, it is the delay between cgs when the PC is idle that causes dils problem.

Here is %,.,I-iere the DESCATOC Card comes into play, the card is able to sense any incoming calls from a rnicrophone connectic.)n to the bell of a telephone that is connected to the same line as your PC's Modem. As soon as a call comes in the DESCATOC Card senses die ring pattern of the call ( more -about that III a moment) and gets the PC to bootstrap die appropriate host software as the phone is still ringing until the host software has been loaded %+iereupon the PC picks die call up and the Nfodern takes the call in the normal fashion.

After die call termiates, die host soft%,are that was loaded initiates a count out to power off sequence whereby if Windows was previously loaded (95 or 3.') in order for the host software to run the DESCATOC takes over control of the PC system and bring-, it either out to DOS for V,indow, s 3) -' or for Windows 95 the ' It is now safe to turn oif your computer ' message, 'Xiiereupon the PC looses its power supply until the next call is realized by the Z80 DES&\TOC Card.

A little while back I mentioned that flits Card is -able to sense ring patterns and make decisions apprnpriate.ly as to what host software. the PC is to boot on power up. This is achieved by die DESCATOC Card being pre programmed by the PC widi all the PC control parameter-- upon the very first time the Card is powered up. In case you are wondening how aii internal card that fits into a spare. ISA slot is powered as die PC is nearly always completely switched off, die card has its own external power supply.xlilch is always connected to the rnains supply. This mav seem to be a contradic6on in terms, but if you care to observe the excel charts enclosed in this pub'lication, you -will find that the DESCATOC Card runs at an electric current level many, many times below that of the PC if it were con6nually connected to the mains.

11-iis basically amounts to a huge saving of money to you as a PC comms user over a quarterly power bill period, and ultimately more importantly a colossal saving of coal and of planetaria] raw energy components such as coal becoming stock-piled at power stations up and down the country rather thari being bumt.

This is why die DESCATOC Card is an energy conserving project. So, once the Card is pre progranirned the control data that is generated and sent from the PC to the DESCATOC Card is stored in RAN4 -Nlemorv on board the Card. Upon reception of an incon-Ling call, this data is then used by the Z80 Microprocessor to help it to decide exactly what to do to the PC upon PC power up. Tlie data is held continuously in the Cards R212M Memory. The card is default supplied wid-i Volatile RANI Memory. However, the customer may specify that dieyvould like non volatile R-A-M'Memory fitted for an extra norninal sum of monei, this of course would mean that the card would ride out total power outs without the need for it to be reprograrnmed upon restoration of the main power supply.

Because die DESCATOC Card is able to detect ring patterns upon incoming calls it can be programmed usuilg die PC DESCATOC Control Program to tell the PC to execute a certain type of Host Software upon reception of a certa-in type of ring pattern. So, the DESCATOC Card supports distinctive ringing. The Telecommunications service provider can assign all manner of different types of ring pattern for a given phone number and die DESCATOC Card can detect them all!!, how is this so ?, it is due to the fact that the PC DESCATOC Control Program gets the DESCkTOC Card to listen to die ring pattern in question after which the ring pattern is translated into a certain Binary pattern of infinite combinations yet unique to the ring style, and stored in R-10d on the Card ready for use by die DESCATOC Card upon reception of an fficorrng call with the same ring pattern.

17his means that the Sysop can then assign as many types of Host Software diere are for as =my types of different ring pattern combinations there are without any problem. At the moment, I have. enabled 4 Distinctive Ring Pattern Programming Channels per Card, thus enabling the selecfion of up to four different types of PC host software to be booted on power up. The Wfimate result of all this is summed up in the following Table:

Terrni'nal Dialed DESCATOC Card Programmed Operations ------------------------ - -------- 2499802 POWI,-arait9, mosst2lrnosNxtl2,clicklllF-,kX.F-'.,,-E. run 2257296 PO\N71,-,,,alt2Ok-eNCD\retwaltl2k-evE:ret,eyBBS.EXE run 2214340 PO\N,"1,walt8O,alt-s,arrowup4,arrowrgtl,arrc)-%,?up5,arro%-,,rgTl, ret these examples are, respectively relating to:

249980-1 DESCATOC command references to a mouse nLineuvertin W3.1 21-57296 DESCATOC command references to a keyboard maneuver in DOS.

2214340 DESCATOC corrimand references to a keyboard maneuver in \N-195.

These conunands are an example of how the Sysop,,vould enter this data in a V%' 'Indows or DOS based application for the DESCATOC programming PC based program.

No,,%,, the above commands will be briefly explained.

POV'1 Turn the PC power on POWO Turn the PC power off wait-',: wait X amount of secs before executing next command mosst2l move internal mouse pointer 21 PC interrupts heading south.

moswt12 same as mosst2l except heading west.

click-EXY click X mouse button Y times X could be 1, rn or r. Y may-be 1 or 2.

send to PC keyboard decoder a DOS style command.

re; send a carriage return to the PC keyboard decoder run tells PC to execute E' XE program arro\vupX tells PC cursor to go up X places on a drop menu in windows X igh t arro,.,.,rgt as above, except the cursor moves X places ri now these high level commands are translated into binary by the PC and sent to the Z80 system via the 1SA bus and it', port svstem. As binary. code, the Z80 stores this data in its personal RA-M ready for use upon reception of an incoming call.

Z80 DESCATOC CARD CIRCMT DESCRIPTION CONTINUED PART 2

PIO 2 - CIRCUIT OPERATIONAL DESCRIPTION -------------------------------------------------------------

PIO 2 is associated with the internal Keyboard. All bits that are associated with this PIO are configured as output. This means that there are in effect 16 bits across 2 active ports that are used here to control the HT6547B Keyboard Encoder chip. PIO 2 does not create any interrupts to the Z80 because the Pori applications do not need this facility. There now follows a general description of the function of the bits driving the Internal Keyboard Encoder.

PAO - PA6 These bits select one of the 104 switches contained in the two CD4067 16 line to I decoder chips.

PA 7 a logic 0 on this bit enables a switch closure, and thus a character is sent to the PC. A I on this lines enables a switch release, breaking the circuit, and so stopping the Internal Keyboard from repeating the same character.

This bit is wired to the INHEBIT active high pin of both 4067's.

PBO this bit is connected to a 405' 3 triple SPDT switch IC. this bit controls switch B in this case. Switch B routes the Keyboard line called DATA from either the external Keyboard to the DATA line of the PC's Keyboard connector socket when this bit is at 0, or when this bit is at 1, the DATA line is re-routed ftom the PC's Keyboard Connector Socket to the internal Keyboard's DATA line. When the DATA line is routed away ftom one Keyboard, that keyboard will not function at all until both its CLOCK and DATA lines are connected to the PC's Keyboard Socket via this 4053 chip. The two Keyboards can be switched in this way as many times as necessary without any problem at all.

PB1 The same as PBO except that PB I controls the Keyboard's CLOCK line and this bit controls switch A of the 405-3 chip.

PB2-PB5 these bits control the auxiliary Keyboard switches SHIFT ALT CTRL, and DEL. these bits are wired to another type of switching IC similar to the 4053. TMs chip is the 4016 quad push to make, release to break single pole switch array it's basically four switches in one package. Each control bit on the switches 'pushes' the switch in and makes a circuit when the PB bit is at 1, when this bit is at 0, the 'release' action is applied and the circuit becomes open again. the very same action as if a Human puts one of their fingers on key of a keyboard, depresses the key, and then releases it again.

PB6 - PB7 these last two bits are not used in this application.

PIO SELECTION CIRCUIT DESCRIPTION

The ') PIO chips on this card are all connected together except for the CE line. all three CE lines belonging to all -3) PIO's are all connected to separate pins of a 74LS 1 8 3 line to 8 line decoder chip. This chip decodes the 1/0 port address assignment of each PIO in the Z80 1/0 address map. As there are only ') PIO chips to select, only the first 3 output bits of the 74LS 1 -3) 8 are used, and they are 0, 1 and 2 respectively. It i s these that connect to the CE lines of each PIO chip. CE is active low and so are the output lines of the 74LSI'38, so no inverter logic is necessary to interface the 1318 to the PIO's. As the I ") 8 only has to contend with operating just 3) of its possible 8 lines, only 2 address bits of the Z80 are therefore required in order to select the night PIO.

The address bit involved are A3 and A4 respectively. The Z80 address bits A5 and A2 together with IORQ select the 74LS 1 3) 8 chip itself, due to the fact that this chip has 3 lines which need the binary word 001 applied to it before the chip is selected by the Z80. The operation of PIO selection by the Z80 can be summed up in the following table

IORQ A2 A3 A4 A5 CEO CEI CE2 A6-C/D A7-A/B RESULT --------------------------------------------------------------------------------------------- 1) 0 1 0 0 0 0 1 1 1 1 cont,Port B, PIO 0 2) 0 1 0 0 0 0 1 1 1 0 cont,Port A, PIO 0 3) 0 1 0 0 0 0 1 1 0 0 data,Por-t A, PIO 0 4) 0 1 0 0 0 0 1 1 0 1 data,Port B, PIO 0 5) 0 1 1 0 0 1 0 1 1 1 cont,Port B, PIO 1 6) 0 1 1 0 0 1 0 1 1 0 cont,Port A, PIO 1 7) 0 1 1 0 0 1 0 1 0 0 data,Port A, PIO 1 8) 0 1 1 0 0 1 0 1 0 1 data,Port B, PIO I 9) 0 1 1 1 0 1 1 0 1 1 cont,Port B, PIO 2 10) 0 1 1 1 0 1 1 0 1 0 cont,Port A, PIO 2 11) 0 1 1 1 0 1 1 0 0 0 data,Port A, PIO 2 12) 0 1 1 1 0 1 1 0 0 1 dataPort B, PIO 2 The above binary words have their Hexadecimal equivalents shown next. Associate the number next to the closed bracket with the equivalent Hex Words.

1) C5h,C4h,C6h, or C7h. PIO 0 2) 44h, 4511, 46h, or 47h. PIO 0 3)) 04h, 05h, 06h, or 07h. PIO 0 4) 84h, 85h, 86h, or 87h. PIO 0 the Hex words on their respective 5) CChCDhCEh, or CFh. PIO I lines all mean the same as each other, 6) 4Ch, 4Dh, 4Eh, or 4Fh. PIO I as AO and A I are not decoded. 7) OCh, ODh, OEh, or OFh. PIO 1 8) 8Ch, 8Dh, 8Eh, or 817h. PIO 1 9) DCh, DEh, DFh, o DDh. PIO 2 10) 5Ch, 5Dh, 5Eh, or 517h. PIO 2 11) 1 Ch, I Dh, I Eh, or I Fh. PTO -2 12) 9Ch, 9Dh, 9Eh, or 9Fh. PTO 2 Address bit A6 selects either Control when the bit is at 1, or Data When the bit is at 0. Control and Data refer to the type of word being sent to the selected PTO. A Control word is part of the initial programming process and is always sent to the PTO when the Programmer wishes to change the mode of a port or a bit in a port of a PTO. The Control Word is always sent to the PTO when the Card is first powered up. This is because without the Control Word, the PTO does not know what mode to set up its ports into as there is a choice of 4.

Address bit A7 selects the A or the B ports of the PTO ready for programming with the Control Word or for Reading, or writing Data from with the Data Word.

CIRCUIT DESCRIPTION OF THE USE OF THE LED DISPLAYS

The LED displays are used mostly for diagnostic purposes, for at a glance one can see the general health of the Card. If the Card at a later stage becomes faulty my customer can return the card to me and I wfll be able to repair it with ease. Of course, the LED's also mak-e the card a little unusual in the sense that the Card fits internafly into a spare ISA slot and so, when the Cover of the PC is closed over the structure of the Case one can no longer see them illuminating!!. It does also serve to enhance the look of the Card wHe it is in operation, and provide to the Customer a little idea (not too much!) of what is actually happening to the flow of binary around the DESCATOC Card. The fol.lowing is a summary of the meaning of the LED's:

THE SEVEN SEGMENT DISPLAY ------------------ The Seven Segment Display serves as a useful output device for:

a) running the diagnostics program, because if you know the software you also know what to expect being displayed here.

b) a preview indicator as to what software the PC will be Booted into. The number and the type of software the PC is booted into, will change dependant on the ning I pattern of the phone and thus the phone number being dialed by the Client Modem on the other end of the phone line.

THE HALT LED -------------------- When this LED is illuminated, it means that the Z80 has read the Machine Code Instruction HALT (76h), and is standing by waiting for an interrupt to occur, program execution has stopped at this point. the Z80 will no longer carry out further instructions until a valid interrupt has occurred on either one of it's two interrupt pins, the purpose of this LED is to allow diagnostics of the PC Communications I procedure, as the instruction HALT., will play a vital part of the transfer of data between the two computers.

THE NNULED ------------------- when this LED is illuminated it means that the Z80 is currently executing a Non Maskable Interrupt. This LED will pulse at regular intervals dependant on whether or not the Z80 has enabled the pulse for itself If the pulse is not enabled this LED will not light at all, but if it is enabled this LED will light approximately once every 12 Seconds. the Purpose of this LED is to check the fact that the Z80 has not crashed in its execution of its software and to check that the Z80 is happy to accept, and execute a Non Maskable Interrupt.

THE DISTINCTIVE RING PATTERN LED -------------------------------------------- ------- When a call comes into the DESCATOC Card, the exchange creates an infinite combination of different ring patterns, dependant on where you live in the world and who your Telecommunications provider is. Here in Sheffield in England the local Cable provider is Yorkshire Cable. Now this Company offers there customers the chance to add ') extra dummy phone numbers to there existing telephone line and number. the Customer therefore ends up with four phone numbers and one telephone line. A seriously brilliant idea and I don't mind saying so!. What this actually means to the DESCATOC project is that for the connection charge of one telephone line, a customer with tMs card and their connection can have FAX, BBS, INTERNET and VOCAL calls all routed properly and without hassle and errors. For instance, this Card can be programmed to ignore phone calls that have the standard national ring pattern because they are normally vocal calls, the 7 Segment display would show a 0 and the PC would not power up as the Z80 knows to ignore this call because it has been programmed to do so, and the distinctive ring pattern LED would illuminate in sympathy with the ring pattern on the phone, when the phone is ringing it is illuminated, during brief moments of silence the LED is not illuminated. this then, provides a visual indication that not only the sound to switch amplifier relay is working properly, but also it shows the audio signal created by the phone has been processed correctly by the Z80.

THE CAPS, SCRL, AND NUM LEDS --------------------------------------------- The function of these LEDS is identical to the function of the LEDS found on most modern external 102/104 key keyboards and thus are self explanatory. Of course, these LEDS refer to the status of the internal keyboard rather than the external, which would have it's own three status LEDS.

3.2768Mhz Crystal Oscillator This Oscillator circuit is based around a 74LS04 Hex inverter chip. As such, it is a true TTL oscillator, except that because the Z80 needs a clean voltage swing of between GND and Vcc each and every clock cycle, a I transistor PNP amplifier with a hfe of some 200 times that of the current at its base is used to boost the 3.4 volts of the TTL signals to the required Z80 system clock input level. As you can imagine, the clock is the most critical and vital part of any CPU system, as all 1/0 operations performed by the CPU are tied to its preciseness. Therefore, if the clock cycles are unstable, the CPU simply will not function correctly and neither will its 1/0 peripheral chips that also require this signal to be input to them. The Circuit operates in the following way:

Crystal XI sets the maximum frequency the 3 inverters can oscillate at. When power is applied to this circuit the first time, the outputs of the first and second stages are both 1, this logic high is feedback via the two I k resistors each stage independent of the other, this resistor feedback loop creates a I at the inputs of the inverters so that their outputs now swing low, now the cycle is repeated again as this 0 is fed back to the 2 gates, now this happens very violently indeed, but, only up to the resonance response of the crystal, once the frenzied activity of the two gates reaches this frequency, their movement stabilises and their switching between hi and lo locks to the frequency of the crystal. Upon power up this all happens in a fraction of a second so that the circuit reaches its operating frequency very quickly indeed, the I OnF capacitor between the two main stages adds further stability so that the circuit is more stable under temperature conditions. the output of this stage is fed to the base of a 2N3) 702 PNP bipolar transistor. This transistor is used to pull up the output voltace of the final 3rd gate to near Vcc which is nearly 5v DC. Therefore the transistor works in unison with the last gate, when this gates input is fed a 0 from the first stage, the PNP transistor is switched hard on, and as its collector is connected to the output of the last gate a I appears here at both devices, the transistor helping the output of the last gate up to near Vcc. When the input to the last gate is at 1, the PNP transistor and the last gate both output 0 together, this is how the operation of the transistor and that of the last crate do not short each other out, but instead the transistor aids the gates output. the 22 ohm resistor in the emitter circuit sets the operational output current of the stage too some 200mA for logic 1. The IK resistor and the 220 Ohm resistor form a potential divider for the base circuit setting the bias voltage to around (220/1000+220) = 0.9 of a Volt the base bias voltage is only there when the output of the first stage is 0 and the transistor conducts. this base voltage offsets the swing of the coRector/emitter circuit so that locic 0 is always GND and logic I is always about 5V at around 200mA. Finally the 47pF capacitor in the Base circuit adds further stabilisation of the input signals to the transistor by rolling off high frequency noise.

I NE555 OSCILATOR FOR THE NNE TNITERRUPT ---------------- When I desian a circuit these days I can never resist droppincy one or two of these -D great little IC's into the design!.They seem to have no end of applications. Well, C I I C here the little chip is set up in free running mode producing a cycle ( not a tandem every 12 seconds. The calculations are as follows:

Manufacturers formula - Fo = 1.44\(((Ra + (2 Rb) Q therefore If Ra = 68000 Ohms, and Rb 470 Ohms and C = 220 Micro farrads the output frequency Fo, Aill be 0. 094 Hz or I cycle per 10 seconds. The Mark and Space ratio are calculated as f6flows:

Manufacturers Mark Formula: T I = 0. 69') (Ra + Rb) C therefore If Ra, Rb and C are the same as above, T I = 10. 5 Seconds (logic I NMI not enabled).

the Space ratio Formula is: TO = 0.693) Rb C therefore If Ra and Rb and C are the same as above, TO 71 nAliseconds ( logic 0 NMI active). So, as you can see from our calculations the NMI pulse actually occurs once every 10.5 Seconds at length's of about a 70th of a second, which is enough time to cause an interrupt to the Z80. NE555 OSCILLATOR SOUNDER What ?, I hear you say, another one 1, that's right, another one!, but this time the little beastie is running a lot faster and drives a piddly little loudspeaker. How fast does it run 'I, Formula James!:

Of course, all formula above is true. So, we merely enter in the values for Fo, and they are - Ra = 8200 Ohms, Rb = 10000 Ohms and C = 47nF using the Fo formula again we get an output frequency this time of 1.0864Khz. this frequency is what could be said the sensitive point of our natural hearing mechanism in our heads, and i'm blowed if that is the product of evolution, but that's another factual story.

THE Z80 FOR PC DESCATOC CARD CIRCUIT DESCRIPTION IS CONCLUDED.

Z80 CARD CIRCUIT DESCRIPTION

The main circuit consists of 4 important chips, and they are 1) the Z80 8 bit Microprocessor 2) PIO 0 3) PIO 1 4) PIO 2 The Z80 is responsible for communicating with the PC via these PIO chips. The PIO chips interface the Z80 into the PC system harmoniously. To achieve this, two completely different address systems were needed to be implemented. First, we have theaddress of the Card itself in the PC bus system which occupies four fully programmable address ports in all of the PC's 64K addressable 110 space. These are all of the 74HCT688 comparator chips that arewired directly to the 8 bit ISA bus system of the PC, these function in the following way: four 8 way DIL switch blocks select the appropriate PC 1/0 address of the particular 74HCT688 they are connected too. ISA 1/0 address lines A3 to A8 are used in the port decoding procedure. so, for example if the binary pattern 0 1100 10 was selected across one of DIL blocks, the 74HCT688 will only bring its A=B line to 0 (active), when exactly the same pattern appears across the address lines A3 to A8 of the PC's 1/0 Address space. the 74HCT688 which has its A=B connected to the BSTB input pin of PIO 0 will therefore send B STB active low when 0 1100 10 appears across A3 to A8 of the ISA bus of the PC. this line BSTB strobes in input data into the Z80 system from the 74HCT273) byte wide latch. When BSTB is active, it also creates an interrupt to the Z80 whereupon the Z80 enters the Machine Code routine held in the EPROM which enables it to communicate with the PC and do such interestine tl- dncs as download to and store in its personal RAM Memory, data which it needs that has been previously stored on the PC Hard Disk. this data is in fact information about what characters to send to the internal keyboard and mouse controllers upon a telephone ling activation, and also how long to wait between sending the PC commands.

Exactly how the Z80 Card communicates with the PC now follows a) The 74HCT273 8 bit latch is connected to a 688 decodincy PC 1/0 address &H05F, data flows to the Z80 from the PC.

b) The 74HCT688 decoding address &H062 operates a 74HCT245 8 bit transceiver C which is wired so that data always flows from the Z80 to the PC.

C) The 74HCT688 decoding address &H061 operates another 74BCT245 but this time onlv 2 of the Z80's control wires, HALT and PA7 on PIO I are read by the PC.

d) The 74HCT688 decoding &H060 operates BSTB of PIO 0 directly.

C Now bearing this mind, this is what happens when the Card is powered for I j, the first time The Z80 reads its program from 0000h onwards, it first of all checks for holes in its RAM if that's OK, 2 bleeps can be heard on its own sounder this occurs because of an internal 1/0 operation peculiar only to the Z80 Card ( more about this later). next it sends the 8 bit word 00h to Port A of PIO 0 and executes a HALT (76h) instruction. it now waits for valid data to appear across PBO to PB7 of Port B of PIO 0. the PC now reads the Z80's status, and by sensing that the HALT pin of the Z80 is now active, the PC reads the byte at 1/0 address &H062, this will be the 00h that the Z80 sent earlier, this word tells the PC to boot the Z80 Card config program in windows. once all the data has been entered into this program, the data must then be sent to the Z80 Card's Z- RAM Memory ready for processing by the Z80 upon reception of an incoming call. So, the PC and the Z80 enter into a communications loop until all the data has been sent, whereupon both CPU's exit their programs.

Now, the PC sends the first 8 bit word to 1/0 address &HO5F, the byte is now stored in the latches of the 74HCT273 ready to be read by the Z80. after this the PC now activates BSTB which causes a maskable interrupt to occur to the Z80, the Z80 now deactivates HALT and executes the communications loop held in its EPROM system software (the particular address it jumps too cannot at this time be given as the system software has not been written yet!), once the byte has been read in by the Z80 with IN a,(n) the Z80 dumps this byte to a determined address in its RAM Memory ready to be used later. after this the Z80 reactivates HALT and waits for the next interrupt and byte to be sent. WHIe in this loop the PC always waits for the Z80's HALT line to go active before it attempts to send it another byte so that data does not get corrupted in the transfer process. as the two computers (the PC and Z80), are very powerful the transfer of 100 bytes takes a fraction of a second as the Z80 always executes pure Machine Code in all its operations with all devices. Now, when all the bytes have been sent, the last words that are sent to the Z80 are 00h, FFh, 00h, FFh respectively, and in that order. this of course uses four interrupts to the Z80, upon reading the last byte FFh, the Z80 forces the PC to leave the Card's configuration program and brings the PC out to DOS prompt for Windows 3. and DOS, or the 'it is now safe to switch off your computer' screen for Windows 95, after which, the Z80 waits a pre prog J grammed time (this will have used some of the data the PC 'ust passed over, as you will have to enter the amount of time it waits), after this time elapses the Z80 sends 0 to PA5 of PIO I upon which the Z80 disengages the PC's power supply and resets waiting for a call. this bit PA5 controls a darlin-ton transistor pair that connects 12v to the PC's power relay only when PA5 of PIO I Is at logic 1, this level (+33.2 volts), is continuously held by the i8O until as such time the Z80 needs to turn the PC off. The above procedure is the only necessary communication theZ80 Computer needs with the PC Computer in order for correct operation of the Z80 Card to ensue. A11 other communication with the PC from now on will be with only the internal keyboard (when the user is not present).unless a PC error has occurred, which is the subject of our next topic.

NON MASKABLE INTERRUPTS AND PC ERRORS The Z80 has 2 types of hardware interrupt one of them is fully programmable in every 0 sense of the word which is the one named INIT, and has just been under discussion in ourlast chapter. the other type is the NMI interrupt which is not at all programmable, I if this type of interrupt occurs during an INT service, the execution of that interrupt service will temporarily stop in favour of the Non Maskable Interrupt program which always starts at 0066h, after the execution of the NMI interrupt has completed, the Z80 continues where it left off in the INT interrupt program, after this has completed and there are no more NMI interrupts, the Z80 branches back to executing the main program once more.

The NNE pin of the Z80 is an input active when at 0. this pin becomes active when the NE555 (yes, another one of those again.) timer brings the NMI wire to 0 volts. the activation of the NM wire occurs at regular intervals of around once every 12 Seconds. the NTNU service program starting at 0066h in the Z80"s EPROK will contain a wealth of program jumps which relate to emergency service procedures that are relevant to both computers. The types of software procedures that will be run are as follows 1. Total Power Failure (Z80 Computer looses its RAM data) Olh 2. disable Z80 Card Sounder 02h enable Z80 Sounder 03 h 4. re enter keyboard data 04h 5. re enter Mouse data 05h 6. erase and re enter columb I sequence data 06h 7. erase and re enter columb 2 sequence data 07h 8. erase and re enter columb 3) sequence data 08h 9. erase and re enter columb 4 sequence data 09h 10. erase all data and start afresh OAh 11. restore all corrupted RAM data from Hard Disk OBh 12. run automated internal keyboard controller test OCh 0. perform a total Z80 system self diagnostic ODh 14. do nothing except return from NMI 00h 15. Manually exit from W95 and switch off ready 4 calls OEh 16. Manually exit from W-3). & switch off ready for calls 10h These listed items will form the main part of all the jumps the Z80 needs to make when it receives an NM. pulse from the NE555. It works like this - . the Z80 jumps to 0066h in the EPROM chip and then considers makincr jumps depending on what data is present on the 74HCT27') octal latch. as mentioned earlier, data arrives at this latch with the PC sending the data to the latches address which is default set to &H05F. For the PC to send data to this port in the first place, the PC must have booted a piece of software for itself to process. It is in fact the Human operator that selects the appropriate program on the PC. the PC then sends the appropriate word to address &H05F, and when the Z80 receives its interrupt, the byte is read into the Z80 via PIO 0 Port B. For example, if you wish to run the internal keyboard test, you first run on the PC a program called K.EYBTE.EXE in windows, this will send the byte ODh to port &H05F, and when the Z80 gets the N-MI pulse, the Z80 will jump to a predefined area in the EPROM which tells the Z80 how to interrogate the internal keyboard. this EPROM program will work in harmony with the PC, and all its output will be to the Monitor screen so that you will be able to see all of what the Z80 is doing to its internal PC keyboard.

It is basicaBy a similar story for all the others. once the NMI Machine Code program has terminated, the Z80 sends a FFh to the PC's input port via port A of PIO 0 to the PC's address &H062. this allows the windows NMI application program to terminate as the PC now knows that the Z80 has completed the test.

CIRCUIT DESCRIPTION OF THE INTERNAL KEYBOARD

Tl-s circuitry is based around Holtek's HT6547B Keyboard Encoder chip. The purpose of this IC is to send to the PC 8 bit words coded in serial fashion for a given X/Y cross hairs switch depression. This is in fact the very same chip that features as the main and if not the only one in all modem 102/104 key keyboards.

The switch matrix forms a 16 x 8 grid giving a total possible 128 switches. Of course, only up to 104 of them are used in this application. These 104 switches are all taken care of by two CD4067BE 16 line to I decoders. each of these IC's has a nibble input from the Z80 which controls wliich of the 16 switches in the chip is selected. for example:

0 0 0 0 = switch 0 selected 000 1 ----- -----2 ----- I I I I = switch 15 selected With the nibble lines stable, if a 0 then a I is applied to the INH03IT pin of the 4067, a switch whose two connections become pin I COMMON and pin 14 (in the I I I I example) are briefly connected. Now, if these two pins are connected to one of the SCO and one of the SCI inputs of the HT6547B respectively, at the moment the INHO31T went from I to 0, a character would be sent to the PC's keyboard decoder on the motherboard and the PC would display the sent character. in this circuit however the two COMMON pins on the two 4067's are wired together, thus two switches have to be made in any combination of both 4067's in order for a circuit to be made and thus in order for the HT6547B to send a character to the PC. as we are only interested in a 16 x 8 matrix, 8 of the switches on one of the 4067's are wired to the GND rail in the circuitry and the appropriate bit of it's control nibble not used and wired to GND. therefore only -3) bits of the 4067's control nibble are used they are: 1, 2,4 only. 8 is not used. Of course all 16 of the switches are used in the other 4067 chip, therefore the whole control nibble of this chip is used by the Z80. Thus as you can see, with the swoop of one byte the Z80 is able to depress and send to the PC any of the 104 characters in any combination, therefore very easily the Z80 can get the PC to execute any one of its EXE programs written on its Hard Disk without you even typing a letter in CENTRAL PROCESSOR CIRCUIT DESCRIPTION

The Zilog Z80 has been with us a few years now, and of course has developed along at the same speed as the IBM series integrated circuits, to become now one of the worlds 0 greatest 8 bit Central Processor Units ever built. It appears now in a variety of formats including the ubiquitous Microcontroller format. The current power is I believe I OMhz Clock, I Mb Memory, on board clock, 32k RAM, and full 8 bit 1/0 porting.

This is all very well and good for other people, but I like to keep things a little more traditional when it comes to my choice of circuit design for the Z80. A quick g-lance at the circuit diagram in this design reveals that I have in fact designed my very own customised Microcontroller. The Microcontroller Circuit consists of in this case a) Z80A 4Mhz CPU b) 27128 l6k x 8 250nS EPROM Memory c) 2 x 2114 200nS I k x 4 bit static RAM ( 2 of these gives I k x 8) d) 3 x Z80 PIO chips yielding 6 x 8 bit user ports in all e) 74LS04 'I tier TTL clock @ 3.2768 Mhz MEMORY The memory for this circuit is controlled by a 74LS 13) 8 3 to 8 line decoder driver. The CPU Address line A] 4 controls the selection of the RAM or the EPROM Memory. MREQ is connected to bit 3) of the decoder chip and bit 2 is connected GND, thus the decoder can only switch in 2 binary patterns. The particular pattern depends on the logic state of the A] 4 fine of the CPU. The two logic patterns therefore Are AO Al A2 -- all lines here belong to the 74LS138 decoder. A14 M GND - these all belong to the CPU. R E Q a) 0 0 0 this means that the decoder enables its 0 output pin. b) 1 0 0 this means that the decoder enables its I output pin. the remaining decoder output pins are not used in this app I I When the CPU wishes to access valid memory, it brings the MREQ line low and active, it then places its address across its address lines and then activates its RD to read Memory or, WR to write to memory line, whereupon if A] 4 is 0, then the EPROM is read, but if A] 4 is at 1, then the RAM is read or written too. Now because A14 is connected to the decoders least significant bit, and the Memory is connected to the decoders least significant 2 output bits, the Memory is organised thus 1.

EPROM read only. A] 4 at 0. EPROM address range therefore between 0000113FFFh. RAM read/write capability. A 14 at 1. RAM address range therefore 40OOh-4400h.

The reason why the RAM starts to be accessed 4000h onward is because A] 4 is when at logic l,the equivalent of 0 -'256 64 = 16384.

4000h is the equivalent of 16-384d. this address line remains at I for any CPU address above 16') 83 and below 3 2768 (A 15 - not used). Conversely, when A 14 is at logic 0-, it /--N means that address bits AO-A I') are being used only, this means address numbers in the range OOOOh-3)FFFh are valid here. And as the EPROM is connected to the 74LS 1 3) 8 0 output pin, this means that the EPROM Memory chip occupies this slot.

PIO 0 OPERATIONAL DESCRIPTION

All PIO Integrated Circuits in this main circuit design yield 2 x 8 bit fully programmable 1/0 ports. The programming Modes for the Z80 PIO chip are as 0 follows MODE MODE CONTROL WORD DESCRIPTION ----------------------------------------------------------- 0 OFh Byte Output I 4Fh Byte Input 2 8Fh Byte Bi-directional 3 CFh Bit Mode FO - C'- L Of the above Modes for the Z80 PIO chip, Mode 3 is the most interesting. In this main circuit design, this mode has been implemented in Port A PIO 1. A description of the operation of PIO I will be given in full after this chapter on PIO 0.

PIO 0 is connected in the following manner, 0 means data flows toward the peripheral device and I means data flows toward the Z80 CPU from the peripheral device.

PIO 0 - Z80 TO PC COMMUNICATIONS INTERFACE PORT A 0 PAO - PA7 configured as byte output to PC PORT B I PBO - P137 configured as byte input from PC PORT A - all valid data flows away from the Z80 to the Pentium/80486. This port is mainly used for the programming sequences of the ZSO Card using PC software. Basically, data is entered upon the PC's Keyboard by Hand, the Keyboard data is then coded and then is transferred to the Z80 system RAM using PIO 0. PORT B - all valid data flows into the Z80 system from the Pentium/80486. A full description of the use of PIO 0 has already been given.

rli-U PIO I - BIT 1/0,& 7 SEGMENT DISPLAY DRIVER ------------------------------- --------------------------------- This PIO is wired to most of the peripheral devices on the card and so justifies an in depth report. The following is a diagram to aid understanding of how the PIO is wired and to what devices send data to it, and what devices receive data from it.

PORT A - BIT 1/0 --------------- ------ 0 PAO - PA2 output data to 7447 7 Segment Driver chip. 0 PA3 - output on/off bit for NE555 generating NMI pulse 0 PA4 - output on/off bit for NE555 driving on board speaker 0 PA5 output on/off bit switching on/off PC main power relay I PA6 - input on/off pulses from phone amplifier circuit relay 0 PA 7 - output bit to PC fom-drig part of PC Comms using PIO 0 PAO - PA2 these bits form the three quarter nibble that controls what number characters are displayed on the 7 segment display. as the first 3 bits of the 7447's input nibble are wired, this means that the following is true:

INPUT DATA ON 7447 7 SEGMENT NOW DISPLAYING 0 0 0 Number 0 0 Number I 0 10 Number 2 1 1 0 Number 3 00 1 Number 4 1 Number 5 0 1 1 Number 6 1 1 1 Number 7 The star character denotes that this input bit of the 7447 driver chip is tied to the GND connection and therefore is always the equivalent of 0.

PA3 - this PIO bit controls the switching off and on of the NMI pulse. Therefore the Z80 has the capability to switch on and off at will its own Non Maskable Interrupt. This piece of added hardware the bit switches, does in fact convert the NM into another maskable interrupt line, althoughwith not quiet the same software programmable characteristics as the INT line.

PA4 - this PIO bit controls the switching on and off of the bell sounder on the Z80 Circuit board. The sounder is enabled upon the instigation of a NMI pulse to the Z80.

0 The NE555 controlling the dispersion of these pulses is set to send an NMI every 12 Secs approximately. Upon reception of the NMI pulse. the Z80 leaves whatever it was doing previous, ajd starts executing the EPROM Machine Code program from 0066h onward. It is during the execution of this code that the Z80 comes across the instructions - DB OC IN A,(OCh) get all bit status of Port A PIO I CB E7 SET 4,A change status of bit PA4 to I D3 OC OUT (OCh),A switch sounder on CD -- -- CALL, DELAY subroutine to allow enough time for sound CB A7 RES 4,A reset to 0 PA4, prepare to switch off sound D-) OC OUT (OCh),A actually now switch the sound off this sequence is roughly what the Z80 would expect to read without going too deep into the proper program, here the CPU registers would have to be preserved and then restored again once the subroutine CD would have completed execution by the Z80, otherwise the above program would goof up the system. You may ask why bother to set all this sounder business up in the first place ?, the answer is, the sounder on this card plays 2 very important parts, and they are respectively:

A) so that the operator can tell if the card has received the NMI error command from the PC or not.

B) so that the operator knows that the Card is working properly suggesting that the Z80 is not only receiving the NMI pulses from the NE555, but also ack-nowledo n "i g the fact that the Z80 is itself stiH executing its Machine Code programming correctly, as the sound here can only be generated by the Z80 actually processing its program 0 1- data, and then acting upon it thus.

PA5 - When this bit is high, the PC is actually powered up, as the electrical characteristics of the bit are amplified by a pair of high gain NPN transistors configured in the darlington arrangement. the output of these transistors switches 12 volts solidly across the solenoid of the PC's power relay, thus energising the relay and closing its contacts which are connected to the Main AC supply. The bit remains at logic I (+ 33.7V), and the relay's contacts are thus kept closed, for the duration of the telephone call. Only when the Card has been sent a certain word from the PC, does the Card switch off the PC until the next call arrives. This happens of course when the Z80 resets to 0 bit PA5, which then in turn de-energises the double transistor Darlington Pair in tum de- energising the relay solenoid and thus cutting off the power to the PC. The usual Semiconductor protection is provided by the IN4001 diode clamped across the relay's solenoid connections. In normal operation the diode is connected reversed biased across the solenoid's switched 12 volt supply and thus does not conduct much current at all, but as soon as the transistors switch off the 12 volt supply to the relay, a large reverse biased current is momentarily generated in 0.

the relay solenoid, but now the diode is for-ward biased and immediately short circuits this unwanted current out to nothing well before it can damage the Darlington Pair transistors, which is what would have happened had the diode not been there.

PA6 - this and PA5 are probably the most important two bits in the whole Card. P4Yhowever is an input bit. The data it receives is composed primarily of 1 s and 0 s that follow in sympathy with the ring (1) and silence (0) of the telephone. thus, only for the duration of each ring is this input bit at logic 1. This enables an infinite combination of ring patterns to not only be recognised and acted appropriately upon by the Z80, but also to be programmed into the Z80 system as a string of bytes, each unique distinctive ring pattern producing its very own unique train of bytes. once the ring patterns have been stored as a group of bytes, it only remains for the Z80 to compare the incoming ring pattern with that of which is stored in its memory, and thus boot the PC with the appropriate host software if a match is found. If a match is not found, (i.e the standard National ring pattern for Vocal Calls), the Z80 ignores the call and the PC is not switched on and booted. This effectively enables up to 3 other numbers to be associated with your ONE telephone line!, and none of them will confuse. The operation of the peripheral device feeding PA6 is as follows:

two very high gain transistors are wired to form a two stage common emitter amplifier. the two transistors are directly coupled to each other collector to base. The life gain of this 2 transistor amplifiers somewhere in the region of about 10,000 - 12,000 times that of the AC signal appearing at the Base of the first stage. the Base of this first stage is connected to a low impedance dynamic mic of about 600 Ohms, the input signal being in the strength of around 1 x 10^ - 4 of an Ampere, a very small signal indeed. The 820K Ohm resistor coupling the emitter of the second stage to the Base of the first creates a stable environment for the AC audio signal to pass through. The 820pf Capacitor of the second stage reduces the high frequency response of the amplifier creating further stability. the AC audio signal now having many millivolts in strength appears at the cathode of the 10 Microfarrad capacitor that is connected to the output collector of the second stage. The AC Audio signal is now half wave rectified by two signal diodes whose output pulses pump up a 0.33 Microfarrad Electroylitic. capacitor. When the voltage at the Anode of this capacitor reaches approx 1. 7 Volts the output Darlington Pair is switched hard on and supplies the full 12 volts to the Relay thus energising it and creating a '1' at the input of this bit PA6. A I remains constant while the rectified AC Audio Signal still keeps the 0.33 Electroylitic charged and the Base of the 1" stage of the Darlington Pair held positive and energised. but as soon as the telephone ring pauses the rectified AC Audio signal stops feeding the 0.33 Electroylitic capacitor and disables current flowing to the Darlington Pair, which in turn switches off the relay, now PA6 is connected to GND via a 47K resistor providing an effective 0 to be input to the bit. thus a telephone bell sound equals a I on PA6, and no telephone bell sound equals a 0 on PA6. it is the Mark and Space Ratio length of these I's and O's that the Z80 is able to recognise and convert to Binary data appropriately using its system software in the EPROM PA 7 - tput H!andshake bit use by the Z80 in comm io-nwith the PC.

of Y 0 (undecide et at thTe time of writi is whether or not to u ?AAWRODIY on the PIO, or for t 10 co t this bi ere. Will probably or the P 10 controls!) PA7 - Now used to illuminate or not, the LED display.

PART 1 CONCLIJDED ELAIMS 1. A Microprocessor based Computer Control Unit that attaches to a PC Computer and fully overides operation of the PC by a person.

2. A Microprocessor based Computer Control Unit as claimed in claim I that contains bi-directional communication circuits which allow all maner of Digital Ifformation to flow freely between this Microprocessor based Control Unit and the PC Computer.

3. A Microprocessor based Computer Control Unit as claimed in claims I and 2 that contains a built in 208 key internal PC Computer type Keyboard that is solely for the use of the Computer Control Unit's Microprocessor, allowing this Microprocessor to send all manner of keyboard control sequences to a PC Computer just as easily as a person can normally do using an ordinary Keyboard.

4. A Microprocessor based Computer Control Unit as claimed in any preceeding claims that utilises and reads all manner of Telephone Ringing Patterns enabling the Computer Control Unit to select any PC Software for the PC Computer. Accordingly, one Telephone Ring Pattern equals one Telephone Number which in turn equals one peice of PC Software the PC Computer must run each time this particular Ringing Pattern appears.

5. A Microprocessor based Computer Control Unit as claimed in any preceeding claim which is Wy programmable from a PC based programming platform. Programming allows the Microprocessor of the Computer Control Unit information about its user environment and the various infinite associatons of PC Software too each type of Telephone Ringing Pattern.

6. A Microprocessor based Computer Control Unit as claimed in any preceeding claim that totally disconnects and reconnects the full Mains Power Supply to the PC Computer, subject to it's own software control status.

7. A Microprocessor based Computer Control Unit as claimed in any preceeding claim that is so versatile, with a small amount of re programming, can be used to enable a Telephone distress call upon the triggering of various Input Sensors such as PIR and the like.