GB2334649A - Combined coding and decoding apparatus and method for time-division multiple access - Google Patents

Abstract

A coding and decoding device for time-division multiple access portable radio terminal equipment, including a code stream and frame number register storing a 64-bit code stream and 22-bit frame numbers; a coding and decoding component that codes the data to be transmitted and decodes the received data upon application of a code stream and a frame number in series from the code stream and frame number register; and a controller producing a second clock signal that provides 86 clock cycles for the code stream and frame number register and a third clock signal that is applied to the coding and decoding component for 100 clock cycles from the 87th clock cycle for running the coding and decoding component, 114 clock cycles from the 187th clock cycle for reception, and 114 clock cycles from the 301st clock cycle for transmission, upon application of a reference clock signal.

Description

COMBINED CODING AND DECODING APPARATUS AND METHOD FOR TIME-DIVISION MULTIPLE ACCESS BACKGROUND OF THE INVENTION The present invention relates to a combined coding and decoding apparatus and method for time-division multiple access data processing. More particularly, it relates to a data processing system for a portable radio terminal equipment of increased efficiency and performance in coding and decoding of data.

Conventional portable terminal equipment utilising the European time division multiple access technique (generalised sequential machine; GSM) includes a coder and a decoder.

FIG. 1 depicts the structure of a TDMA frame consisting of 8 time slots (0-7). As shown in FIG. 1, eight people can use one TMDA frame at a time. The set of intervals between a reception (Rx) time slot (0) and a transmission (Tx) time slot (3) that a person can use consists of 2 time slots (1, 2).

FIG. 2 is a block diagram of receiving and transmitting paths of conventional portable radio terminal equipment.

A decoder 30 is included in the receiving path, and a coder 40 is included in the transmitting path. The coder and decoder are separate circuits yet typically use a same algorithm (e.g. they may use one of the algorithms known as A51 or A52). Alternatively, the coder and decoder may create data in advance, used for coding and decoding, and store the coded information in an auxiliary memory for further use. Such an arrangement is common because both the coder and decoder each establishes a timing control with blocks performing different functions.

Specifically, in a typical implementation, 186 clock cycles per frame are required for coding or decoding. 86 clock cycles are needed in order to produce a 22-bit input frame number and 64-bit code stream from the coder or decoder. Subsequently, the coder or decoder operates for 100 clock cycles while the data held in the coder or decoders register is prepared for use in actual coding or decoding. While the code stream has not changed, the frame number changes for each frame, and the coder or decoder must recreate data for coding or decoding with every changed value.

After application of the 186 clock cycles, decoded data for the input data of the 114 clock cycles from the 187th clock cycle to a 300th clock cycle is obtained from the decoder in the receiving path.

In the transmission path, coded data for the 114 clock cycles from the 301st clock cycle to the 414th clock cycle are obtained from the coder of the transmitting path after standing by until the 300th clock cycle.

As the coder and the decoder operate independently, as separate circuits, 300 clock cycles are required to receive 114 clock cycles of data, and 414 clock cycles are required to transmit 114 clock cycles of data. These periods operate independently of each other, so to receive and transmit 114 clock cycles of data will require 300+414=714 clock cycles.

Both the coder and decoder need 186 clock cycles for coding and decoding.

The present invention aims to reduce the number of clock cycles required for coding and decoding, and so improve efficiency and performance of portable radio terminal equipment.

SUMMARY OF THE INVENTION The present invention provides TDMA radio terminal equipment in which the components performing coding and decoding of data are combined into one. The invention also provides a method for decoding and coding received data and transmitted data in such time division multiple access radio terminal equipment.

Accordingly, the present invention provides a method for decoding and coding received data and transmitted data for time division multiple access radio terminal equipment, comprising the steps of: - providing a combined coding and decoding means; - supplying code stream and frame number data to the coding and decoding means during a first number A+B of clock cycles; - preparing for coding and decoding, using the supplied code stream and frame number data in the coding and decoding means, during a second number C of clock cycles; - decoding received data during a third number D of clock cycles; and - coding data to be transmitted, during a fourth number E of clock cycles, wherein the steps are all performed within a total number A+B+C+D+E of clock cycles equal to the sum of the first, second, third and fourth numbers.

The step of coding data to be transmitted preferably follows the step of decoding received data.

The providing and preparing steps are preferably followed by the decoding and coding steps.

The step of coding may comprise logically combining data from the coding and decoding means with the received data, and the step of decoding may comprise logically combining data from the coding and decoding means with the data to be transmitted. Logically combining may comprise performing and exclusive-OR operation.

The present invention also provides apparatus for decoding and coding received data and transmitted data in time division multiple access radio terminal equipment, comprising: - a combined decoding and coding means; - means for supplying code stream and frame number data to the coding and decoding means during a first number A+B of clock cycles; - means for preparing for coding and decoding, using the supplied code stream and frame number data in the coding and decoding means, during a second number C of clock cycles; - means for decoding received data during a third number D of clock cycles; and - means for coding data to be transmitted, during a fourth number E of clock cycles, wherein the supplying, using, decoding and coding may all be performed within a total number A+B+C+D+E of clock cycles equal to the sum of the first, second, third and fourth numbers.

The apparatus may further comprise: - control means for producing: - the first number A+B of clock cycles to the means for supplying, to time the supply of the code stream and frame number data to the coding and decoding means; - the second number C of clock cycles from the A+B+l'th clock cycle, to the coding and decoding means, for preparing for decoding and coding, in the coding and decoding means; - the third number D of clock cycles from the A+B+C+l'th clock cycle, to the coding and decoding means, for decoding the received data; and - the fourth number E of clock cycles from an A+B+C+D+l'th clock cycle, to the coding and decoding means, for coding the data to be transmitted.

The apparatus may further comprise: - clock means for supplying a reference clock signal; - means for supplying second and third clock signals in accordance with the reference clock signal, wherein the second clock signal is used for the first number A+B of clock cycles supplied to the means for supplying, and the third clock signal is used for the second, third and fourth numbers of clock cycles supplied to the coding and decoding means.

The clock means may form a part of a supervising control means. The means for supplying may comprise a code stream and frame number register for storing the code stream and frame number data for supply to the coding and decoding means.

The control means may produce a reset signal for resetting the coding and decoding means for every timedivision multiple access frame.

The code stream and the frame number data are preferably provided serially to the coding and decoding means.

In a particular embodiment of the invention, A=64, B=22, C=100, D=114 and E=114.

Preferably, coding is performed only when a transmission control signal is at an active level.

Preferably, decoding is performed only when a reception control signal is at an active level.

The present invention also provides portable radio terminal equipment, comprising coding and decoding apparatus as described.

BRIEF DESCRIPTION OF THE DRAWINGS Certain embodiments of the present invention will now be described, by way of examples only, with reference to the accompanying drawings in which: FIG. 1 depicts the structure of a TDMA frame consisting of 8 time slots; FIG. 2 is a block diagram of transmitting and receiving paths of conventional portable radio terminal equipment; FIG. 3 is a block diagram of the transmitting and receiving paths of portable radio terminal equipment in accordance with the present invention; and FIG. 4 is a block diagram of the coding and decoding device of FIG. 3.

DETAILED DESCRIPTION OF THE INVENTION According to an embodiment of the present invention, a coder and a decoder are combined into a single device used for both transmission and reception, by exact scheduling of transmission time and reception time, Typically, most of channel processing is performed in a digital signal processor (DSP) through software, and blocks needing lots of clock cycles, such as a Viterbi equaliser, are realised using hardware.

FIG. 3 is a block diagram of the transmitting and receiving paths of portable radio terminal equipment in accordance with an embodiment of the present invention.

Unlike the conventional art illustrated in FIG. 2, the coder and decoder are combined into a single coding and decoding device 50, which is connected to both the transmitting path and the receiving path.

FIG. 4 is a block diagram of the coding and decoding device of FIG. 3.

According to an aspect of the invention, a code stream and frame number register 100 is provided, to hold code stream and frame numbers.

A coding and decoding component 200 codes the data to be sent and decodes the received data according to the code stream and a frame number stored in the code stream and frame number register 100, and supplied to the coding and decoding component 200. The code stream and frame number are preferably provided serially to the coding and decoding component 200.

A controller 300 controls coding and decoding. A first clock signal CLK1, a first reset signal RST1, a transmission control signal Tx~t, and a reception control signal Rx~t are supplied to controller 300. First clock signal CLK1 is provided by a supervising controller to controller 300, and controller 300 generates second and third clock signals CLK2 and CLK3 from first clock signal CLK1. Second clock signal CLK2 is used for providing 86 clock cycles to code stream and frame number register 100. Third clock signal CLK3 is used for providing data from the 87th to the 186th clock cycles to coding and decoding component 200.

Code stream and frame number register 100 applies 86 data bits SD, comprising the frame number and the code stream, synchronised with second clock signal CLK2, to coding and decoding component 200. After input of the data, coding and decoding component 200 operates for 100 clock cycles that are produced by third clock signal CLK3 after the first 86 cycles are completed, thus preparing the data for use in performing the actual coding and decoding.

If reception control signal Rx~t is applied, an exclusive OR operation is performed (feature 13 of Fig. 3) with the data produced by coding and decoding component 200 and data produced by Viterbi equaliser and decoder (shown as feature 12 of FIG. 3). The operation is carried out on 114-bits of data from the 187th clock cycle to the 300th clock cycle.

Once transmission control signal Tx~t is applied after receiving data, an exclusive OR operation (feature 18 of Fig. 3) is performed with respect to 114-bits of data from the 301st to 414th clock cycle, output by interleaver 19 of Fig. 3, thus coding the data. If there is a transmission of data without reception of data, after standing by until the 300th clock cycle, coded data for the clock cycles from the 301st to 414th clock cycle are obtained.

Therefore, according to an aspect of the present invention, receiving, transmitting or transmitting and receiving 114 clock cycles of data will take no longer than 414 clock cycles. This is a significant improvement over the conventional systems described above, which required up to 714 clock cycles for transmitting and receiving 114 clock cycles of data.

The number of clock cycles required to perform the various tasks, and the operation of the coding and decoding device for time-division multiple access portable radio terminal equipment according to the present invention may be generalised as follows.

A clock means is provided for supplying a reference clock signal. Coding and decoding means are provided for coding data to be transmitted and decoding received data. A code stream of bit length A and a frame number of bit length B are supplied to the coding and decoding means for use in the coding and decoding. Control means are preferably provided for producing second and third clock signals.

The second clock signal is preferably used to provide A+B clock cycles to time the application of the code stream and frame number. The third clock signal may be used for applying, to the coding and decoding means,: a number C of clock cycles from the A+B+l'th clock cycle for operating the coding and decoding means; a number D of clock cycles from the A+B+C+l'th clock cycle for decoding received data; and a number E of clock cycles from an A+B+C+D+l'th clock cycle for coding of data to be transmitted. These clock signals are preferably provided in accordance with the reference clock signal.

First reset signal RST1, input to controller 300, is used for resetting the overall system, and second reset signal RST2 from controller 300 is used to reset coding and decoding component 200 for each TDMA frame. If the frame number is increased, new coded and decoded data is generated using the increased frame number.

The present invention combines a coder and a decoder into one block, thus there is no need to have the hardware necessary for individual operation of the coder and the decoder. In addition, there is no need to repeat clock cycles 1-186 in the transmission path, nor to systematically stand by for the 114 clock cycles used to represent received data, so the present invention reduces the required clock cycles to 414 clock cycles from 714 clock cycles, eliminating 300 clock cycles.

Although the present invention has been described with reference to a limited number of particular embodiments, many variations and modifications to the apparatus of the invention are possible. For example, the invention may be applied to radio equipment other than portable radio terminal equipment. The respective bit lengths of the code stream, frame number, coding/decoding operation, reception or transmission periods may be chosen at will, for compatibility with particular transmission standards.

Although the invention has been described with reference to a code stream and frame number register, for supplying the code stream and frame number, other equivalent means may be substituted.

Claims (19)

1. CLAIMS 1. A method for decoding and coding received data and transmitted data for time division multiple access radio terminal equipment, comprising the steps of: - providing a combined coding and decoding means; - supplying code stream and frame number data to the coding and decoding means during a first number A+B of clock cycles; - preparing for coding and decoding, using the supplied code stream and frame number data in the coding and decoding means, during a second number C of clock cycles; - decoding received data during a third number D of clock cycles; and - coding data to be transmitted, during a fourth number E of clock cycles, wherein the steps are all performed within a total number A+B+C+D+E of clock cycles equal to the sum of the first, second, third and fourth numbers.
2. 2. A method according to claim 1 wherein the step of coding data to be transmitted follows the step of decoding received data.
3. 3. A method according to claim 1 or claim 2 wherein the providing and preparing steps are followed by the decoding and coding steps.
4. 4. A method according to any preceding claim wherein the step of coding comprises logically combining data from the coding and decoding means with the received data.
5. 5. A method according to any preceding claim wherein the step of decoding comprises logically combining data from the coding and decoding means with the data to be transmitted.
6. 6. A method according to claim 4 or claim 5 wherein logically combining comprises performing and exclusive-OR operation.
7. 7. Apparatus for decoding and coding received data and transmitted data for time division multiple access radio terminal equipment, comprising: - a combined decoding and coding means; - means for supplying code stream and frame number data to the coding and decoding means during a first number A+B of clock cycles; - means for preparing for coding and decoding, using the supplied code stream and frame number data in the coding and decoding means, during a second number C of clock cycles; - means for decoding received data during a third number D of clock cycles; and - means for coding data to be transmitted, during a fourth number E of clock cycles, wherein the supplying, using, decoding and coding may all be performed within a total number A+B+C+D+E of clock cycles equal to the sum of the first, second, third and fourth numbers.
8. 8. Apparatus for decoding and coding according to claim 7, further comprising: - control means for producing: - the first number A+B of clock cycles to the means for supplying, to time the supply of the code stream and frame number data to the coding and decoding means; - the second number C of clock cycles from the A+B+l'th clock cycle, to the coding and decoding means, for preparing for decoding and coding, in the coding and decoding means; - the third number D of clock cycles from the A+B+C+l'th clock cycle, to the coding and decoding means, for decoding the received data; and - the fourth number E of clock cycles from an A+B+C+D+l'th clock cycle, to the coding and decoding means, for coding the data to be transmitted.
9. 9. Apparatus according to claim 8, further comprising: - clock means for supplying a reference clock signal; - means for supplying second and third clock signals in accordance with the reference clock signal, wherein the second clock signal is used for the first number A+B of clock cycles supplied to the means for supplying, and the third clock signal is used for the second, third and fourth numbers of clock cycles supplied to the coding and decoding means.
10. 10. Apparatus according to claim 9 wherein the clock means forms a part of a supervising control means.
11. 11. Apparatus according to any of claims 7-9, wherein the means for supplying comprises a code stream and frame number register for storing the code stream and frame number data for supply to the coding and decoding means.
12. 12. Apparatus according to any of claims 8-10 wherein the control means produces a reset signal for resetting the coding and decoding means for every time-division multiple access frame.
13. 13. An apparatus or a method according to any preceding claim wherein the code stream and the frame number data are provided serially to the coding and decoding means.
14. 14. An apparatus or a method according to any preceding claim in which A=64, B=22, C=100, D=114 and E=114.
15. 15. An apparatus or a method according to any preceding claim wherein the step of coding is performed only when a transmission control signal is at an active level.
16. 16. An apparatus or a method according to any preceding claim wherein the step of decoding is performed only when a reception control signal is at an active level.
17. 17. An apparatus for coding and decoding data for timedivision multiple access portable radio terminal equipment substantially as described and/or as illustrated in Figs. 3-4 of the accompanying drawings.
18. 18. Radio terminal equipment, comprising apparatus according to any of claims 7-17.
19. 19. A method for coding and decoding data for timedivision multiple access portable radio terminal equipment substantially as described and/or as illustrated in Figs. 3-4 of the accompanying drawings.