GB2333268A - Selective anisotropic plasma etching of a silicon nitride film using CO and a CHF gas at reduced substrate temperature - Google Patents
Selective anisotropic plasma etching of a silicon nitride film using CO and a CHF gas at reduced substrate temperature Download PDFInfo
- Publication number
- GB2333268A GB2333268A GB9901151A GB9901151A GB2333268A GB 2333268 A GB2333268 A GB 2333268A GB 9901151 A GB9901151 A GB 9901151A GB 9901151 A GB9901151 A GB 9901151A GB 2333268 A GB2333268 A GB 2333268A
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- United Kingdom
- Prior art keywords
- gas
- etching method
- film
- dry etching
- silicon nitride
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- General Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Plasma & Fusion (AREA)
- Drying Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
A silicon nitride film 13 is preferentially plasma etched with respect to a silicon oxide film 12 and polysilicon 11 using CO together with CHF 3 or H 2 and CHF 3 , CF 4 or C 2 F 6 with the substrate temperature being 10‹C or less. O 2 , an inert gas or N 2 may also be present.
Description
ANISOTROPIC DRY ETCHING METHOD
BACKGROUND OF THE INVENTION
Field of the Invention
The present invention relates to an anisotropic dry etching method for selectively anisotropically dry etching a silicon nitride film with respect to a silicon oxide film, a polysilicon film and a silicon film.
Description of the Related Art
In conventional methods of dry etching a silicon nitride film, SF6 gas is used as described in, for example,
Japanese Patent Application Laid-Open No. 8-321484 and NF3,
Cl2 and the like are used as described in, for example,
Japanese Patent Application Laid-Open No. 6-181190.
According to those conventional techniques, it is possible to selectively etch a silicon nitride film with respect to a silicon oxide film. However, since a silicon etch rate is fast, it is not possible to selectively etch a silicon nitride film with respect to a silicon film. When using a mixed gas of, for example, CHF3 or CF4 and H2, the etch rate of silicon can be reduced and the silicon nitride film can be selectively etched with respect to silicon.
Use of such a mixed gas, however, results in an increase in the etch rate of the silicon oxide film, as well. It has been, thus, difficult to etch a silicon nitride film having a high etch selectivity with respect to both a silicon film and a silicon oxide film.
With the technical background as stated above
Japanese Patent Application Laid-Open Nos. 59-222933 and 60-115232 disclose the technique of using gas having a F to H composition ratio of 2 or less such as CH2F2 and CHF as a method for selectively etching a silicon nitride film with respect to a silicon film and a silicon oxide film.
That is, these references teach that the silicon nitride film can be selectively etched with respect to both the silicon film and the silicon oxide film by using a gas of a F to H composition ratio of 2 or less.
The gas having a F to H composition ratio of 2 or less, however, is in a range of explosion and, thus, has a disadvantage in that it is difficult to handle.
SUMMARY OF THE INVENTION
An anisotropic dry etching method according to the present invention is a method for selectively anisotropically dry etching a silicon nitride film with respect to a silicon oxide film, a polysilicon film and a silicon film. The anisotropic dry etching method according to the present invention is characterized in that a substrate temperature is set at 10 C or less, a mixed gas of a compound gas containing fluorine, carbon and hydrogen and carbon monoxide is used as a reactive gas.
Advantageously, the present invention may therefore provide an anisotropic dry etching method capable of selectively, anisotropically dry etching a silicon nitride film with respect to all of the silicon oxide film, the polysilicon film and the silicon film.
In this anisotropic dry etching method, it is preferable that the compound gas containing fluorine, carbon and hydrogen is either a mixed gas of at least one selected from the group consisting of CHF3, CF4 and C2F6 and hydrogen gas or CHF3 gas. It is also preferable that a mixture ratio of CO gas to a total gas flow rate of the reactive gas is 70 to 95 volume %.
According to the present invention, there is no need to particularly use, as a compound gas containing fluorine, carbon and hydrogen, simple gas having a F to H composition ratio of 2 or less such as CH2F2 and CHaF Thus, the present invention is not restricted by the F to H composition ratio.
BRIEF DESCRIPTION OF THE DRAWING
FIG. 1 is a graph showing the relationship between substrate temperature and etch rates of respective films to describe the principle of the present invention;
FIG. 2 is a cross-sectional view showing an embodiment of applying the present invention to contact hole etching in the order of steps; and
FIG. 3 is a cross-sectional view showing an embodiment of applying the present invention to groove etching in the order of steps.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
Embodiments of the present invention will now be described in detail with reference to the accompanying drawings. Description will be given first to a silicon nitride film and the etch selectivity of the silicon nitride film with respect to other silicon oxide films and silicon films. FIG. 1 is a graph showing the relationship between substrate temperature and etch rates of respective films, with the axis of abscissas indicating the substrate temperature and the axis of ordinates indicating the film etch rate. The etch rates were measured using a parallel plate dry etching system. CHEF3 was used as a compound gas containing gaseous fluorine, carbon and hydrogen. Using a mixed gas of the CHF3 and CO gas as a reactive gas, etch rates of a silicon nitride film, a polysilicon film and a silicon oxide film were measured while changing the substrate temperature. At a substrate temperature of 500C to 1000C at which etching has been conventionally conducted, the etch rate of the silicon nitride film is slow and it is impossible to selectively etch the silicon nitride film with respect to, in particular, the silicon oxide film. As the substrate temperature was decreased, the etch rate of the silicon nitride film rapidly increased. The etch rate of the polysilicon film and that of the silicon oxide film increased slightly and far slower than that of the silicon nitride film. At a substrate temperature of 500C or less, the etch rate of the silicon nitride film increased surprisingly. At a substrate temperature of 100C or less, the etch selectivity of the silicon nitride film with respect to the silicon oxide film was 5 or more. Further, since the etch rate of the polysilicon film was far slower, it was possible to etch the silicon nitride film with etch selectivity of 10 or more with respect to the polysilicon film.
It is considered that the reason the etch rate of the silicon nitride film increases as the substrate temperature decreases is that the lower temperature of the substrate causes reaction products to be easily generated.
In other words, when CO is added, fluorine is taken out in the form of COF and plasma lacking in fluorine occurs.
Besides, as the substrate temperature decreases, the quantity of CXHy, which is decomposed or generated from fluorocarbon gas such as CHF2, adhering to the substrate increases. If so, HCN which is a reaction product increases in quantity and is exhausted, with the result that the etch rate of the silicon nitride film increases.
On the other hand, when CO is added, F becomes insufficient in quantity on the silicon oxide film. As a result, the etch rate of the silicon oxide film decreases.
The deposition of carbon rich polymerized films of high ion impact resistance on the polysilicon film or the silicon film, when CO is added, is accelerated. Since the deposited films protect the silicon surface, it is considered that the etch rate of the polysilicon film and that of the silicon film are slow.
As regards a mixture ratio of CHF3 to CO, it was discovered that CO gas needs to be added by 70% or more of the overall gas flow rate to generate plasma lacking in fluorine and to suppress the etch rate of the silicon oxide film to low level.
Next, description will be given to an anisotropic dry etching method embodying the present invention,
based on the principle stated above. FIGS. 2A through 2E are cross-sectional views showing the first embodiment in the order of steps. In the first embodiment, the anisotropic dry etching method embodying the present invention is employed to remove the nitride film of a self-aligned contact with the nitride film used as a stopper.
First, as shown in FIG. 2A, a silicon oxide film 2, a polysilicon film 3 and a silicon oxide film 4 are sequentially deposited on a silicon substrate 1. After forming a resist (not shown), the resist is patterned.
Using the resist as a mask, the silicon oxide film 2, the polysilicon film 3 and the silicon oxide film 4 are subjected to anisotropic dry etching, thereby forming an electrode wiring.
Next, as shown in FIG. 2B, a silicon oxide film 5 is deposited on the entire surface. The silicon oxide film 5 is subjected to anisotropic etch-back thereby to form a sidewall on the side surface of the wiring.
As shown in FIG. 2C, a silicon nitride film 6 serving as an etching stopper is then deposited on the entire surface and an interlayer insulating film 7, such as a BPSG film, is formed. Thereafter, a contact hole pattern is formed with a resist 8.
Subsequently, as shown in FIG. 2D, using the resist 8 as a mask, the interlayer insulating film 7 is subjected to an anisotropic dry etching and a contact hole 9 is formed to such an extent as to reach the silicon nitride film 6 serving as a stopper.
As shown in FIG. 2E, the silicon nitride film 6 exposed to the interior of the contact hole 9 is then removed and a hole is formed in the silicon substrate 1.
The embodiment of the present invention is applied to the removal of the silicon nitride film 6. Namely, the silicon nitride film 6 is selectively etched with respect to the silicon oxide film 5 and the silicon substrate 1 at the same time.
In other words, an etching is conducted, for example, for 90 seconds with CHF gas of 10 sccm, CO gas of 90 sccm, pressure of 40 mTorr, high frequency (RF) powex of 150 w and at a substrate temperature of 100C. As a result of the etching process, the silicon nitride film 6 within the contact hole 9 is selectively removed. At this time, since the silicon nitride film can be selectively etched with respect to the silicon oxide film 5 and the silicon substrate 1 according to the present invention, the silicon oxide film 5 and the silicon substrate 1 are cut less in quantity. Thereafter, a conductive material is buried into the contact hole 9 to provide continuity between the substrate and the upper wiring layer. In this case, a contact hole can be formed in a stable manner by self-aligned contact without short-circuiting the electrode wiring with the conductive material and without the need to dig deeply the silicon substrate.
FIGS. 3A through 3C are cross-sectional views showing the second embodiment of the present invention in the order of steps, in which a method embodying the present invention is applied to the groove formation step of forming a groove wiring on a contact plug of polysilicon.
First, as shown in FIG. 3A, a contact plug 11 of polysilicon is formed in an oxide film 12 deposited on a silicon substrate 10. Thereafter, a silicon nitride film 13 serving as an etching stopper and a silicon oxide film 14 serving as an interlayer film are sequentially deposited and further a groove wiring pattern is formed with a resist 15.
As shown in FIG. 3B, using the resist 15 as a mask, an anisotropic dry etching is then conducted to the silicon oxide film 14 and a groove is formed to such an extent as to reach the silicon nitride film 13 serving as a stopper.
Thereafter, as shown in FIG. 3C, using the resist 15 as a mask, the silicon nitride film 13 is removed thereby to expose the polysilicon plug 11. The present embodiment is applied to the removal of the silicon nitride film 13.
Namely, the silicon nitride film 13 is selectively etched with respect to the silicon oxide film 12 and the polysilicon plug 11 at the same time. The same etching conditions as those in the first embodiment are employed.
Thus, the silicon nitride film 13 is removed. Here, since the silicon nitride film 13 can be selectively etched with respect to the silicon oxide film 12 and the polysilicon plug 11, the silicon oxide film 12 and the polysilicon plug 11 are cut less and it is thereby possible to flatten the bottom of the groove. Accordingly, later wiring formation can be conducted in a stable manner.
Needless to say, the present invention should not be limited to the above-stated embodiments. In the embodiments, a mixed gas of compound gas containing carbon, hydrogen and fluorine, and CO is used. For example, a small quantity of oxygen gas, rare gas (inert gas) or nitrogen gas may be added to the mixed gas so as to enhance etching removability.
As described so far, according to the preferred embodiments of the present invention, by setting substrate temperature at 100C or less and by using a mixed gas of compound gas containing fluorine, carbon and hydrogen, and carbon monoxide (CO) as reactive gas, the silicon nitride film may advantageously be selectively anisotropically dry etched with respect to all of the silicon oxide film, the polysilicon film and the silicon film. Thus, the present invention may realize a semiconductor device structure which has been conventionally difficult to realize.
Claims (11)
1. An anisotropic etching method comprising the step of selectively anisotropically dry etching a silicon nitride film with respect to a silicon oxide film, a polysilicon film and a silicon film, said etching being conducted under conditions that a substrate temperature is 100C or less and a mixed gas of a compound gas containing fluorine, carbon and hydrogen, and carbon monoxide is used as a reactive gas.
2. The anisotropic dry etching method according to claim 1, wherein said compound gas containing fluorine, carbon and hydrogen is either a mixed gas of hydrogen gas and at least one selected from the group consisting of
CHF3, CF4 and C2F6 gas or CHF3 gas.
3. The anisotropic dry etching method according to claim 1, wherein a mixture ratio of CO gas to a total gas flow rate of the reactive gas is 70 to 95 volume %.
4. The anisotropic dry etching method according to claim 2, wherein a mixture ratio of CO gas to a total gas flow rate of the reactive gas is 70 to 95 volume %.
5. The anisotropic dry etching method according to claim 1, wherein a gas selected from the group consisting of oxygen gas, rare gas and nitrogen gas is added to said compound gas containing fluorine, carbon and hydrogen.
6. The anisotropic dry etching method according to claim 2, wherein a gas selected from the group consisting of oxygen gas, rare gas and nitrogen gas is added to said compound gas containing fluorine, carbon and hydrogen.
7. The anisotropic dry etching method according to claim 3, wherein a gas selected from the group consisting of oxygen gas, rare gas and nitrogen gas is added to said compound gas containing fluorine, carbon and hydrogen.
8. The anisotropic dry etching method according to claim 4, wherein a gas selected from the group consisting of oxygen gas, rare gas and nitrogen gas is added to said compound gas containing fluorine, carbon and hydrogen.
9. An etching method comprising the step of
anisotropically dry etching a silicon nitride film at a
substrate temperature of 100C or less using as a reactive gas a
mixture of carbon monoxide and a gas containing fluorine, carbon
and hydrogen.
10. An etching method substantially as described herein
with reference to the drawings.
11. A semiconductor device manufactured using an etching
method as defined in any preceding claim.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10009096A JPH11214355A (en) | 1998-01-20 | 1998-01-20 | Anisotropic dry etching method |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| GB9901151D0 GB9901151D0 (en) | 1999-03-10 |
| GB2333268A true GB2333268A (en) | 1999-07-21 |
| GB2333268B GB2333268B (en) | 2000-01-19 |
Family
ID=11711094
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB9901151A Expired - Fee Related GB2333268B (en) | 1998-01-20 | 1999-01-19 | Anisotropic dry etching method |
Country Status (5)
| Country | Link |
|---|---|
| JP (1) | JPH11214355A (en) |
| KR (1) | KR19990067997A (en) |
| CN (1) | CN1113396C (en) |
| GB (1) | GB2333268B (en) |
| TW (1) | TW440942B (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2001017007A1 (en) * | 1999-08-27 | 2001-03-08 | Tokyo Electron Limited | Method of etching and method of plasma treatment |
| US7504338B2 (en) | 2002-10-31 | 2009-03-17 | Applied Materials, Inc. | Method of pattern etching a silicon-containing hard mask |
| WO2012047459A3 (en) * | 2010-09-28 | 2012-06-07 | Tokyo Electron Limited | Selective etch process for silicon nitride |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002252222A (en) * | 2001-02-22 | 2002-09-06 | Nec Corp | Method of manufacturing semiconductor device and semiconductor device |
| JP5466756B2 (en) * | 2010-03-04 | 2014-04-09 | 東京エレクトロン株式会社 | Plasma etching method, semiconductor device manufacturing method, and plasma etching apparatus |
| CN103779203B (en) * | 2012-10-17 | 2016-11-02 | 株式会社日立高新技术 | Plasma etching method |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4529476A (en) * | 1983-06-01 | 1985-07-16 | Showa Denko K.K. | Gas for selectively etching silicon nitride and process for selectively etching silicon nitride with the gas |
| GB2165992A (en) * | 1984-10-23 | 1986-04-23 | Sgs Microelettronica Spa | Reduced-beak planox process for the formation of integrated electronic components |
| US5643473A (en) * | 1987-07-31 | 1997-07-01 | Hitachi, Ltd. | Dry etching method |
-
1998
- 1998-01-20 JP JP10009096A patent/JPH11214355A/en active Pending
-
1999
- 1999-01-16 TW TW088100636A patent/TW440942B/en not_active IP Right Cessation
- 1999-01-19 KR KR1019990001533A patent/KR19990067997A/en not_active Ceased
- 1999-01-19 CN CN99100230A patent/CN1113396C/en not_active Expired - Fee Related
- 1999-01-19 GB GB9901151A patent/GB2333268B/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4529476A (en) * | 1983-06-01 | 1985-07-16 | Showa Denko K.K. | Gas for selectively etching silicon nitride and process for selectively etching silicon nitride with the gas |
| GB2165992A (en) * | 1984-10-23 | 1986-04-23 | Sgs Microelettronica Spa | Reduced-beak planox process for the formation of integrated electronic components |
| US5643473A (en) * | 1987-07-31 | 1997-07-01 | Hitachi, Ltd. | Dry etching method |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2001017007A1 (en) * | 1999-08-27 | 2001-03-08 | Tokyo Electron Limited | Method of etching and method of plasma treatment |
| US6780342B1 (en) | 1999-08-27 | 2004-08-24 | Tokyo Electron Limited | Method of etching and method of plasma treatment |
| US7211197B2 (en) | 1999-08-27 | 2007-05-01 | Tokyo Electron Limited | Etching method and plasma processing method |
| US7504338B2 (en) | 2002-10-31 | 2009-03-17 | Applied Materials, Inc. | Method of pattern etching a silicon-containing hard mask |
| WO2012047459A3 (en) * | 2010-09-28 | 2012-06-07 | Tokyo Electron Limited | Selective etch process for silicon nitride |
| US8501630B2 (en) | 2010-09-28 | 2013-08-06 | Tokyo Electron Limited | Selective etch process for silicon nitride |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1113396C (en) | 2003-07-02 |
| CN1224235A (en) | 1999-07-28 |
| GB2333268B (en) | 2000-01-19 |
| GB9901151D0 (en) | 1999-03-10 |
| KR19990067997A (en) | 1999-08-25 |
| TW440942B (en) | 2001-06-16 |
| JPH11214355A (en) | 1999-08-06 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PCNP | Patent ceased through non-payment of renewal fee |