GB2333178A - Forming capacitor electrodes for integrated circuits - Google Patents
Forming capacitor electrodes for integrated circuits Download PDFInfo
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- GB2333178A GB2333178A GB9800587A GB9800587A GB2333178A GB 2333178 A GB2333178 A GB 2333178A GB 9800587 A GB9800587 A GB 9800587A GB 9800587 A GB9800587 A GB 9800587A GB 2333178 A GB2333178 A GB 2333178A
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- Prior art keywords
- silicon
- hemispherical grain
- oxide layer
- hsg
- silicon oxide
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- 239000003990 capacitor Substances 0.000 title claims abstract description 19
- 238000000034 method Methods 0.000 claims abstract description 58
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 47
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 36
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 30
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 28
- KOPOQZFJUQMUML-UHFFFAOYSA-N chlorosilane Chemical compound Cl[SiH3] KOPOQZFJUQMUML-UHFFFAOYSA-N 0.000 claims abstract description 13
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 239000005046 Chlorosilane Substances 0.000 claims abstract description 10
- 239000002243 precursor Substances 0.000 claims abstract description 10
- 239000006227 byproduct Substances 0.000 claims abstract description 9
- 229920005591 polysilicon Polymers 0.000 claims abstract 3
- 239000010703 silicon Substances 0.000 claims description 20
- 229910052710 silicon Inorganic materials 0.000 claims description 19
- 239000002019 doping agent Substances 0.000 claims description 17
- 238000005229 chemical vapour deposition Methods 0.000 claims description 14
- XYFCBTPGUUZFHI-UHFFFAOYSA-N Phosphine Chemical compound P XYFCBTPGUUZFHI-UHFFFAOYSA-N 0.000 claims description 8
- 238000004519 manufacturing process Methods 0.000 claims description 7
- 239000000463 material Substances 0.000 claims description 7
- RBFQJDQYXXHULB-UHFFFAOYSA-N arsane Chemical group [AsH3] RBFQJDQYXXHULB-UHFFFAOYSA-N 0.000 claims description 6
- 235000012239 silicon dioxide Nutrition 0.000 claims description 6
- 239000000377 silicon dioxide Substances 0.000 claims description 6
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 claims description 5
- 238000000151 deposition Methods 0.000 claims description 5
- MROCJMGDEKINLD-UHFFFAOYSA-N dichlorosilane Chemical compound Cl[SiH2]Cl MROCJMGDEKINLD-UHFFFAOYSA-N 0.000 claims description 4
- 238000011065 in-situ storage Methods 0.000 claims description 4
- 229910000077 silane Inorganic materials 0.000 claims description 4
- FDNAPBUWERUEDA-UHFFFAOYSA-N silicon tetrachloride Chemical compound Cl[Si](Cl)(Cl)Cl FDNAPBUWERUEDA-UHFFFAOYSA-N 0.000 claims description 4
- ZDHXKXAHOVTTAH-UHFFFAOYSA-N trichlorosilane Chemical compound Cl[SiH](Cl)Cl ZDHXKXAHOVTTAH-UHFFFAOYSA-N 0.000 claims description 4
- 239000005052 trichlorosilane Substances 0.000 claims description 4
- 230000008021 deposition Effects 0.000 claims description 3
- 239000007789 gas Substances 0.000 claims description 3
- 230000000149 penetrating effect Effects 0.000 claims description 3
- 229910000073 phosphorus hydride Inorganic materials 0.000 claims description 3
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims 7
- 229910052739 hydrogen Inorganic materials 0.000 claims 7
- 239000001257 hydrogen Substances 0.000 claims 7
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 claims 6
- IXCSERBJSXMMFS-UHFFFAOYSA-N hydrogen chloride Substances Cl.Cl IXCSERBJSXMMFS-UHFFFAOYSA-N 0.000 claims 6
- 229910000041 hydrogen chloride Inorganic materials 0.000 claims 6
- VXEGSRKPIUDPQT-UHFFFAOYSA-N 4-[4-(4-methoxyphenyl)piperazin-1-yl]aniline Chemical compound C1=CC(OC)=CC=C1N1CCN(C=2C=CC(N)=CC=2)CC1 VXEGSRKPIUDPQT-UHFFFAOYSA-N 0.000 claims 1
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical group [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims 1
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 claims 1
- 229910052785 arsenic Inorganic materials 0.000 claims 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical group [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims 1
- 229910052796 boron Inorganic materials 0.000 claims 1
- 229910052801 chlorine Inorganic materials 0.000 claims 1
- 239000000460 chlorine Substances 0.000 claims 1
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 claims 1
- 238000000059 patterning Methods 0.000 claims 1
- 239000005049 silicon tetrachloride Substances 0.000 claims 1
- 229910021417 amorphous silicon Inorganic materials 0.000 abstract description 11
- 238000010899 nucleation Methods 0.000 abstract description 8
- 230000006911 nucleation Effects 0.000 abstract description 6
- 238000003860 storage Methods 0.000 description 11
- 230000007423 decrease Effects 0.000 description 6
- 239000010409 thin film Substances 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 4
- 239000004020 conductor Substances 0.000 description 4
- 238000000206 photolithography Methods 0.000 description 4
- 229910000070 arsenic hydride Inorganic materials 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 230000010354 integration Effects 0.000 description 3
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 3
- 230000008901 benefit Effects 0.000 description 2
- 229910052681 coesite Inorganic materials 0.000 description 2
- 229910052906 cristobalite Inorganic materials 0.000 description 2
- ZOCHARZZJNPSEU-UHFFFAOYSA-N diboron Chemical compound B#B ZOCHARZZJNPSEU-UHFFFAOYSA-N 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 229910052682 stishovite Inorganic materials 0.000 description 2
- 229910052905 tridymite Inorganic materials 0.000 description 2
- 229910015148 B2H6 Inorganic materials 0.000 description 1
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 125000003407 arsaniumyl group Chemical group [H][As+]([H])([H])[*] 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000007795 chemical reaction product Substances 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- PZPGRFITIJYNEJ-UHFFFAOYSA-N disilane Chemical compound [SiH3][SiH3] PZPGRFITIJYNEJ-UHFFFAOYSA-N 0.000 description 1
- 238000011534 incubation Methods 0.000 description 1
- 230000006698 induction Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 229910001936 tantalum oxide Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D1/00—Resistors, capacitors or inductors
- H10D1/60—Capacitors
- H10D1/68—Capacitors having no potential barriers
- H10D1/692—Electrodes
- H10D1/711—Electrodes having non-planar surfaces, e.g. formed by texturisation
- H10D1/712—Electrodes having non-planar surfaces, e.g. formed by texturisation being rough surfaces, e.g. using hemispherical grains
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/04—Coating on selected surface areas, e.g. using masks
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
- C23C16/24—Deposition of silicon only
Landscapes
- Chemical & Material Sciences (AREA)
- General Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Engineering & Computer Science (AREA)
- Materials Engineering (AREA)
- Mechanical Engineering (AREA)
- Metallurgy (AREA)
- Organic Chemistry (AREA)
- Inorganic Chemistry (AREA)
- Semiconductor Memories (AREA)
- Electrodes Of Semiconductors (AREA)
- Chemical Vapour Deposition (AREA)
Abstract
In a method for fabricating a hemispherical grain silicon structure as a bottom electrode of a capacitor in an integrated circuit, poly-silicon is formed as the seed for nucleation instead of amorphous silicon. A silicon oxide layer 24 provided with a contact hole 22 is formed on a substrate 20. The contact hole is filled with polysilicon and patterned to form a capacitor electrode 26. Native oxide on the electrode is removed by H 2 or HCI solution and then, using chlorosilane as a precursor, a hemispherical grain silicon structure 28 is grown on the electrode by CVD to increase its capacitance. The by-products H 2 and HCI of the reaction prevent growth of the structure 28 on the silicon oxide layer 24.
Description
METHOD FOR FABRICATWG STRUCTURE OF HEMISPHERICAL GRAIN
SILICON
CROSS-REFERENCE TO RELATED APPLICATION
This application claims priority benefit of Taiwan application Serial no. 86115362, filed
Oct., 18, 1997, the full disclosure of which is incorporated herein by reference.
BACKGROUND OF THE INVENTION Field of the Invention
The invention relates to a method for fabricating a capacitor in an integrated circuit (IC), and more particular to a method for fabricating a structure of hemispherical grain silicon (HSG-Si).
Description of the Related Art
In a DRAM, the typical method to access data is by charging or discharging optionally into each capacitor of the capacitor array on the semiconductor substrate.
Due to the higher and higher integration of IC, dimensions of devices or structures (such as transistors, capacitors) become smaller and smaller. Thus, in a conventional planar capacitor, the storage of charges (that is, the capacitance) decreases.
The decrease of charge storage causes various problems, including mechanical deterioration and charge leakage by the larger susceptibility, and therefore, causes potential loss. The charge leakage caused by larger susceptibility may cause more frequent refresh period, and by which, memory can not handle data saving and reading properly. Moreover, the decrease of charge storage may need more complex data reading plan, or more sensitive charge induction amplifier.
Up to now, there are three ways to solve the above problems caused by the decrease of capacitance of a capacitor due to the higher and high integration in a very large scaled integrated circuit. The first method is to reduce the thickness of the dielectric layer between two conductors in a capacitor. It is known that the capacitance is proportional to the inverse of the distance between two conductors in a capacitor.
Thus, the decrease of the thickness of dielectric layer increases the capacitance effectively.
However, according to the consideration of the uniformity and stability of the dielectric layer, this is a method difficult to control. The second method is to adapt the material with higher dielectric constant, such as tantalum oxide (Ta205) as the dielectric layer in a capacitor. The capacitance of a capacitor is proportional to the dielectric constant of the dielectric layer between two conductors. Thus, this is a direct method. However, due to the high leakage current and the low breakdown voltage of this material, this technique is still under development. The third method is to increase the surface area of the storage node of the capacitor. The capacitance is proportional to the surface area of storage node, that is, the conductor (electrode). Therefore, to increase the surface area of the storage node increases the capacitance as well. The very common structure for increasing the surface area is the fin-shape or box-shape structure. However, these structures are too complex for mass production. Another available method is to fabricate a structure of hemispherical grain as the electrode. The conventional method to form a HSG-Si electrode structure can be referred to "H. Ttoh et al. IEDM, 9(1994)", "M. Sakao et al. TEDM, 665 (1990)", "J. J. Rosato et al. J. Electrochem. Soc. Vol. 149,
No.12, 3678 (1992)", "H. Watanabe et al. WEE Trans. Elect. Devices, Vol.42, No.7, 1247 (1995)", "P. C. Fazan et al. IEDM, 663 (1990)", and "JP pat 5-315543" Fig.la and Fig.lb show a conventional method for forming HSG-Si. Firstly, referring to Fig. 1 a, on a substrate 10 having a silicon oxide layer 14 formed thereon, and a contact hole 12 filled with poly-silicon penetrating through the silicon oxide layer 14, using low pressure chemical vapour deposition (LPCVD), an amorphous silicon thin film 16 is formed uniformly. Being patterned by photolithography and reactive ion etching (RIE), the amorphous silicon thin film 16 is then dipped into a dilute hydrogen fluoride (HF) solution to remove the native oxide layer 18 grown on the surface of the amorphous silicon thin film 16. The amorphous silicon thin film becomes a very pure seed for nucleation.
Referring to Fig. ib, in an ultra-high vacuum (UHV) annealing process, a molecular beam of disilane (Si2Hs) is radiated onto the amorphous silicon thin film 16 on the substrate 10, and the anneal is performed. Therefore, the silicon atoms within the amorphous silicon thin film migrate and a hemispherical grain (HSG) structure 1 6a is formed on the surface.
While applying the above method to form HSG-Si electrode structure in a DRAM, the obtained capacitance is only 1.8 times of a normal flat electrode. In addition, after the HSG-Si is grown, the subsequent etch back process increases the capacitance up to 30% to 50%.
SUMMARY OF THE INVENTION
It is therefore an object of the invention to provide a method for fabricating a
HSG-Si structure as a storage node, that is, a storage electrode, of a capacitor in an integrated circuit. The capacitor with the electrodes fabricated by the method has large capacitance and can be used in the integrated circuit with high integration.
It is therefore another object of the invention to provide a method for fabricating a
HSG-Si structure with a higher growing. In the invention, the poly-silicon with higher growing speed is used as a seed for nucleation instead ot Dure amorphous silicon.
Therefore, steps of the time consuming deposition and seeding of amorphous silicon, and the UHV process are skipped. The process is simplified, and the cost for fabrication is reduced.
To achieve these objects and advantages, and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention is directed towards a method for fabricating a hemispherical grain silicon structure as a storage node, that is, a storage electrode of a capacitor in an IC. A substrate having a silicon oxide layer and a contact hole formed thereon is provided. The silicon oxide layer is penetrated by the contact hole, and the contact hole is filled with poly-silicon as a contact plug. Using
LPCVD, a poly-silicon layer is formed on the substrate. The poly-silicon layer is then patterned by conventional photolithography and etching process to cover the contact hole and part of the silicon oxide layer. The native silicon oxide layer on the surface of the poly-silicon layer is removed by H2 or HC1 solution. Using silane or chlorosilane as the precursor, a HSG-Si structure is grown on the surface by chemical vapour deposition.
The by-product produced during the formation ofthe HSG-Si structure, such as, HC1, or the additional HC1 and H2 is reacted with the silicon oxide. Therefore, the possibility of growing HSG-Si on the silicon oxide layer is suppressed. That is, HCI can be used as an etchant, to adjust the selectivity for the growth of grain on the poly-silicon layer and the silicon oxide layer. During growth, arsine (AsH3) or phosphine (PH3) can be added as an N-type dopant, or diborane (B2H6) can be added as a P-type dopant.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive
of the invention, as claimed.
BRIEF DESCRIPTION OF THE DRAWINGS
The accompanying drawings, which are incorporated in and constitute a part of
the specification, illustrate an embodiment of the invention and together with the
description, serve to explain the principles of the invention. In the drawings,
Figure la and Figure 1b show the conventional method for fabricating a HSG-Si
structure; and
Figure 2 shows the method for fabricating a HSG-Si structure in a preferred embodiment according to the invention.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
In a preferred embodiment according to the invention, a method for fabricating an
HSG-Si structure applied as the storage electrode of a capacitor is provided. The capacitance is increased with the increasing surface area of the HSG-Si structure.
A substrate having a silicon oxide layer and a contact hole formed thereon is provided. The silicon oxide layer is penetrated by the contact hole, and the contact hole is filled with poly-silicon as a contact plug. On the contact hole and the silicon oxide layer, using CVD, a poly-silicon layer is formed. The poly-silicon layer is then patterned by conventional photolithography and etching process. The native silicon oxide layer on surface of the poly-silicon layer is removed by H2 or HCI solution. Using silane or chlorosilane as the precursor, a HSG-Si structure is grown on the surface by chemical vapour deposition. The by-product produced during the formation of the HSG-Si structure, such as, HCI, or the additional HCl and H2 is reacted with the silicon oxide.
Therefore, the possibility of growing HSG-Si on the silicon oxide layer is suppressed.
That is, HCI can be used as an etchant, to adjust the selectivity for the growth of grain on the poly-silicon layer and the silicon oxide layer. During nucleation, arsine (AsH3) or phosphine (PH3) can be added as an N-type dopant, or diborane (B2H6) can be added as a
P-type dopant.
A detail description of a preferred embodiment according to the invention is given in the following paragraphs.
Referring to Fig.2, a substrate 20 comprising a silicon oxide layer 24 and a contact hole 22 penetrating through the silicon oxide layer 24 is provided. The contact hole is filled with poly-silicon as a contact plug. The poly-silicon layer is then patterned by conventional photolithography and etching process, such as RULE, as a bottom electrode. The poly-silicon layer 26, that is, the bottom electrode, as shown in Fig.2 covers the contact hole 22 and the part of the silicon oxide layer 24. A native oxide layer on the surface of the poly-silicon layer 26 is removed by H2 or HC1 solution for convenience of the subsequent process.
At about 200"C to 6000C, using a chlorosilane material as a precursor, silicon grain is grown by CVD. Whereas the suitable precursor includes silane (SiH4), dichlorosilane (SiH2CI2), trichlorosilane (SiHCl3), or silicon chloride (SiC14). The formula of the reaction of these precursors are:
Though HSG-Si can be grown on the silicon oxide laye 24, the by-products HCI and H2 for the formation of the silicon grain are reacted with silicon oxide and silicon as follows:
It is known from the above formula, that the silicon and the silicon oxide are etched away by H2 and HCI. The end products are then vaporised. It is to be noted that on the poly-silicon layer 26, the nucleation of Si on poly-silicon occurs immediately, and the speed for HCI to etch away Si is much slower than the growth of HSG-Si. On the contrary, the nucleation of silicon on the silicon oxide layer 24 is suppressed due to the longer incubation time and SiO2 and Si etched by H2 and HCL. Thus, the selectivity for forming HSG-Si is enhanced. The resultant HSG-Si structure 28 is shown in Fig.2.
In addition to the by-products, HC1 and H2 can be added externally as required, to adjust the selectivity for the growth of silicon grain and the removal of SiO2/Si.
However, due to the high resistance of the undoped silicon, a dopant in implanted to decrease the resistance, that is, to increase the conductivity. Moreover, the in-situ doping can be performed during HSG-Si growth of the formation of HSG-Si in the same reacting chamber. The dopant gas for N-type dopant is AsH3 or PH3, or B2H6 for Ptype dopant, as required.
The invention adapts the method of selective CVD to form HSG-Si directly instead of the conventional deposition and seeding of amorphous silicon, and UHv process. It is known that the speed of depositing amorphous silicon is very time consuming. A HSG-Si structure with larger surface area is obtained by simplified process. Therefore, the fabricating time and the fabrication cost are reduced.
While the invention has been described by way of example and in terms of a preferred embodiment, it is to be understood that the invention is not limited thereto.
To the contrary, it is intended to cover various modifications and similar arrangements and procedures, and the scope of the appended claims therefore should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements and procedures.
Claims (13)
1. A method for fabricating a hemispherical grain silicon structure, comprising:
providing a substrate, comprising a silicon oxide layer and a contact hole penetrating through the silicon oxide layer, the contact hole being filled with poly-silicon;
forming and patterning a poly-silicon layer to cover the contact hole and part of the silicon oxide layer; and
selectively forming a hemispherical grain silicon structure over the substrate, using chemical vapour deposition with a chlorosilane material as a precursor, so that two kinds of by-products are produced.
2. The method according to claim 1, wherein the chemical vapour deposition is performed at a temperature range between 200"C to 600"C.
3. The method according to claim 1, wherein the chlorosilane material includes monochlorosilane, dichlorosilane, trichlorosilane, and silicon chloride.
4. The method according to claim 1, wherein the by-products are hydrogen and hydrogen chloride, so that growth of the hemispherical grain silicon on the silicon oxide layer is suppressed, and the hemispherical grain silicon structure is formed on the polysilicon layer.
5. The method according to claim 1, wherein extra hydrogen and hydrogen chloride are added in during chemical vapour deposition to adjust a selectivity between growth of hemispherical grain silicon on the poly-silicon layer and on the silicon oxide is
adjusted.
6. The method according to claim 1 wherein the hemispherical grain silicon is
in-situ doped with dopant during chemical vapour deposition.
7. The method according to claim 6, wherein dopant is an arsine or a phosphine.
8. The method according to claim 6, wherein dopant is a diborane.
9. A method of fabricating a hemispherical grain silicon structure, comprising:
proving a substrate comprising a silicon oxide layer and a bottom electrode on
the silicon oxide layer, the bottom electrode connected with the silicon oxide layer by a
contact window; and
selectively forming a hemispherical grain silicon structure over the substrate, using chemical vapour deposition with a chlorosilane material as a precursor, so that two by-products are produced.
10. The method according to claim 8, wherein the bottom electrode is a polysilicon layer.
11. The method according to claim 8, wherein the chemical vapour deposition is performed at a temperature range between 200"C to 600"C.
12. The method according to claim 9, wherein the chlorosilane material includes monochlorosilane, dichlorosilane, trichlorosilane, and silicon chloride.
13. A capacitor fabricated by a method as claimed in any one of the preceding claims.
13. The method according to claim 9, wherein the by-products are hydrogen and hydrogen chloride, so that growth of the hemispherical grain silicon on the silicon oxide layer is suppressed, and the hemispherical grain silicon structure is formed on the electrode.
14. The method according to claim 9, wherein extra hydrogen and hydrogen chloride are added to adjust a selectivity between growth of hemispherical grain silicon on the bottom electrode and on the silicon oxide layer.
15. The method according to claim 9, wherein the hemispherical grain silicon is in-situ doped with dopant during chemical vapour deposition.
16. The method according to claim 15, wherein dopant is an arsine or a
phosphine.
17. The method according to claim 15, wherein dopant is a diborane.
Amendments to the claims have been filed as follows
1. A method of fabricating a hemispherical grain silicon (HSG-Si) structure,
comprising:
providing a substrate with adjacent regions of silicon and silicon dioxide; and
depositing the HSG-Si structure by chemical vapour deposition (CVD) in the
presence of silicon, hydrogen and chlorine species such that during deposition, the
HSG-Si struaure grows on the silicon region in preference to the silicon dioxide
region.
2. A method according to claim 1, wherein the CVD is performed at a
temperature in the range between 200 to 600 "C.
3. A method according to claim 1 or 2, wherein CvD uses a precursor gas
containing silane, chlorosilane or silicon tetrachloride.
4. A method according to claim 3, wherein the chlorosilane is monochlorosilane,
dichlorosilane or trichlorosilane.
5. A method according to claims 3 to 4, wherein hydrogen or hydrogen chloride
are added to the precursor gas.
6. A method according to any preceding claim, wherein the CVD by-produas
are hydrogen or hydrogen chloride.
7. A method according to any preceding claim, wherein the HSG-Si is doped in
situ with a dopant during CVD.
8. A method according to claim 7, wherein the dopant is arsenic or
phosphorous.
9. A method according to claim 7, wherein the dopant is boron.
10. A method according to any preceding claim, wherein the silicon is polycrystalline.
11. A method of fabricating an HSG-Si structure according to any preceding claim, wherein the silicon dioxide layer has a contact hole extending through it from its surface, said hole being filled with a poly-silicon plug, wherein a poly-silicon layer is formed and patterned to cover the plug and HSG-Si is selectively formed on the poly-silicon layer in preference to the silicon dioxide layer.
12. A method of fabricating an HSG-Si structure substantially as hereinbefore described with reference to Figure 2 of the accompanying drawings.
Priority Applications (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB9800587A GB2333178B (en) | 1997-10-18 | 1998-01-12 | Method of fabricating a hemispherical grain silicon structure |
| NL1008062A NL1008062C2 (en) | 1997-10-18 | 1998-01-19 | A method of manufacturing a structure from hemispherical silicon granules. |
| FR9800605A FR2770027B1 (en) | 1997-10-18 | 1998-01-21 | METHOD FOR MANUFACTURING A SILICON STRUCTURE WITH HEMISPHERIC GRAINS |
| JP1051198A JP2945646B2 (en) | 1997-10-18 | 1998-01-22 | Method for producing hemispherical silicon grain structure |
| DE19802523A DE19802523C2 (en) | 1997-10-18 | 1998-01-26 | Process for the production of a structure from hemispherical silicon grain |
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW086115362A TW337024B (en) | 1997-10-18 | 1997-10-18 | Process for producing a hemispherical grain silicon |
| GB9800587A GB2333178B (en) | 1997-10-18 | 1998-01-12 | Method of fabricating a hemispherical grain silicon structure |
| NL1008062A NL1008062C2 (en) | 1997-10-18 | 1998-01-19 | A method of manufacturing a structure from hemispherical silicon granules. |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| GB9800587D0 GB9800587D0 (en) | 1998-03-11 |
| GB2333178A true GB2333178A (en) | 1999-07-14 |
| GB2333178B GB2333178B (en) | 1999-11-24 |
Family
ID=27269170
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB9800587A Expired - Fee Related GB2333178B (en) | 1997-10-18 | 1998-01-12 | Method of fabricating a hemispherical grain silicon structure |
Country Status (5)
| Country | Link |
|---|---|
| JP (1) | JP2945646B2 (en) |
| DE (1) | DE19802523C2 (en) |
| FR (1) | FR2770027B1 (en) |
| GB (1) | GB2333178B (en) |
| NL (1) | NL1008062C2 (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5227651A (en) * | 1991-03-23 | 1993-07-13 | Samsung Electronics, Co., Ltd. | Semiconductor device having a capacitor with an electrode grown through pinholes |
| EP0557590A1 (en) * | 1992-02-28 | 1993-09-01 | Samsung Electronics Co. Ltd. | Method for manufacturing a capacitor of a semiconductor device |
| US5650351A (en) * | 1996-01-11 | 1997-07-22 | Vanguard International Semiconductor Company | Method to form a capacitor having multiple pillars for advanced DRAMS |
| GB2314683A (en) * | 1996-06-28 | 1998-01-07 | Nec Corp | Semiconductor device |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5290729A (en) * | 1990-02-16 | 1994-03-01 | Mitsubishi Denki Kabushiki Kaisha | Stacked type capacitor having a dielectric film formed on a rough surface of an electrode and method of manufacturing thereof |
| JP2882217B2 (en) * | 1992-10-30 | 1999-04-12 | 日本電気株式会社 | Method for manufacturing semiconductor device |
| US5439848A (en) * | 1992-12-30 | 1995-08-08 | Sharp Microelectronics Technology, Inc. | Method for fabricating a self-aligned multi-level interconnect |
| US5663090A (en) * | 1995-06-29 | 1997-09-02 | Micron Technology, Inc. | Method to thermally form hemispherical grain (HSG) silicon to enhance capacitance for application in high density DRAMs |
| EP0801421B1 (en) * | 1996-03-25 | 2003-09-17 | United Microelectronics Corporation | Method for growing hemispherical grain silicon |
| KR100224727B1 (en) * | 1996-11-30 | 1999-10-15 | 윤종용 | A warm wall type reaction chamber and method for manufacturing using the same |
-
1998
- 1998-01-12 GB GB9800587A patent/GB2333178B/en not_active Expired - Fee Related
- 1998-01-19 NL NL1008062A patent/NL1008062C2/en not_active IP Right Cessation
- 1998-01-21 FR FR9800605A patent/FR2770027B1/en not_active Expired - Fee Related
- 1998-01-22 JP JP1051198A patent/JP2945646B2/en not_active Expired - Fee Related
- 1998-01-26 DE DE19802523A patent/DE19802523C2/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5227651A (en) * | 1991-03-23 | 1993-07-13 | Samsung Electronics, Co., Ltd. | Semiconductor device having a capacitor with an electrode grown through pinholes |
| EP0557590A1 (en) * | 1992-02-28 | 1993-09-01 | Samsung Electronics Co. Ltd. | Method for manufacturing a capacitor of a semiconductor device |
| US5650351A (en) * | 1996-01-11 | 1997-07-22 | Vanguard International Semiconductor Company | Method to form a capacitor having multiple pillars for advanced DRAMS |
| GB2314683A (en) * | 1996-06-28 | 1998-01-07 | Nec Corp | Semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| GB2333178B (en) | 1999-11-24 |
| FR2770027B1 (en) | 2001-11-09 |
| FR2770027A1 (en) | 1999-04-23 |
| NL1008062C2 (en) | 1999-07-20 |
| DE19802523C2 (en) | 2001-03-29 |
| DE19802523A1 (en) | 1999-04-22 |
| JPH11121718A (en) | 1999-04-30 |
| JP2945646B2 (en) | 1999-09-06 |
| GB9800587D0 (en) | 1998-03-11 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PCNP | Patent ceased through non-payment of renewal fee |
Effective date: 20090112 |