GB2332290A - Memory management unit incorporating memory fault masking - Google Patents

Abstract

A memory management unit (MMU) 30 containing a virtual memory cache also implements a memory replacement or memory masking algorithm to avoid accessing defective cells in the main memory 18. If a memory replacement algorithm is implemented, a location in substitute memory 20 is accessed instead of a defective location in main memory 18. If a memory masking algorithm is implemented then either the addresses of defective cells are not generated, or addresses are remapped to access working cells. Memory defect maps may be stored in an EPROM or look-up table. Defect maps for each memory module may be stored on the memory module, with the defect map being read by the MMU. The MMU may be incorporated in the processor 12 (figure 3). The substitute memory 20 may be included on the motherboard.

Description

2332290 1 PROCESSING SYSTEM This invention relates to memory systems for

computers and the like, and, in particular, to memory systems which use partial memory circuits.

As the processing power of modern personal computers has increased over the last f ew years, there has been a corresponding increase in the complexity of the software used in these personal computers. Use of higher complexity software has given rise to a dramatic increase in the memory requirements of personal computers. This increase in memory requirements has produced a world-wide demand for semiconductor memory circuits, particularly dynamic random access memory (DRAM), because they are used in SIMMs (single in-line memory modules).

DRAM fabrication plants generally have a low yield of working devices (sometimes only 40% of all devices manufactured are working devices). One effect of this is that a large number of partially working devices (partial circuits) are produced. A partially working device is a device which is not perfect (because it contains at least one faulty cell location) but which has a large number of perfect working cells.

For over twenty years methods have been proposed for using partial circuits in a memory system to obtain full memory function. Most of these methods involve the creation of a new memory system. Some memory systems incorporate a main memory composed of partial circuits, a substitute memory which may also be composed of partial 2 circuits or may be composed of perfect circuits, and some controlling means for disabling known faulty cells and diverting accesses to known good cells. Other memory systems operate on the addresses of faulty cells so that the addresses are mapped to known good addresses in the substitute memory.

We have devised a memory system which may incorporate partial circuits and which obviates the need for additional control circuitry on each memory system. We centralise control functions, thus improving efficiency. Provision is also made for the avoidance or infrequent access of defective locations.

Thus the present invention provides a device for managing access to a memory system, where the device performs the functions of a processor or a memory management unit characterised in that the device implements a memory placement algorithm or memory masking algorithm to avoid accessing defective cells in the memory system.

According to a particular aspect of the invention, the memory system comprises a main or primary memory and a substitute memory, and access to substitute memory is by way of address and data buses separate from those which serve for access to the primary memory.

For a better understanding of the present invention and to show how it may be carried into effect, reference will now be made by way of example to the following diagrams, in which:

Figure la shows how a prior art partial memory system

3 connects to a processor in a computer system; Figure 1b shows a more detailed view of the prior art partial memory system shown in Figure la, where the partial memory system is composed of a main memory, a substitute store and a controller.

Figure 2 shows one configuration of the present invention.

Figure 3 shows another configuration of the present invention.

Figure la shows a prior art memory system 10 connected to a processor 12 by means of an address bus 14 and a data bus 16. Figure 1b shows a diagram of one of the possible configurations of the memory system 10 of Figure la. The memory system 10 comprises a main memory 18 which contains one or more faulty locations, a substitute memory 20 which contains at least one working memory location, and a controller 22 for diverting accesses intended for faulty locations in the main memory 18 to working locations in the substitute memory 20. The memory system 10 operates as a perfect memory and is transparent to the processor 12. In this case a common address bus 14 and data bus 16 are used to access both the main memory 18 and the substitute memory 20.

Figure 2 shows one embodiment of the present invention. In Figure 2 the usual memory controller 22 is replaced by a new memory controller 30. The new memory controller 30 may perform all of the functions of a 4 standard memory controller. These functions include, for example, determining whether data to be accessed resides in cache memory or in main memory, making space in the cache memory when necessary by copying data from the cache to the main memory, and performing the virtual address (as generated by the processor) to physical address (to access the main memory) translation. Memory management is used to map virtual addresses to physical addresses and to control the locality of data between the cache and the main memory. Access to the memory controller 30 from the processor 12 is by way of address bus A and data bus D.

Access from the memory controller 30 to the primary memory 18 is by way of address bus All and data bus D" and to the substitute memory by way of address bus A' and data bus D'.

In addition, the new memory controller 30 also performs replacement memory management functions. These replacement memory management functions include the functions necessary to monitor the addresses of memory locations which are being accessed and to recognise when a defective location is being addressed.

In some processors a pipelined addressing sequence is used; a series of addresses is generated and data is received which lags the current address by a set number of cycles. Thus the processor knows the addresses that will be accessed prior to accessing the addresses. In response to a request to access a defective location in primary memory 18 the new memory controller 30 accesses a substitute memory location instead. It should be emphasised that the particular algorithm used to replace faulty memory locations is not crucial to this invention.

In some embodiments of this invention the new memory controller 30 will map addresses of known faulty locations to known good locations in a similar way to the mapping used to map virtual addresses to physical addresses. In other embodiments of this invention no address mapping will be used but each known faulty address will be routed to the substitute memory instead. In other embodiments of the present invention there is no separate discrete substitute memory unit: The new memory controller or processor avoids generating defective addresses or masks out defective addresses in the primary memory. Thus the memory used will not be fully functional in that the number of usable cells will be less than the total number of cells, but the usable cells will work perfectly and the system will be fully operational as a lower capacity memory system. The processor or new memory controller may also be equipped to determine in use if a cell becomes unusable. This is similar to the operation of a magnetic disc drive which maps out faulty blocks as they become defective or as they are written to.

This invention also relates to a method of incorporating the replacement or fault masking algorithm into a memory controller and so obviate the need for an additional integrated circuit to function as a controller in the memory system. A computer system consists (amongst other functional units) of a processor and memory. The 6 memory can be partitioned. These partitions in the memory (for example SIMMs) may have defects. Information on the defects in each partition may be stored in a defect map (for example an EPROM (erasable programmed read only memory) or a lookup table). The defect map may be accessed by either the processor or the memory management system (perhaps even both) to compensate for the defects in the particular partition of memory selected. The present invention extends the functions of the memory management system. It uses the memory management function to store information relating to the defects in the main memory.

In some embodiments of the present invention the defect map may be stored in a programmable read only memory which is on an extended memory board and is designed to be read directly from the extended memory by the new memory management unit or the processor.

Figure 3 shows another embodiment of the present invention wherein the memory controller is incorporated into the processor 12 that performs the processing functions for the entire memory system. Access to the main memory is by way of address bus All and data bus D" and to the substitute memory by way of address bus A' and data bus D'. This embodiment would require the processor of a computer to include the functions necessary to perform the memory replacement algorithm. It is envisaged that as replacement techniques mature they will be incorporated into standard processors. This would enable computer systems to use extended memory modules (such as memory 7 SIMMs) which are composed of partial memory circuits but which do not have any control circuitry or perhaps even any substitute storage or non- volatile memory. This would have the advantages of simplifying the production of memory modules and of lowering the cost of manufacturing these modules. The modules would come with a notification (in a convenient media) of the defective locations which were present in the module. This information would then be made available to the processor which could import the information for permanent or temporary storage.

Whether the invention is implemented as two units (a processor and a memory management unit) or as one unit (a processor) is a matter of convenience dictated by factors such as silicon real estate and the cost of using two circuits rather than one. The same logical functions occur whether one unit or two units are used.

In other embodiments of the present invention the modules may contain nonvolatile memory for storing the addresses of faulty locations. The nonvolatile memory on the modules may be specifically designed to be accessed by the memory management unit or the processor.

Previously, nonvolatile memory on memory modules was designed to be accessed by a controller on the memory module.

The configuration of the address and data buses shown in Figure 3 may vary depending on the memory replacement scheme being implemented.

It is possible that computer systems using this novel 8 architecture would have some redundant memory available to use as a substitute store. This redundant memory may be included on the motherboard of computers so that the processor could access the redundant memory and use it as a substitute for any faulty locations in the main memory.

Thus no substitute storage would be required on the SIMMS. this solution would probably only be viable if some form of address mapping was conducted on the faulty address, otherwise a substitute address would have to exist for each address in the main memory.

It will be appreciated that various modifications may be made to the above described embodiments within the scope of the present invention. For example, the present invention may be implemented by using a second processor which is controlled by the main processor.

9

Claims (6)

1. A device for managing access to a memory system, where the device performs the functions of a processor or a memory management unit characterised in that the device implements a memory placement algorithm or memory masking algorithm to avoid accessing defective cells in the memory system.

2. A device as claimed in claim 1, wherein the memory system comprises a main or primary memory and a substitute memory, and access to substitute memory is by way of address and data buses separate from those which serve for access to the primary memory.

3. A device is claimed in either preceding claim, wherein the algorithm utilises address mapping.

4. A device as claimed in claim 3 wherein the device is arranged to read a defect map, and the defect map is stored in a programmable read only memory of an extended memory board.

5. A device is claimed in any preceding claim when incorporated into a processor which additionally performs the processing functions for the memory system.

6. A computer system incorporating a device as claimed in any preceding claim.