GB2330960A

GB2330960A - Feedback rf power control with offset stored during off period removed during on period

Info

Publication number: GB2330960A
Application number: GB9722855A
Authority: GB
Inventors: Andrew Christopher Kingswood
Original assignee: Nokia Telecommunications Oy
Current assignee: Nokia Oyj
Priority date: 1997-10-29
Filing date: 1997-10-29
Publication date: 1999-05-05
Also published as: WO1999022446A1; GB9722855D0; AU9532698A

Abstract

A power control loop for a BTS (Base Transceiver System) is described which allows the power control to take into account compensating values which are detected during guard periods between signal bursts in an RF communication system. The power amplification factor is thus modified in dependence on the detected level of the amplified signal in a feedback loop, modified by the compensating value. This is used to remove an offset voltage Voff which exists in the guard period. Use in a TDMA system is described.

Description

IMPROVED POWER CONTROL OF RF SIGNALS This invention relates to power control for radio frequency (RF) signals7 and particularly to power control of RF signals in a mobile communication network. In a mobile communication network, a base transceiver system transmits and receives radio signals between a base station (BS) and mobile stations (MS) . It is necessary to control the transmitted power levels of the radio signals and this is done in dependence on a variety of parameters in accordance with the GSM and other standards. In any mobile communication system, it is desirable to have fairly accurate control over the power levels of the transmitted signals in order to ensure that they reach mobile stations with an adequate but not excessive power level and to prevent interference between neighbouring base stations operating in the same channel.

Figure 1 represents an existing power control architecture for a transceiver which uses a power control loop. A carrier wave modulated at the RF frequency is received at input 8. This input signal is attenuated or amplified by the gain control circuit 30 to produce an amplified signal Vamp having a high power level for transmission for example, the output power of the transmitter may be 46dBm (i.e. antilog (4.6)mW). The amplified signal Vamp is presented to the output connector 40 for transmission as an RF signal and to the input of a detector 50. The detector 50 produces an output voltage signal henceforth referred to as the voltage detect signal Vdet. The detector 50 detects the peak voltage of the amplified signal Vamp and produces an output voltage level Vdet. The voltage level is in proportion to the peak amplitude of the amplified signal Vamp. It is a DC or video signal. The voltage detect signal Vdet is supplied to an integrator 34 which also receives a power control signal Vc from processor circuitry in the transceiver. The integrator 34 determines the difference between Vc and Vdet. This difference is applied to a gain control circuit 30 as control signal 32 to vary the gain of the gain control circuit 30 and thus the amplitude of the amplified signal Vamp. Thus, the amplitude of the amplified signal Vamp is controlled by a power control loop.

This loop causes the amplified signal Vamp to track the power control signal Vc.

The accurate control of the power of a transmitted radio frequency signal is particularly desirable in TDMA cellular network systems. In a TDMA system if the power level of the transmitted signals can be accurately controlled it may be possible to use the same frequency channel at the same time in neighbouring cells. Accordingly it is highly desirable to improve the efficiency of the power control of radio frequency signals. As is known7 in a TDMA system, the amplified signal is transmitted as a sequence of signal bursts representing different time slots and separated by guard periods during which the signal level should be zero or at least very small in relation to the transmitted power level during a signal burst.

According to one aspect of the present invention there is provided a power control loop for a base transceiver system comprising: first amplification circuitry connected to receive an RF input signal in the form of a sequence of signal bursts separated by guard periods and to supply an amplified signal to an output node; detection circuitry for detecting said amplified signal; and compensating means for holding a compensating value depending on the level detected by the detection circuitry during said guard periods; wherein the detection circuitry is connectable to modify the amplification factor of the first amplification circuitry in dependence on a detected level of the amplified signal during said signal bursts modified by the compensating value.

The present invention has particular applications for controlling the power of transmitted signals from the base transceiver station.

According to another aspect of the present invention there is provided a method of controlling the power of a transmitted RF signal in the form of a sequence of signal bursts separated by guard periods, comprising the steps of: detecting the transmitted signal during said guard periods and holding a compensating value depending on the detected level; and detecting the power level of the transmitted signal during the signal bursts and controlling said power level in dependence on the detected power level and the compensating value.

For a better understanding of the present invention and to show how the same may be carried into effect, reference will now be made by way of example to the accompanying drawings in which: Figure 1 is a block diagram of a known power levelling loop for a transceiver; Figure 2 is a block diagram of a two transceiver base transceiver system; Figure 3 is a block diagram illustrating the internal components of a transceiver; Figures 4a and 4b are illustrative of power control signals Vc having power control envelopes and the voltage detect signals Vdet; Figure 5 is a block diagram of a power levelling loop according to the present invention; Figure 6a illustrates an implementation of the power levelling loop of Figure 5; Figure 6b is a circuit diagram illustrating the components of a suitable integrator; Figure 7 is a block diagram illustrating the components of a suitable compensator; Figure 8 is a circuit diagram illustrating the components of a suitable corrector; Figure 9a is a block diagram illustrating a first offset calculator; and Figure 9b is a block diagram illustrating a second offset calculator.

Figure 2 is a block diagram of a two transceiver base transceiver system (BTS) in a mobile communication system by way of background. Each of two transceivers TRXl,TRX2 contains transmit and receive circuits which are known in the art. The outputs of the transmit circuits Txl,Tx2 are connected to a filter circuit 3 which supplies them in a form for transmission via an antenna 5. The transmitted radio signals are denoted by reference numeral 17. The antenna 5 also receives radio signals 19 from mobile stations and supplies these to the receive circuits in the transceivers TRX1,TRX2 as received signal Rx.

The transmit circuits include a modulation circuit for modulating data to be transmitted onto a carrier wave at an appropriate carrier frequency. At present, the GSM standard has a carrier frequency range of 890-915 MHz (uplink: MS to BTS) and 935-960 MHz (downlink: BTS to MS). As shown in Figure 3, each transceiver TRX comprises a processor 7 and an RF unit RFU. Data to be transmitted is supplied from the processor 7. The processor 7 and RF unit also down-convert, filter, demodulate, and decode the received signal Rx supplied to it from the filter unit. The processor 7 also supplies control signals to the RF unit. In particular, the processor 7 supplies the power control signal Vc which controls the power level of the signal transmitted by the transceiver.

In a TDMA system the base transceiver communicates with each mobile station in succession. A burst of data is sent to a first mobile station in a first time slot, then a burst of data is sent to a second mobile station in a second time slot, and so on.

Each of the mobile stations is in a different environment, consequently each of the signal bursts will normally require a different power. The voltage level and ramp times for each signal burst are defined by a power control signal Vc which takes the form of an envelope. Exemplary voltage envelopes are illustrated in Figures 4b and 4d. Figure 4b illustrates a voltage envelope for a base transceiver station which is communicating with two mobile stations in succession, a first MS in time slot one and a second MS in time slot two. Figure 4d illustrates a voltage envelope for a base station which is also communicating with two mobile stations a first MS in time slot one and a second in time slot three, where the base station is not communicating with a mobile station during time slot two.

The ramp times and duration for each burst is set according to the GSM standard. Typical values are 10ys for the ramp times and 577ups for the duration of the burst. The amplitude of the voltage envelope depends on the required power level and this is set according to a number of different parameters, including the cell size in a cellular mobile communication network, the power efficiency of the antenna and the reported signal strength by the mobile station.

Referring to Figure 4b, according to the GSM standard successive time slots are separated by a guard period in which the transmitter is switched off. The guard period is detected and the transmitter is disabled so that Vamp is zero between time tl and t2. In Figure 4b the guard period between burst one and burst two runs from time tl to time t2 and during this period the power control signal Vc is zero. Figure 4a illustrates diagrammatically how the voltage detect signal Vdet varies in response to the power control signal Vc. The diagram plots the voltage detect signal Vdet against time. The voltage detect signal Vdet represents the detected peak voltage of the amplified signal Vamp which produces the transmitted RF signal. In an optimal system, it would be expected that the voltage detect signal Vdet would follow the amplified RF signal Vamp which would follow the power control signal Vc. As Vamp is zero between tl and t2 it would be expected that the voltage detect signal Vdet would be zero. However, a d.c. offset component may be present on the detected signal Vdet as illustrated in Figure 4a as Voff.

This offset can be unavoidable due to circuit tolerances, or can be deliberately introduced to alter power detection levels of different amplification circuits. In either case, unless it is removed the voltage offset Voff prevents the accurate control of the amplified signal Vamp by the power control loop.

In Figure 4d the time slot two between times T1 and T2 iS not utilised. Consequently, the transceiver should be switched off at time tl which is the beginning of the guard period between time slot one and time slot two and not switched back on until time t4 which is the end of the guard period between time slot two and time slot three. The beginning and end of the respective guard periods are detected and the transmitter is disabled so that Vamp is zero between time tl and t4. Figure 4c illustrates in a manner analogous to Figure 4a how the voltage detect signal Vdet varies with respect to time. It consequently also indicates how the power of the transmitted RF signal varies with respect to time. In an optimal system, it would be expected that the voltage detect signal Vdet would follow the amplified RF signal Vamp and consequently would be zero between times tl and t4.

However, for the reason given above a d.c. offset component may be present on the detected signal Vdet.

When the transceiver is operating at very low output powers the voltage detect signal Vdet may become comparable to the voltage offset Voff. This limits the lower value to which the voltage detect signal Vdet can fall and hence limits the dynamic range of the power control loop and introduces non-linearities in the control of the output power at low power levels. Accurate removal of the voltage offset Voff offers improved power control loop performance.

Figure 5 illustrates a power control loop according to one embodiment of the present invention. Figure 5 has reference numerals in common with Figure 1 and where common reference numerals are used they refer to equivalent structural and functional elements. The circuit of Figure 5 differs from that of Figure 1 in that the output of the detector 50, the voltage detect signal Vdet, is compensated by the compensator 48 to produce the compensated signal Vdet'. The compensated signal Vdet' is then input into the integrator 34 to produce a control input signal 32. As previously mentioned in relation to Figures 4a and 4c the voltage detect signal Vdet may include a voltage offset Voff. This voltage offset, if not removed from voltage detect signal Vdet will compromise the accurate control of the amplitude of the transmitted radio frequency signal Vamp. The compensator 48 removes the zero offset voltage Voff.

Vdet' = Vdet-Voff The removal of the voltage offset Voff from the voltage detect signal Vdet consequently improves the operation of the power control loop.

Figure 6a illustrates a power control loop in accordance with Figure 5, within a transceiver.

An amplifying circuit 4 includes a pre amp stage 4a with first and second pre amp amplifiers 24,26 and a power amp stage 4b with a power RF amplifier 28. The pre amp stage 4a receives the modulated carrier wave at the RF input 8. The pre amp stage 4a also includes a gain control circuit 30, for example a variable voltage attenuator (WA). The WA 30 is connected between the first and second amplifiers 24,26 and receives a control input 32 from an integrator 34. The integrator 34 is a standard integrator and will not be described further herein although some of its components are shown in Figure 6a. A suitable integrator is shown in Figure 6b. The RF signal which is input to the pre amp stage 4a is amplified by the first RF amplifier 24 before being supplied to the VAA 30 and the second amplifier 26. The second amplifier 26 further amplifies the signal in dependence on the attenuation set at the WA 30 by the control signal 32.

The thus amplified signal is supplied to the power RF amplifier 28 which implements the bulk of the power amplification. The amplified signal Vamp is supplied to a filter circuit 3 via a circulator 46. Reference numeral 40 represents the connecter to the filter circuit 3.

The integrator 34 receives the compensated signal Vdet' which represents the compensated peak voltage of the amplified signal Vamp. The peak voltage of the amplified signal Vamp is detected by a detection circuit 20 from a proportion of the amplified signal derived from a power coupler 44. The power coupler 44 couples (AC only) a small proportion of the signal Vamp (RF signal). This can be implemented as an edge coupled, parallel line, microstrip hybrid directional coupler. The detection circuit 20 produces an output, the voltage detect signal Vdet, in proportion to the amplified signal Vamp. The voltage detect signal Vdet is input to compensator 48 which produces a compensated signal Vdet'. The compensator 48 removes the voltage offset Voff from the voltage detect signal Vdet. The integrator also receives the power control signal Vc from the processor 7 and determines the difference 32 between Vc and Vdet'. This difference 32 is applied to the WA 30 to control its attenuation. Thus, a power control loop is established.

Figure 7 is a block diagram illustrating the components of a suitable compensator 48. The compensator 48 receives at input 51 the voltage detect signal Vdet. This signal is processed to provide at the output 53 a compensated signal Vdet'. The d.c. voltage offset Voff is calculated by offset calculator 52, and supplied to corrector 54. The corrector 54 receives the voltage detect signal Vdet, corrects it using the voltage offset Voff provided by the offset calculator 52 and presents a compensated signal Vdet' at the output 53.

Figure 8 is a circuit diagram illustrating the components of a suitable corrector 54. The corrector 54 has two inputs 56 and 55 for respectively receiving the voltage offset Voff and the voltage detect signal Vdet. The circuit is a simple subtractor comprising an op-amp 60 and resistors 57a,57b,58,59. The compensated signal Vdet' at output node 53 equals the voltage detect signal Vdet minus the voltage offset Voff.

Figure 9a is a block diagram illustrating an offset calculator 52. The offset calculator has an input 61 and an output 62. The voltage detect signal Vdet is received at input 61 and the voltage offset Voff is provided at output 62. The circuit includes sample and hold circuitry 64 and control circuitry 63.

Referring also to Figure 4a the operation of this circuit will be explained. The control circuitry 63 enables sample and hold circuitry 64. When enabled, the sample and hold circuitry samples the signal received at the input 61, holds the sampled signal and presents that held signal at the output 62 until it is again enabled by the control circuitry 63. According to the GSM standard it is known that during the guard period between signal bursts the transmitter is deactivated. Consequently the expected value of the transmitted signal and the voltage detect signal Vdet should be zero. However, due to circuit tolerances this is not necessarily the case. During the guard period the RF output power of the transmitted signal Vamp is zero but the voltage detect signal Vdet may have a non-zero DC offset value Voff as illustrated in Figure 4a. The control circuitry 63 enables the sample and hold circuitry 64 at a time Tref. Time Tref lies during the guard period, that is between times tl and t2 and times t3 and t4 in Figure 4a. Consequently the sample and hold circuitry samples the voltage offset Voff and holds it, thus presenting it at its output 62. Sampling and holding may occur in every guard period or in selected guard periods. Referring to Figure 4c the voltage detect signal Vdet has a non-zero value Voff between the times tl and t4. The control circuitry 63 enables the sample and hold circuitry 64 at a time Tref, where Tref lies between times tl and t4. The sample and hold circuitry when enabled will sample the voltage offset Voff and hold it, thus presenting it at its output 62. Sample and hold circuitries are well known in the art and the specific circuit implementation of one will thus not be described herein.

Figure 9b is a block diagram illustrating a second offset calculator 52 capable of calculating the voltage offset Voff.

Reference numerals which are common with those of Figure 9a refer to the same structural or functional features. The control circuitry 63 enables the sampler 68 and the memory 65 at a time Tref. The memory 65 holds the expected value of the voltage detect signal at the time Tref. This expected voltage is labelled Vexp and is output by the memory 65 when it is enabled.

The sampler 68 samples the voltage detect signal Vdet when enabled. The output of the sampler 68, Vdet, and the output of the memory 65, Vexp, are both input to the offset determinator 66. The offset determinator 66 compares the sampled voltage detect signal Vdet with the expected voltage Vexp. It calculates how much the voltage detect signal Vdet varies from the expected voltage detect signal Vexp. This difference represents the voltage offset Voff, and is output from the offset determinator 66 to the holding circuit 67. The holding circuit 67 holds the voltage Voff and supplies it to its output node 62 from whence it is supplied to corrector 55 as illustrated in Figure 7.

Whereas the circuit of Figure 9a can be utilised when the voltage detect signal Vdet is expected to be zero, the circuit illustrated in Figure 9b has a more general application. It can be used to calculate the voltage offset Voff when the voltage detect signal Vdet is expected to be a specific voltage (Vexp) at a particular time (Tref). The control circuitry 63 enables the sampler 64 and the memory 65 at this specific time, where the memory 65 stores the expected value of the voltage detect signal (Vexp).

In copending GB Application No. 9717672.1 a modular selfconfiguring transceiver is described. In one described embodiment of that application a booster module can be attached to a transceiver to boost the output signal. It is desirable for the transceiver with attached booster module to have accurate power control over the boosted signal. Consequently it is desirable to have a power control loop in which the voltage detect signal Vdet is derived from the boosted signal. In this case the boosted signal would take the place of the amplified signal Vamp as illustrated in Figure 6a. The creation of the power control loop is established on connection of the booster module to the transceiver. The transceiver, however, already incorporates a power control loop similar to that illustrated in Figure 6a which controls the power of the amplified signal Vamp.

It is therefore necessary for the transceiver to self-configure, that is for it to derive the voltage detect signal Vdet from the boosted signal rather than from the amplified signal Vamp. This is achieved by having a switching circuit which detects the presence of a booster module attached to the transceiver and reconfigures the transceiver so that the power control loop utilises a voltage detect signal derived from the boosted signal.

One method by which this can be achieved is for the booster module to deliberately introduce a d.c. offset into the voltage detect signal Vdet. The transceiver would respond to this d.c. offset and reconfigure itself so that the correct power loop was established. The compensator 48 and the power control loop illustrated in Figure 5 of the present application could be used to remove this known introduced d.c. offset. For example the offset calculator 52 as illustrated in Figure 9a or 9b would be appropriate. It would sample and hold the voltage detect signal during the guard period. Consequently the voltage offset Voff would represent the introduced d.c. offset which is then compensated for by corrector 55.

Claims

CLAIMS: 1. A power control loop for a base transceiver system comprising: first amplification circuitry connected to receive an RF input signal in the form of a sequence of signal bursts separated by guard periods and to supply an amplified signal to an output node; detection circuitry for detecting said amplified signal; and compensating means for holding a compensating value depending on the level detected by the detection circuitry during said guard periods; wherein the detection circuitry is connectable to modify the amplification factor of the first amplification circuitry in dependence on a detected level of the amplified signal during said signal bursts modified by the compensating value.
2. A power control loop as defined in claim 1 wherein successive signal bursts in said sequence of signal bursts have different power levels.
3. A power control loop as defined in claim 1 or 2 wherein successive signal bursts in said sequence of signal bursts have different frequencies within a frequency range.
4. A power control loop as defined in any one of claims 1 to 3 wherein said compensating means comprises a detector for detecting said amplified signal and holding circuitry for holding said compensating value.
5. A power control loop as defined in claim 4 wherein said holding circuitry comprises sample and hold circuitry.
6. A power control loop as defined in claim 4 or 5 wherein said compensating value is the level detected by the detector during the guard period.
7. A power control loop as defined in claim 4 wherein said holding circuitry comprises memory.
8. A power control loop as defined in claim 7 wherein said compensating value is the level detected by the detection circuitry during the guard period corrected in accordance with the content of the memory.
9. A power control loop as defined in any one of claims 4 to 8 wherein said holding circuitry holds said compensating value in response to the diminution of the RF input signal.
10. A power control loop as defined in any preceding claim wherein said detection circuit includes a detector and a corrector, wherein said corrector subtracts said compensating value from the detected level of the amplification signal.
11. A power control loop as defined in any preceding claim wherein the power of the said amplified signal is substantially zero during the guard periods.
12. A method of controlling the power of a transmitted RF signal in the form of a sequence of signal bursts separated by guard periods, comprising the steps of: detecting the transmitted signal during said guard periods and holding a compensating value depending on the detected level; and detecting the power level of the transmitted signal during the signal bursts and controlling said power level in dependence on the detected power level and the compensating value.
13. A method of controlling the power of a transmitted RF signal, as defined in claim 12, wherein successive signal bursts in said sequence of signal bursts have different power levels.
14. A method of controlling the power of a transmitted RF signal, as defined in claim 12 or 13, wherein successive signal bursts in said sequence of signal bursts have different frequencies within a frequency range.
15. A method of controlling the power of a transmitted RF signal, as defined in any one of claims 12 to 14, wherein said compensating value is the detected level.
16. A method of controlling the power of a transmitted RF signal, as defined in any one of claims 12 to 14, wherein said compensating value is the detected level corrected in accordance with a pre stored value.
17. A method of controlling the power of a transmitted RF signal, as defined in any one of claims 12 to 16 wherein said step of holding said compensating value, is in response to the diminution of the detected power level of the transmitted signal.
18. A method of controlling the power of the transmitted RF signal, as defined in any one of claims 12 to 17, wherein said step of controlling said power level comprises calculating the difference between the detected level and the compensating value and controlling the amplitude of the transmitted signal in dependence upon said difference.
19. A method of controlling the power of the transmitted RF signal, as defined in any one of claims 12 to 18 wherein said transmitted signal has substantially zero output power during the guard period.
20. An apparatus substantially as hereinbefore described with reference to Figures 2 to 9b of the accompanying drawings.