GB2329804A

GB2329804A - Time and frequency interleaving device for a multicarrier system

Info

Publication number: GB2329804A
Application number: GB9811110A
Authority: GB
Inventors: Masami Aizawa; Keisuke Harada; Hidenori Tsuboi
Original assignee: Toshiba Corp; Advanced Digital Television Broadcasting Laboratory
Current assignee: Toshiba Corp; Advanced Digital Television Broadcasting Laboratory
Priority date: 1997-05-30
Filing date: 1998-05-26
Publication date: 1999-03-31
Anticipated expiration: 2018-05-26
Also published as: GB2329804B; JP3239084B2; GB9811110D0; KR100531387B1; CN1201310A; TW370752B; JPH10336594A; KR19980087495A; CN1112781C

Abstract

Write and read addresses in column and row directions are generated on the basis of a clock signal synchronized with input data. These addresses are selected by a selector to control write and read of a RAM. Sub-blocks of data are formed and the superposing interleave is executed with a value in the column direction multiplied by an integer, in a memory circuit, and the interleave in the frequency direction is used for the addresses in the column direction and the interleave in the time direction is used for the addresses in the row direction. By these operations, an interleave of a desired depth can be easily constituted and the circuit size can be reduced. OFDM (orthogonal frequency division multiplexing) is referred to.

Description

2329804 - 1

TITLE OF THE INVENTION

MULTI-CARRIER TRANSMISSION INTERLEAVING DEVICE AND METHOD BACKGROUND OF THE INVENTION

The present invention relates to an interleaving device employed f or digital broadcasting based on, f or example, multi-carrier transmission, and the interleaving method.

Recently, the satellite television broadcasting system in the digital mode has been realized and is being developed, and the ground broadcasting shows a similar tendency. In the ground broadcasting the multi-pass fault (ghost) caused by reflection, the Rayleigh phasing fault caused by movement and the like occur, which are not seen in the satellite broadcasting.

Therefore, a system called OFDM (orthogonal frequency divisional multiplex) using a plurality of orthogonal carriers and having a long symbol is considered advantageous.

In the digital broadcasting, error correction is indispensable from the viewpoint of variation of the transmission path and improvement of the transmission characteristics. However, if successive errors such as burst errors are generated, they exceed the ability of correction and their correction becomes impossible.

This is why the data rearranging operation called an interleave, which diffuses burst errors to front and 2 rear blocks to prevent them from exceeding the ability of correction, is executed.

The interleave is classified into several groups according to the method of rearranging data. The block interleave, of them, has been often used since it is easier. One of the other interleaves is the convolutional interleave (document "Burst-Correcting Codes for the Classic Bursty Channel", G.D. Forney, Jr.) The convolutional interleave is said to be effective to the periodical burst error caused by the radar interference and the like (document NASA, "S.N. users guide, Appendix J and K", STDN No.101.2, Revision 6, 1991.), and is used in various circumstances.

The multi-pass fault results from occurrence of a radical fall with a specific frequency in a transmission bandwidth Bw as shown in FIG. 1, with respect to the phase. Since the data is lost during the period in which the fall occurs, a burst-like error is generated in its de- modulation signal. Particularly in Rayleigh-Rice phasing, since the signal is largely attenuated along the time direction as shown in FIG. 2, a very long burst-like error can be easily generated.

As a result, in the interleave of the conventional multi-carrier transmission, it is difficult to constitute an interleave block having a desired depth and the circuit size is extremely large.

3 BRIEF SUMMARY OF THE INVENTION

As described above, in the interleave of the conventional multi-carrier transmission, there is a problem that it is difficult to constitute an interleave block having a desired depth and the circuit size is extremely large.

The present invention aims at providing a multicarrier transmission interleaving device which can solve the above-described problem and which allows the interleave block of a desired depth to be easily constituted and allows the circuit size to be reduced, and also providing the interleaving method.

In order to solve the above-described problem, the multi-carrier transmission interleaving device for transmitting data by use of a plurality of carriers and the interleaving method, of the present invention, write addresses and read addresses in the column direction and the row direction are generated on the basis of a clock signal synchronized with the data. The write addresses and read addresses are transmitted to a memory circuit while controlling their output timing. At this time, sub-blocks are constituted by certain values and the superposing interleave is executed with a value in the column direction multiplied by an integer, in a memory space of the memory circuit. The interleave in the frequency direction is used for the addresses in the column 4 direction and the interleave in the time direction is used for the addresses in the row direction.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING

FIG. 1 is a graph showing characteristics in a frequency axis in a transmission path when a multi-pass is generated; FIG. 2 is a graph characteristics in a time axis in a transmission path when a multi-pass is generated; FIG. 3 is a block diagram showing a structure of an embodiment of a multi- carrier transmission interleaving device according to the present invention.

FIG. 4 is a diagram showing a schematic structure to explain an operation of the embodiment; FIG. 5 is a block diagram showing a circuit structure of the conventional convolutional interleave for comparison with the embodiment; FIG. 6 is a block diagram showing a modified example of the embodiment; FIG. 7 is a block diagram showing the modified example of the embodiment; FIG. 8 is a block diagram showing an applied example of the embodiment; FIG. 9 is a block diagram showing a schematic structure of a de- interleaving device corresponding to the structure of FIG. 4; and FIG. 10 is a block diagram showing a schematic structure of a de- interleaving device corresponding to the structure of FIG. 7.

DETAILED DESCRIPTION OF THE INVENTION

An embodiment of the present invention will be described below with reference to the figures.

FIG. 3 shows a structure of a multi-carrier transmission interleaving device according to the present invention. A write address generating section (W-addr) 11 and a read address generating section (Raddr) 12 generate a write address and a read address, respectively, in accordance with the same clock signal CK. The addresses generated by the address generating sections 11 and 12 are transmitted to a RAM 14 by a selector 13, which changes a read cycle and a write cycle of the addresses at one clock signal. If the RAM 14 has another read address line and another write address line for the respective addresses, they may be used, of course. The RAM 14 writes input data IN during a write cycle, and reads stored data during a read cycle to obtain output data OUT.

The operation of the interleaving device having the above structure will be described below.

As described above, the multi-pass in which data is lost in a symbol as seen in FIG. 1 is different from the Rayleigh phasing in which data is lost by the symbol unit seen in FIG. 10 with respect to the characteristic of the error. Noticing this matter, the present invention realizes an effective interleave by 6 grouping the units into those for multi-pass and those for Rayleigh phasing..

For the purpose of this operation, the interleave in a carrier (frequency) direction f is effective for the former and the interleave in a temporal (time) direction t is effective for the latter. In a conventional device, since these interleave operations are executed independently of each other, overhead caused by peripheral circuits for generating an address or a plurality of RAMs will be a problem. In the present invention optimization of each interleave will be set in the following manner.

First, the interleave in the time direction (row) t will be described here.

When the multiplex transmission, etc. are conceived, synchronization of the frame can be made unnecessary by taking advantage of the convolutional interleave in the time direction. However, if the number of data items in the carrier direction is large, the interleave depth in the time direction becomes too large, which causes problems such as increase in the interleave delay and large capacitance of a buffer. For this reason, sub-blocks are constituted by setting a value in the carrier direction to be. a value obtained by multiplying a certain value Bz by an integer, and the interleave depth is repeated in the sub-block unit. The summary of this process is shown in FIG. 4.

7 FIG. 4 conceptually shows data arrangement executed by the RAM 14 in which the axis of ordinate represents the carrier direction f, the axis of ordinate represents the time direction t, the number Bz of repeat carriers of the sub-blocks is set at 4 and the interleave depth is set at 4. If this circuit is applied to an OFDM different in the number of carriers, completely the same circuit can be realized with a structure extended in the carrier direction, in any case, by setting different numbers of carriers at values obtained by multiplying the certain value Bz by an integer.

Next, the interleave in the carrier direction (column) f will be described.

Since the data is lost within one symbol in the multi-pass, adjacent data remaining are first restored, as shown in FIG. 1. At this time, as shown in FIG. 4, the write column address is operated as a general counter that increases one by one. The read column address is set at a value which allows adjacent samples to be properly separated from each other with reference to an equal interval, or a quadratic function, or a Mseries ("Mseries" is an abbreviation of a maximum length shift register, constituted by an n-stage feedback-type shift register, having a cycle of 2n-1 bits, with a characteristic that random signals including the 2n-1 number of '1111 and the 2n-1-1 of,0,, 8 in one cycle can be obtained), or a specific function, a ROM table and the like. By these operations, the data error at the carrier potion that falls radically as shown in FIG. 1 can be dispersed to the entire body, and can be restricted so as not to exceed the ability of correction. Of course, the same operations may be executed for the write address.

If the mobile reception, etc. are not considered in the multi-pass only, the time interleave that requires a memory region of a large capacitance does not need to be used, and therefore, it is possible to handle the interleave in the carrier direction as a block interleave and operate the interleaves independently of each other. In either case the structure can be simply realized. When the size of the sub-block is made to correspond to the width of the data segment, the timing control can be executed easily.

Further, sharing of the circuit will be described now.

For comparison, FIG. 5 schematically shows a circuit configuration of a conventionally conceived convolutional interleave. In the conventional structure, if the interleave depth is set at, for example, 12, there is one through-path and eleven FIFO shift registers 21-31 expanded by one cell are prepared in parallel below the through-path. A switch 32 introduces the input data IN to the through-path and 9 the eleven shift paths sequentially and a switch 33 take out the outputs of the respective.paths sequentially.

In the conventional structure as described above, however, since there is the through-path (the uppermost path having no delay), paths before and after the register cannot be selected quite arbitrarily. On the other hand, in the structure of the above-described embodiment, since there is no through-path and select sequence can be varied before and after the register as shown in FIG. 4, the interleave in the frequency direction f can be incorporated into the interleave circuit in the time direction t.

Furthermore, as shown in FIG. 6, even if the depth in the time direction is set at 1 in the same structure, the interleave in the only frequency direction f can be realized by reducing the RAM addresses in the circuit remaining unchanged.

In general, since the overhead in the address decoder for accessing to the RAM cells or in the wire region, is made large by increasing the number of the RAMs, the circuit size can be reduced by using the smaller number of RAMs having the same capacitance.

Values such as 1k, 2k, 4k and 8k are used as the number of carriers in the system of OFM When the interleave/de-interleave that can be operated with, for example, 8k, the maximum number of carriers are constituted, the rate of usage of the RAMs becomes 1/8 since the carrier direction becomes shorter in the transmission with 1k.

Generally, however, the characteristics against worse phasing can be enhanced as the interleave depth is larger. Therefore, if the number of carriers is varied in the case of, for example, the present embodiment, the interleave can be realized only by increasing the interleave depth set when the carrier number is 1k at eight times and changing the column address of the RAM 4 partially to the row address. FIG. 7 schematically shows a case where the interleave depth is large and the length in the carrier direction is short.

Therefore, in the multi-carrier transmission interleaving device having the above structure, the interleave block having a desired depth can be easily constituted, it can be realized by the write/read control of the RAM 4, and thereby the circuit size can be reduced than that of the prior art.

FIG. 8 shows an applied example of the interleaving device according to the present invention. Reference numeral 41 denotes a demultiplexer (DEMPX) for decomposing the input data in the unit of bit. After interleaveprocessed in the unit of block by a block interleave processing section (block length Bz) 42, the respective bit outputs decomposed by the 11 de-multiplexer 41 are synthesized at a multiplexer (MPX) 43. Further, the synthesized output is input to a convolutional interleave circuit 44 of the unit of sub-block described in the first aspect, processed in the interleave in which the sub-blocks are repeated in every number Bz of carriers and is output.

That is, if the convolutional interleave of the first aspect is combined with the bit interleave as described above, the bit interleave can be contained within a symbol by enlarging the bit interleave block size by the number obtained by multiplying the value of the block interleave by an integer (of course, it may be equal), and the matching can be enhanced.

In the Detailed Description of the Embodiment, the interleave has been described. However, it can be applied to the de-interleave. FIGS. 9 and 10 schematically show the structure of the de-interleave corresponding respectively to the schematic structure of the interleave shown in FIGS. 4 and 7.

According to the above-described structure of the embodiment, with the interleave in the convolutional type, detection of synchronization is not needed and the frame structure is formed by combination of small blocks. Therefore, the interleave block of a desired depth can be easily constituted. Further, the circuit dimensions can be reduced by sharing the interleave of the frequency/time.

12 As described above, according to the present invention, it is possible to provide the multi-carrier transmission interleaving device which allows the interleave block of a desired depth to be easily constituted and the circuit dimensions to be reduced, and also provide the interleaving method.

Claims

1. A multi-carrier transmission leaving device for transmitting data by use of a plurality of carriers, comprising:

write address-generating means for generating write addresses in the column direction and the row direction on the basis of a clock signal synchronized with said data; read address generating means for generating read addresses in the column direction and the row direction on the basis of said clock signal; timing control means for selecting an output timing of said write addresses and said read addresses; and a memory circuit for outputting the write/read of the data on the basis of the write addresses and the read addresses timing-controlled by said timing control means, wherein in a memory space of said memory circuit, sub-blocks are constituted at certain values and superposing interleave is executed by multiplying the column direction by an integer; and the interleave in a frequency direction is used for said address in the column direction and the interleave in a time direction is used for said address in the row direction.

2. A multi-carrier transmission leaving device 1 a is according to claim 1, wherein said write address generating means and said read address generating means use functions for generation of said read/write addresses in the column direction.

3. A multi-carrier transmission leaving device according to claim 1, wherein said write address generating means and said read address generating means generate said read/write addresses in the column direction by adding integer values and obtaining a surplus with the number of valid data carriers.

4. A multi-carrier transmission leaving device according to claim 1, wherein said write address generating means and said read address generating means use a maximum length shift register for said read/write addresses in the column direction.

5. A multi-carrier transmission leaving device according to claim 1, wherein as for said row addresses, said timing control means alternately exchanges the read addresses and the write addresses to execute the interleave in the only frequency direction.

6. A multi-carrier transmission leaving device according to claim 1, wherein said write address generating means and said read address generating means use a block interleave as said interleave in the column direction.

7. A multi-carrier transmission leaving device according to claim 1, wherein when bit interleave is is executed at a front stage of said device, magnitude of said sub-block is set to be a value obtained by multiplying a block length of the bit interleave at said front stage by an integer.

8. A_multi-carrier transmission leaving device according to claim 1, wherein when a data signal in the multi-carrier transmission system whose number of carriers can be selected is input, a depth of the interleave in the row direction is larger as the number of carriers is decreased.

9. A multi-carrier transmission leaving device according to claim 1, wherein the magnitude of said sub-block corresponds to a width of a segment of said data.

10. A multi-carrier transmission interleaving method of transmitting data by use of a plurality of carriers, comprising the steps of:

generating write addresses and read addresses in a column direction and a row direction, respectively, on the basis of a clock signal synchronized with said data; selecting outputs of said write addresses and said read addresses in accordance with the interleave; outputting said data to a memory circuit so as to be written and read, on the basis of said selected write address and read address; constituting said sub-block with a certain value 16 and executing superposing interleave by multiplying a column direction by an integer, in a memory space of said memory circuit; and using the interleave in a frequency direction for said address in the column direction and using the interleave in a time direction for said address in the row direction.

11. A multi-carrier transmission interleaving method according to claim 10, wherein a function is used for generation of said read/write addresses in the column direction.

12. A multi-carrier transmission interleaving device according to claim 10, wherein a function of adding integer values and obtaining a surplus by the number of valid data carriers is used for generation of said read/write addresses in the column direction.

13. A multi-carrier transmission interleaving method according to claim 1, wherein the maximum length shift register is used for generation of said read/write addresses in the column direction.

14. A multi-carrier transmission interleaving method according to claim 1, wherein as for said addresses in the row direction, the interleave in the only frequency direction is executed by alternately exchanging said read addresses and said write addresses.

15. A multi-carrier transmission interleaving method according to claim 10, wherein a block 17 interleave is used as said interleave in the column direction.

16. A multi-carrier transmission interleaving method according to claim 10, wherein when a bit interleave is executed at a front stage, a magnitude of said sub-block is set to be a value obtained by multiplying a block length of the bit interleave at the front stage by an integer.

17. A multi-carrier transmission interleaving method according to claim 10, wherein when a data signal in the multi-carrier transmission system whose number of carriers can be selected is input, a depth of the interleave in the row direction is larger as the number of carriers is decreased.

18. A multi-carrier transmission interleaving method according to claim 10, wherein the magnitude of said sub-block corresponds to a width of a segment of said data.

19. A multi-carrier transmission interleaving device and method, substantially as hereinbefore described with reference to FIGS. 3 10 of the accompanying drawings.