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GB2328810A - NMOS output driver with negative voltage protection - Google Patents

NMOS output driver with negative voltage protection Download PDF

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Publication number
GB2328810A
GB2328810A GB9801074A GB9801074A GB2328810A GB 2328810 A GB2328810 A GB 2328810A GB 9801074 A GB9801074 A GB 9801074A GB 9801074 A GB9801074 A GB 9801074A GB 2328810 A GB2328810 A GB 2328810A
Authority
GB
United Kingdom
Prior art keywords
input
nmos transistor
pull
control signal
electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
GB9801074A
Other versions
GB9801074D0 (en
Inventor
Chang-Ho Lee
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of GB9801074D0 publication Critical patent/GB9801074D0/en
Publication of GB2328810A publication Critical patent/GB2328810A/en
Withdrawn legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
    • H10D89/601—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs
    • H10D89/811—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs using FETs as protective elements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00315—Modifications for increasing the reliability for protection in field-effect transistor circuits

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Static Random-Access Memory (AREA)
  • Dram (AREA)

Abstract

An NMOS pull-up transistor 213 is protected against high negative voltages appearing on the output node 241 by NMOS transistor 233, which has its gate connected to the negative supply through a current-limiting resistor 251. When a high negative voltage appears on the output node 241, the protective transistor 233 turns on to transmit the high negative voltage to the negative supply rail through the resistance 251, which may be of silicide construction.

Description

2328810 AN INPUT/OUTPUT DRIVER FOR A SEMICONDUCTOR DEVICE The present
invention relates to a semiconductor device, and in particular, to an input/output driver for buffering data.
In general, the voltage level of data must be converted between an internal and an external level, when the data is output or received by a semiconductor memory device. For example, data is converted from a CMOS level to a TTL level or vice versa. A circuit for converting the voltage level of data used for a semiconductor device is an inputloutput driver.
FIG. 1 is a circuit diagram of an inputloutput driver of a conventional semiconductor memory device. Referring to FIG. 1, the input/output driver 101 of the conventional semiconductor device includes a pull-up device 111, a pull-down device 121, a protective device 131 and an input/output pad 141.
The pull-up device 111 includes a first NMOS transistor 113 having a drain connected to a power supply voltage Wc, a source connected to the input/output pad 141 and a gate to which a control signal DOKP is applied. When the control signal DOKI? is high, the pull-up device 111 is turned on to transmit the power supply voltage Vcc to the input/output pad 141, and when the control signal DOI(P is low, the pull-up device 111 is turned off.
1 The pull-down device 121 includes a second NMOS transistor 123 having a drain connected to the input/output pad 141, a source connected to a ground terminal GND and a gate to which the control signal DOKN is applied. When the control signal DOKN is high, the pull-down device 121 is turned on to electrically connect the input/output pad 141 to the ground terminal GND and reduce the voltage of the input/output pad 141 to a low level, and when the control signal DOKN is low, the pull-down device 121 is turned off.
The protective device 131 includes a third NMOS transistor 133 having a drain to which the control signal DOKP is applied, a source connected to the input/output pad 141 and a gate connected to the ground terminal GND. Since the gate of the third NMOS transistor 133 is low, it is turned off during normal operation.
When the control signal DOKP is low and a high negative voltage of thousands of volts is applied to the input/output pad 141, without the protective device 131, a high forward voltage is generated between the gate and the source of the first NMOS transistor 113, to thereby turn on the first NMOS transistor 113. Accordingly, current flows from the drain of the first NMOS transistor 113 to the source thereof, damaging the first NMOS transistor 113. The protective device 131 is used to prevent such damage to the first NMOS transistor 113.
The gate of the third NMOS transistor 133 included in the protective device 131 Is formed of a material having low resistance, i.e., silicide. Therefore, when the]i,Ch negative voltage is applied to the input/output pad 141, the third NMOS transistor 133 2 is turned on earlier and more than the first NMOS transistor 113 for forming the pullup device 111. Accordingly, only the protective device 131 is turned on, while the pull-up device 111 remains turned off. Accordingly, the protective device 131 protects the pull-up device 111.
However, since the gate of the third NMOS transistor 133 for forming the protective device 131 has a low resistance and is electrically connected to the ground terminal GNI), when the high negative voltage is applied to the input/output pad 141, the gate of the third NMOS transistor 133 may be melted, thereby destroying the protective device 13 1.
According to the present invention, there is provided an inputloutput driver for a semiconductor device comprising: an input/output pad; a pull-up device connected between the input/output pad and a power supply voltage, to pull up the voltage of the input/output pad to the power supply voltage, in response to a control signal; an electrical load having one end connected to a ground terminal; and, a protective device having a control electrode connected to the other end of the electrical load, a first electrode connected to the control signal, and a second electrode connected to the input/output pad, such that when a high negative voltage is applied to the inputloutput pad, the protective device is turned on to transmit the high negative voltage to the ground terminal through the electrical load.
is 3 In the present invention, when the high negative voltage is applied to the input/output pad, the input/output driver of the semiconductor device is not damaged, thereby increasing the reliability of the device.
An example of the present invention will now be described in detail with reference to the accompanying drawings, in which:
FIG. 1 is a circuit diagram of an input/output driver of a conventional semiconductor memory device; and, FIG. 2 is a circuit diagram of an input/output driver of a semiconductor memory device according to the present invention.
Referring to FIG. 2, an input/output driver 201 of a semiconductor device according to the present invention includes a pull-up device 2211, a pull-down device 221, an input/output pad 241, a protective device 231 and a resistor 251.
The pull-up device 211 includes a first NMOS transistor 213 having a first electrode (i.e., a drain) to which a power supply voltage Vcc is applied, a second electrode (i.e., a source) connected to the input/output pad 241 and a control electrode (i.e., a gate) to which a control signal DO1CP is applied. When the control signal DO1CP is high. the first NMOS transistor 211 is turned on to pull up the voltage of the input/output pad 241. That is, when the first NMOS transistor 213 is turned on, the voltage of the input/output pad 241 increases to the power supply voltage Vcc. When the control signal DOKP is low, the first NMOS transistor 213 is turned off, to thereby interrupt transmission of the power supply voltage Vcc to the inputloutput pad 241.
C> 4 The pull-down device 221 includes a second NMOS transistor 223 having a first electrode (i.e., a drain) connected to the input/output pad 241, a second electrode (i.e., a source) connected to the ground terminal GND and a control electrode (i.e., a gate) to which the control signal DOKN is applied. When the control signal DOKN is high, the second NMOS transistor 223 is turned on, to thereby pull down the voltage of the 5 input/output pad 241 to the ground terminal GND level. That is, when the second NMOS transistor 223 is turned on, the input/output pad 241 is electrically connected to the ground terminal GND, thus the voltage of the inputloutput pad 241 drops to a low level. When the control signal DOKN is low, the second NMOS transistor 223 is turned, off, to thereby interrupt electrical connection of the inputloutput pad 241 to the ground terminal GND.
The resistor 251 has one end connected to the ground terminal GND and the other end connected to the protective device 231. The resistor 251 is formed of silicide having low resistance.
The protective device 231 includes a third NMOS transistor 233 having a first electrode (i.e., a drain) to which the control signal DOKP is applied, a second electrode (i.e., a source) connected to the input/output pad 241 and a control electrode (i.e., a gate) connected to the other end of the resistor 251. Since the gate of the third NMOS transistor 233 is connected to the ground terminal GND, the protective device is turned off du i ring a normal operation.
The gate of the third NMOS transistor 233 for forming the protective device 231 is formed of silicide having low resistance, to thereby turn on the third NMOS transistor 233 better than the first NMOS transistor for forming the pull-up device 211. Accordingly, when a high negative voltage is applied to the input/output pad 241, only the protective device 231 is turned on, while the pull-up device 211 remains turned off. Therefore, the protective device 231 protects the pull-up device 211.
When the control signal DOKI? is high, the voltage of the input/output pad 241 is pulled up and the power supply voltage Vcc is transmitted externally, and when the control signal DOKN is high, the voltage of the inputloutput pad 241 becomes that of the ground terminal GND, i.e., OV. When the control signals DOKP and DOKN are low, the first and second NMOS transistors 213 and 223 are turned off, and thus the input/output pad 241 is in a floating state.
When reliability of the input/output driver 201 is tested or when a high negative voltage of thousands of volts is applied to the input/output pad 241, a high forward voltage is generated between the control electrode and the second electrode of the third NMOS transistor 233, and thus the third NMOS transistor 233 is turned on. The high forward voltage is partially applied to the resistor 251, to thereby reduce the voltage applied to the control electrode of the third NMOS transistor 233. Thus, the control electrode of the third NMOS transistor 233 is not melted by the high forward voltage. Accordingly, the high negative voltage applied to the input/output pad 241 is stably transmitted to the ground terminal GND without causing damage, to thereby protect the pull-up device 211 and increase the reliability of the semiconductor device including the input/output driver 201.
6

Claims (9)

  1. CLAIMS: 1. An input/output driver for a semiconductor device, comprising:
    an input/output pad; a pull-up device connected between the input/output pad and a power supply voltage, to pull up the voltage of the input/output pad to the power supply voltage, in response to a control signal; an electrical load having one end connected to a ground terminal; and, a protective device having a control electrode connected to the other end of the electrical load, a first electrode connected to the control signal, and a second electrode connected to the inputloutput pad, such that when a high negative voltage is applied to the inputloutput pad, the protective device is turned on to transmit the high negative voltage to the ground terminal through the electrical load.
  2. 2. The input/output driver of claim 1, wherein the electrical load comprises a resistor.
    is
  3. 3. The inputloutput driver of claim 2, wherein the resistor is formed of silicide.
  4. 4. The input/output driver of any preceding claim, wherein the protective device is an NMOS transistor, the drain of which is the first electrode, the source of which is the second electrode, and the gate of which is the control electrode.
    7
  5. 5. The input/output driver of claim 4, wherein the gate of the NMOS transistor is formed of silicide.
  6. 6. The input/output driver of any preceding claim, wherein the pull-up device is an NMOS transistor, the drain of which is connected to the power supply voltage, the gate of which is connected to the control signal, and the source of which is 5 connected to the input/output pad.
  7. 7. The input/output driver of any preceding claim, further comprising a pulldown device having a first electrode connected to the input/output pad, a control electrode to which another control signal is applied, and a second electrode connected to the ground terminal, to pull down the voltage of the input/output pad in response to 10 the other control signal.
  8. 8. The input/output driver of claim 7, wherein the pull-down device is an NMOS transistor the drain of which is connected to the input/output pad, the gate of which is connected to the other control signal, and the source of which is connected to the ground terminal.
    is
  9. 9. An input/output driver substantially as shown in and/or described with reference to Figure 2 of the accompanying drawings.
    8
GB9801074A 1997-08-28 1998-01-19 NMOS output driver with negative voltage protection Withdrawn GB2328810A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019970041982A KR19990018756A (en) 1997-08-28 1997-08-28 I / O driver of semiconductor device

Publications (2)

Publication Number Publication Date
GB9801074D0 GB9801074D0 (en) 1998-03-18
GB2328810A true GB2328810A (en) 1999-03-03

Family

ID=19519057

Family Applications (1)

Application Number Title Priority Date Filing Date
GB9801074A Withdrawn GB2328810A (en) 1997-08-28 1998-01-19 NMOS output driver with negative voltage protection

Country Status (4)

Country Link
JP (1) JPH1173780A (en)
KR (1) KR19990018756A (en)
DE (1) DE19800856A1 (en)
GB (1) GB2328810A (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5495118A (en) * 1993-01-20 1996-02-27 Hitachi, Ltd. Semiconductor device
US5563525A (en) * 1995-02-13 1996-10-08 Taiwan Semiconductor Manufacturing Company Ltd ESD protection device with FET circuit
US5565790A (en) * 1995-02-13 1996-10-15 Taiwan Semiconductor Manufacturing Company Ltd ESD protection circuit with field transistor clamp and resistor in the gate circuit of a clamp triggering FET

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5495118A (en) * 1993-01-20 1996-02-27 Hitachi, Ltd. Semiconductor device
US5563525A (en) * 1995-02-13 1996-10-08 Taiwan Semiconductor Manufacturing Company Ltd ESD protection device with FET circuit
US5565790A (en) * 1995-02-13 1996-10-15 Taiwan Semiconductor Manufacturing Company Ltd ESD protection circuit with field transistor clamp and resistor in the gate circuit of a clamp triggering FET

Also Published As

Publication number Publication date
GB9801074D0 (en) 1998-03-18
JPH1173780A (en) 1999-03-16
KR19990018756A (en) 1999-03-15
DE19800856A1 (en) 1999-03-04

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WAP Application withdrawn, taken to be withdrawn or refused ** after publication under section 16(1)