GB2324161A - Method and apparatus for detecting peaks of a signal - Google Patents

Abstract

A method for detecting peaks of a signal involves comparing an input signal 50 with a threshold signal 47, 48 in which the threshold signal is derived by a method involving a pulsed signal 40, 42 and a filtering 12 arrangement. The duty cycle, pulse width and frequency of the pulsed signal may be varied to adjust the threshold signal. Also disclosed is apparatus for detecting peaks of a signal which involves digital circuitry providing a controllable pulse signal linked to a low-pass filter for deriving a threshold signal. The threshold signal is input to a comparator along with an input signal to compare the said signals and to provide an output signal which indicates the presence of a peak when the threshold is crossed. The apparatus may include means for varying the duty cycle and the pulse width of the pulsed signal.

Description

METHOD AND APPARATUS FOR DETECTING PEAKS OF A SIGNAL Field of the Invention This invention relates to a method and an apparatus for detecting peaks of a signal. The invention is applicable to but not limited to a programmable peak detector and to a signal detector.

Background of the Invention A radio communication system typically includes a plurality of transceiver base stations that communicate to each other by modems.

The modems receive a digital signal from the transceivers and convert the digital signals into an analogue signals. The analogue signal is transmitted through a communication channel by a first modem and received by a second modem.

The modem includes a peak detector in order to decode the analogue signal and a signal detector in order to monitor the communication channel activity, and for allowing a desired signal on the channel to be selected.

Analogue peak detectors and analogue signal detectors are implemented by analogue components and designed to cater for the characteristics of the analogue signal that is of interest. Thus, they tend to be "one off" circuits.

The disadvantage of analogue peak detectors is that their timing characteristics can not be adjusted and their performance may be affected by the components tolerance. Furthermore, there is a need to design a special peak detector or signal detector to cater for each signal because each signal will have different characteristics.

This invention seeks to provide a method and apparatus for detecting a peak of a signal which mitigates the above mentioned disadvantages.

Summarv of the Invention According to a first aspect of the invention there is provided a method for detecting a peak of an input signal. The method comprises the steps of providing a threshold and comparing the input signal with the threshold signal to provide a signal indicative of a threshold being crossed. The method is characterised in that the step of providing a threshold signal comprises the steps of providing a pulsed signal, varying a duty cycle of the pulsed signal and filtering the pulsed signal to produce the threshold signal.

Embodiments of the invention will now be described by way of example only, with reference to the drawings.

Brief Descnption of the Drawings FIG. 1 is a block diagram of a peak detector in accordance with the invention; FIG. 2 is a block diagram of part of the peak detector shown in FIG. 1; FIG. 3 is a signals chart diagram showing signals that have been generated by the peak detector; and FIG. 4 is a flow chart showing a method for detecting a peak of an input signal according to a preferred embodiment of the invention.

Detailed Description of the Drawings The apparatus according to one of the preferred embodiments of the invention is a programmable peak detector 10. The programmable peak detector 10 includes a logic block 20 (which may be a circuit or provided by a suitably programmed microprocessor) for producing a pulsed signal 40 or 42. The pulsed signal 40, 42 is output from the logic block 20 and enters a low pass filter (LPF) 12. The LPF 12 filters high frequency components from the pulsed signal and generates a DC signal which is used as a threshold level 47 or 48. The threshold level 47, 48 is applied to a positive input of a comparator 14 for detecting a positive peak 51 of an input signal 50. The comparator 14 changes its output port level whenever the threshold level has been crossed. The output signal of the comparator 14 is fed back to the logic block 20. The logic block 20 increases or decreases the threshold level 47, 48 in order to follow the positive peak 51 of the input signal 50.

Having given a general description about the operation of the peak detector, a more detailed description will be given now with reference to FIGs. 2 and 3.

FIG. 2 is a more detailed block diagram of the logic block 20 of FIG. 1. The logic block 20 includes a microprocessor 30, a divider 27, a first clock generator 26, a second clock generator 28, a counter 21, a multiplexer 24, a pulse width modulator (PWM) 23, a comparator 22 and a reference signal level generator 29.

A brief introduction about the function of each block of the logic block 20 will be given now.

The microprocessor 30 controls the operation of the following blocks. The microprocessor 30 pre-sets an initial counting value to the counter 21 using the preset peak level line, and disables or enables the counter 21 operation. The microprocessor 30 varies the frequency of the first clock 26 and the second clock 28. The microprocessor 30 applies a clock to divider 27 and applies a reference level to the reference level generator 29. An indication about the received peak level is received by the microprocessor 30 from the counter 21 and a further indication about the reference level generator 29 is also received.

The divider 27 is operably coupled to the first clock 26 and to the second clock 28. The divider 27, divides, by a value M, the clock which was received from the microprocessor 30 to provide a divided clock to the first clock 26 and to the second clock 28.

The first and second clocks 26, 28 affect the detection characteristics of the peak detector 10. The first clock 26 controls a rise time 53 of the received signal peak detection characteristic and the second clock 28 controls a fall time 52 of the received signal peak detection characteristic. The first clock 26 and the second clock 28 are operably coupled to the multiplexer 24. The multiplexer 24 selects between the first clock 26 and the second clock 28 a clock signal to be applied to the counter 21. The counter 21 provides a digital word to the PWM 23 to set the pulsed signal's duty cycle 44. The counter 21 is programmed by the microprocessor 30 to provide predetermined values.

The predetermined value can be varied by selecting an up counting or down counting operation. The selection is done by changing the level of a U/D port CUp/Down) of the counter 21. The counter 21 can be disabled in order to provide a fixed value to the PWM 23. The digital word which is output from the counter 21 can be considered as the value of the detected peak. The PWM 23 provides a pulsed signal. The pulsed signal duty cycle 44 is determined by a digital word which digital word is provided by the counter 21, and the pulsed signal frequency is provided by a fixed clock.

The comparator 22 is operably coupled to the counter 21 and to the reference signal generator 29. The reference signal generator 29 provides a reference threshold level to the comparator 22 and the counter 21 provides a detected peak level. The comparator 22 switches its output level when the threshold has been crossed. The change in the output level of the comparator 22 indicates that a signal has been detected.

There are at least three embodiments that can be provided by the programmable peak detector 10, a peak tracer, a peak detector and a signal detector.

Peak Tracer When operating as a peak tracer, the microprocessor 30 applies a predetermined counting value and disables the counting operation of the counter 21. The multiplexer 24 routes the first clock 26 signal to the counter 21 to set a fast rise time 53 for peak detection. The counter 21 applies to the PWM 23, a digital word which reflects the predetermined counting value. The digital word value determines the pulse width 46 of the PWM 23 output signal. The PWM 23 outputs a pulsed signal 40 to the LPF 12. The LPF 12 filters the high frequency components from the pulsed signal 42 to provide a threshold signal 43 with threshold level X.

When the threshold level X has been crossed, which indicates that peak has been detected, the comparator 14 changes it output level to a logic level "0". An output port of the comparator 14 is operably coupled to the U/D port of the counter 21 and to the multiplexer 24. The microprocessor 30 enables the counter 21 operation. The output signal of the comparator 14 switches the counter 21 to start the down count and switches the multiplexer 24 to route the second clock 28 to the counter 21. The second clock 28 will provide now a slower clock than the first clock 26 to the counter 21. The counter 21 will start to count down to provide a new digital word to the PWM 23. The PWM 23 will generate a new pulse signal 40 with a narrow pulse width 45 to decrease the threshold level into Y level, as is shown in FIG. 3 signal chart 41. When the new threshold has been crossed the comparator 14 switches its output level to a logic level "1". The counter 21 starts to count up to increase the threshold level and the first clock 26 is routed again to the counter 21 to provide fast rise time.

The operation of tracing the input signal is demonstrated by a signal chart 49 of FIG. 3. The dotted line is representing the changing in the threshold level and plain line is representing the input signal 50.

Maximum or Minimum Peak Detector When operating as a maximum or minimum peak detector, the microprocessor 30 applies a predetermined counting value and disables the counting operation of the counter 21. The multiplexer 24 routes the first clock 26 clock signal which the clock signal is suitable for a fast rise time 53 of the peak detection. The counter 21 is operably coupled to the PWM 23 and applies to the PWM 23 a digital word which reflects the predetermined counting value. The digital word value as before determines the pulse width 46 of the PWM 23. The PWM 27 output a pulsed signal 42 to the LPF 12. The LPF 12 filters the high frequency components from the pulsed signal 40 to provide a threshold signal 43 with threshold level Xx When the threshold level X has been crossed, which indicates that peak has been detected, the comparator 14 changes it output level to a logic level "0". An output port of the comparator 14 is operably coupled to the U/I) port of the counter 21 and to the multiplexer 24. The microprocessor 30 enables the counter 21 operation. The multiplexer 24 routes the second clock 28 which is programmed to generate no clock to the counter 21 (that is a constant signal level is applied). Thus, the counter 21 will not count down and the initial threshold level will remain. The next time that the threshold level is crossed, the comparator 14 will provide a logic "1" output level. The multiplexer 24 will route the first clock 26 to be the clock of the counter 21. The counter 21 will start to count up to provide a threshold level indicative of the peak of the input signal 50.

The operation described above is repeated each time the threshold level is crossed. Thus, the digital word at the output of the counter 21 represents the maximum peak level that has been decoded.

To detect the minimum peak level there is a need to switch between the signals applied to the comparator 14. The received signal 50 will be applied to the positive input of the comparator 14 and the threshold signal will be applied to the negative input of the comparator 14 and the above described operation is carried out.

Signal Detector When the apparatus is to be used as a signal detector for detecting the presence of a desired signal or a certain tone in a received signal, the signal detector uses the output of the peak tracer to detect the desired signal.

The operation of the signal detector will now be described. The digital word which represents the received peak level which is applied by the counter 21 enters the digital comparator 22. A reference digital word which is indicative of the desired signal or tone is also entered to the digital comparator 22. The reference digital word is generated by the reference signal generator 29. The digital comparator compares the two digital words. When the digital word, which represents the peak of the signal, has a higher value than the reference digital word then, the digital comparator will output a signal which is indicative of the signal that has been detected.

Referring now to FIG. 4, a method for detecting a peak of an input signal is shown.

The first step of the method, step 100 is that of providing a pulsed signal 40 with a predetermined duty cycle 44. In the preferred embodiment of the invention, the pulsed signal 40 is provided by the PWM 23, and the predetermined value of the duty cycle is set by the microprocessor 30. The next step, step 102 is that of varying the duty cycle 44 of the pulsed signal 40. Varying the duty cycle 44 of the pulsed signal 40 is done by applying a variable digital word from the counter 21 to the PWM 23. The counter 21 may count up or down to vary the digital word value. By changing the frequency of variation of the duty cycle 44 of the pulsed signal 40, as is shown in step 104 the rise time 53 and the fall time 52 of the peak detector can be controlled. The changing of the frequency of variation of the duty cycle 44 is done by selecting different clocks for the counter 21. The multiplexer 24 selects between the first clock 26 and the second clock 28. The first clock 26 controls the rise time 53 of the peak detector detection operation and the second clock 28 controls the fall time 52 of the peak detector detection operation The next step, step 106 is that of filtering the high frequency components from the pulsed signal 40. The LPF 12 filters the high frequency components from the pulsed signal 40 to apply the threshold signal 47 to the comparator 14, as is shown in step 108. The comparator 14 compares between the input signal 50 and the threshold signal 48, as is shown in step 110. When the threshold X has been crossed the comparator 14 will output a signal with logic level "1" or aofl. Steps 102 to 110 will be repeated to varies the threshold level, thus following the peak 51 of the input signal 50.

Thus, it will now be appreciated that the invention provides a universal peak detector and signal which is digitally implemented. This allows the detector to be programmable therefor it can support a detection of peak of different types levels.

Furthermore, the rise time and the fall time of the detection of the peak of the input signal are programmable to support different modulation techniques and different baud rates.

Claims (8)

Claims

1. A method for detecting a peak of an input signal comprising the steps of: providing a threshold signal; comparing the input signal with the threshold signal to provide a signal indicative of a threshold being crossed; characterised in that the step of providing a threshold signal comprises the steps of: providing a pulsed signal; and filtering the pulsed signal to produce the threshold signal.

2. A method as claimed in claim 1 wherein a duty cycle of the pulsed signal is varied.

3. A method as claimed in claim 1 or 2, wherein the step of varying further comprises the steps of: varying the pulsed signal pulse width; and varying the pulsed signal frequency for varying peak detection response period.

4. A method as claimed in claims 1 or 2 or 3, wherein varying the pulsed signal frequency comprises varying a rise time and a fall time of the threshold signal.

5. An apparatus for detecting a peak of an input signal comprising: a logic circuit for providing a controllable pulsed signal operably coupled to a low pass filter; a low pass filter for filtering high frequency components from the pulsed signal to provide a threshold level; a comparator having a first input operably coupled the low pass filter output and a second input operably coupled to the input signal, which comparator comparing the input signal with the threshold signal to provide a signal indicative of a threshold being crossed.

6. Apparatus as claimed in claim 5 wherein means are provided to vary the duty cycle of the pulsed signal.

7. Apparatus as claimed in claim 6, comprising means to vary the pulse width of the pulsed signal.

8. Apparatus substantially as hereinbefore described with reference to or as illustrated by any one of the drawings.