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GB2320775B - Method and system for data processing - Google Patents

Method and system for data processing

Info

Publication number
GB2320775B
GB2320775B GB9721623A GB9721623A GB2320775B GB 2320775 B GB2320775 B GB 2320775B GB 9721623 A GB9721623 A GB 9721623A GB 9721623 A GB9721623 A GB 9721623A GB 2320775 B GB2320775 B GB 2320775B
Authority
GB
United Kingdom
Prior art keywords
data processing
data
processing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
GB9721623A
Other versions
GB2320775A (en
GB9721623D0 (en
Inventor
Muhammad Nural Afsar
Romesh Mangho Jessani
Soummya Mallick
Robert Greg Mcdonald
Mukesh Sharma
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Motorola Solutions Inc
Original Assignee
International Business Machines Corp
Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp, Motorola Inc filed Critical International Business Machines Corp
Publication of GB9721623D0 publication Critical patent/GB9721623D0/en
Publication of GB2320775A publication Critical patent/GB2320775A/en
Application granted granted Critical
Publication of GB2320775B publication Critical patent/GB2320775B/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
    • G06F9/384—Register renaming

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
GB9721623A 1996-11-04 1997-10-14 Method and system for data processing Expired - Fee Related GB2320775B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/740,911 US5812812A (en) 1996-11-04 1996-11-04 Method and system of implementing an early data dependency resolution mechanism in a high-performance data processing system utilizing out-of-order instruction issue

Publications (3)

Publication Number Publication Date
GB9721623D0 GB9721623D0 (en) 1997-12-10
GB2320775A GB2320775A (en) 1998-07-01
GB2320775B true GB2320775B (en) 2001-07-11

Family

ID=24978580

Family Applications (1)

Application Number Title Priority Date Filing Date
GB9721623A Expired - Fee Related GB2320775B (en) 1996-11-04 1997-10-14 Method and system for data processing

Country Status (3)

Country Link
US (1) US5812812A (en)
JP (1) JPH10143366A (en)
GB (1) GB2320775B (en)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6016540A (en) * 1997-01-08 2000-01-18 Intel Corporation Method and apparatus for scheduling instructions in waves
US5768555A (en) * 1997-02-20 1998-06-16 Advanced Micro Devices, Inc. Reorder buffer employing last in buffer and last in line bits
JP2000163265A (en) * 1998-11-30 2000-06-16 Nec Corp Instruction issuing circuit
US6393536B1 (en) 1999-05-18 2002-05-21 Advanced Micro Devices, Inc. Load/store unit employing last-in-buffer indication for rapid load-hit-store
US6708267B1 (en) * 2000-02-04 2004-03-16 International Business Machines Corporation System and method in a pipelined processor for generating a single cycle pipeline stall
US6918119B2 (en) * 2000-04-20 2005-07-12 International Business Machines Corporation Method and system to improve usage of an instruction window buffer in multi-processor, parallel processing environments
US6961931B2 (en) * 2001-01-10 2005-11-01 International Business Machines Corporation Dependency specification using target patterns
US6950928B2 (en) * 2001-03-30 2005-09-27 Intel Corporation Apparatus, method and system for fast register renaming using virtual renaming, including by using rename information or a renamed register
US20040148489A1 (en) * 2003-01-28 2004-07-29 Sun Microsystems, Inc. Sideband VLIW processor
US8151092B2 (en) * 2005-01-12 2012-04-03 International Business Machines Corporation Control signal memoization in a multiple instruction issue microprocessor
US8037366B2 (en) * 2009-03-24 2011-10-11 International Business Machines Corporation Issuing instructions in-order in an out-of-order processor using false dependencies

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0455966A2 (en) * 1990-05-10 1991-11-13 International Business Machines Corporation Compounding preprocessor for cache

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5463746A (en) * 1992-10-30 1995-10-31 International Business Machines Corp. Data processing system having prediction by using an embedded guess bit of remapped and compressed opcodes
WO1995019006A1 (en) * 1994-01-10 1995-07-13 The Dow Chemical Company A massively miltiplexed superscalar harvard architecture computer

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0455966A2 (en) * 1990-05-10 1991-11-13 International Business Machines Corporation Compounding preprocessor for cache

Also Published As

Publication number Publication date
JPH10143366A (en) 1998-05-29
GB2320775A (en) 1998-07-01
US5812812A (en) 1998-09-22
GB9721623D0 (en) 1997-12-10

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Legal Events

Date Code Title Description
PCNP Patent ceased through non-payment of renewal fee

Effective date: 20051014