GB2318893A - Selecting the operating frequency of a computer - Google Patents
Selecting the operating frequency of a computer Download PDFInfo
- Publication number
- GB2318893A GB2318893A GB9622883A GB9622883A GB2318893A GB 2318893 A GB2318893 A GB 2318893A GB 9622883 A GB9622883 A GB 9622883A GB 9622883 A GB9622883 A GB 9622883A GB 2318893 A GB2318893 A GB 2318893A
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- Prior art keywords
- frequency
- computer host
- operating frequency
- switching
- signal
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/08—Clock generators with changeable or programmable clock frequency
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Executing Machine-Instructions (AREA)
Abstract
The operating frequency of a computer host board 10 is set under program control by a user, by means of a selection controller 20 and the computer screen, rather than by conventional jumpers. At power-on the default frequency of clock generator 11 and the default clock-multiplier factor in board 10 are both low. They can be changed to higher values by the computer outputting data and a specific address over bus 201. The address is recognised by a decoder 36 which causes the data to be held in a latch 33. The data controls, over lines 101 and 102, the clock-multiplier factor and clock generator 11, respectively. Latch 34 resets the computer whenever the operating frequency is changed.
Description
AN APPARATUS AND METHOD FOR SWITCHING AN
OPERATING FREQUENCY OF A COMPUTER HOST BOARD
The present invention relates to an apparatus and method for switching an operating frequency of a computer host board, in particular, to an apparatus and method for switching an operating frequency of a computer host board simply by directly setting on the screen of the computer, instead of by changing or adjusting the jumper after disassembling the computer.
Recently, the spectrum of operating frequencies of the central processing units (CPU) of various computers has been enhanced as the computer grades are improved progress- ively, for example, 75/90/100/110/120/133/150/166/180/200 MHz, etc., while various CPU with various operating frequencies are of various frequency doubling factors. For the CPU, used in a PENTIUM equipped personal computer, the frequency doubling factor is 1.5 for an operating frequency of 75/90/100 MHz, 2.0 for an operating frequency of 120/133 MHz and 3.0 for an operating frequency of 180/200 MHz. Furthennore, the PENTIUM
CPU has various kinds of outer operating frequencies such as 50, 60 and 66 MHz. Also, for the CYRIX CPU of various grades, the frequency doubling factors are 2.0, but their outer operating frequencies are different, such as 50, 55, 60, 66, 75 MHz. For the AMD CPUs of various grades which have a clock pulse similar to that of the PENTIUM CPUs, the outer operating frequencies thereof is from 50 to 60 MHz and the frequency doubling factors are only from 1.5 to 2.0. Consequently, to support the above mentioned CPUs, the manufacturers have to provide a plurality sets ofjumpers and switches on the computer host board within a computer for users to adjust said frequency doubling factor and frequency selection signal. Referring to FIG. 2, there is shown a block diagram of said conventional apparatus for switching an operating frequency of a computer host board. The conventional apparatus uses a switch or jumper selector 12 for outputting a set of frequency doubling signals 101 to the input pins BFO, BF1 of the CPU and system chip, and a frequency selection signal 102 to the input pins SO-S2 of the frequency generator 11. The frequency selection signal 102 is provided for determining the operating frequency 103 required for the CPU and system chip and output by the frequency generator 11. Then the CPU and system chip carry on a frequency doubling process to the input operating frequency 103 according to the frequency doubling factor signal 101.
Therefore, when assembling the CPU, the frequency doubling factor jumper varying from 1.5 to 3 and the outer operating frequency jumper varying from 50Mhz to 66 MHz need to be adjusted.
It is understood that this kind of apparatus and method has several disadvantages. One is that a series of steps such as disassembling the computer, comparing with the handbook and adjusting the jumper are required when the operating frequency is desired to be adjusted. A second disadvantage is that using a jumper for selective skip connection may cause an error set. A third disadvantage is that the metal jumper may be aged and oxidized due to the humidity and may cause a defective contact. Therefore, there is a need for above apparatus and method to be improved.
The present invention provides an improved apparatus and method for switching the operating frequency of a computer host board to mitigate and/or obviate the aforementioned problems.
One object of the present invention is to provide an apparatus and method for switching an operating frequency of a computer host board by means of setting on the screen of the computer, instead of by changing or adjusting the jumper.
Another object of the present invention is to provide an apparatus and method for randomly adjusting the CPU operating frequency. When the resetting frequency is too high so that the computer can not be powered up, a resetting operation can be started on the screen simply by powering off and restarting the computer, without disassembling the computer and clearing the prior set.
In accordance with one aspect of the present invention, a method for switching an operating frequency of a computer host comprises the steps of manually activating a system to enable the system finnware to set a frequency doubling factor and an operating frequency when the system is powered up; outputting an address signal including said frequency and a frequency to be switched by a data/address bus after the system finnware sets the frequency doubling factor and the operating frequency; and decoding said address signal and locking said frequency data, thereby to change the frequency doubling factor output to the CPU and chip set and a frequency selection signal output to a frequency generator.
In accordance with another aspect of the present invention, an apparatus for switching an operating frequency of a computer host uses a frequency selection controller instead of a switch or jumper selector. The frequency selection controller comprises a storage unit for storing and locking the frequency data input by the bus to be changed, said storage unit having a first output connected with the CPU and system chip set for outputting a frequency doubling factor and a second output connected with the frequency generator for outputting a frequency selection signal, thereby the frequency doubling factor and the operating frequency of the computer host can be changed according to the locked frequency data; and a decoder unit for receiving an address signal of the switched frequency input by the bus and decoding and confirming the address signal thereby to output a sequence signal for activating the storage unit.
In accordance with a further aspect of the present invention, the apparatus for switching an operating frequency of a computer host further comprises an initial control unit arranged between the storage unit and the decoder unit and activated by a POWER GOOD signal. The initial control unit enables the storage unit to output a preset low frequency doubling factor and low frequency selection signal so that the system is powered up at a lower speed.
In accordance with still a further aspect of the present invention, the apparatus for switching an operating frequency of a computer host further comprises a reset unit activated by the sequence signal output by the decoder unit. The reset unit outputs a signal for the computer host board resetting its hardware.
Other objects, advantages and novel features of the invention will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings.
In the drawings:
FIG. 1 is a schematic view showing a substantial structure of the apparatus in accordance with the present invention;
FIG. 2 is a block diagram showing a conventional apparatus for switching an operating frequency of a computer host board;
FIG. 3 is a block diagram showing an apparatus and method for switching an operating frequency of a computer host board in accordance with the present invention;
FIG. 4 is a circuit diagram of an preferred embodiment in accordance with the present invention; and
FIG. 5 is a sequence diagram showing the control signals of the apparatus and method in accordance with the present invention.
Referring to FIG. 1, the present invention uses a frequency selection controller 20, instead of a switch or jumper selector used in a conventional apparatus and method, to control a frequency doubling factor 101 required for the CPU and system chip set 10 and a frequency selection signal 102 output to a frequency generator 11. Also, the frequency selection controller 20 controls the numerical states of the frequency doubling factor 101 and the frequency selection signal 102 according to a signal of speed set value output by the CPU and system chip 10. Accordingly, it is easy and quick to set the frequency doubling factor and operating frequency of the computer host board after inputting various speed setting signals 201 to a frequency selection controller 20 under the control of.a program. In a preferred embodiment, this purpose is accomplished by means of setting the CPU frequency doubling factor and the outer operating frequency on a screen of the computer in a setting manner similar to that of the computer host board (BIOS) when the system is powered up. The above mentioned method avoids such steps as disassembling the computer, comparing with the handbook and adjusting the jumper, etc.
In structure, referring to FIG. 3 and FIG. 4, it can be seen that the frequency selection controller 20 inside comprises a storage unit 33, a reset unit 34, an initial control unit 35 and a decoder unit 36. With this arrangement, the controller 20 can carry on the task of decoding and identifying the speed setting signal 201 output from the CPU and system chip, and of resetting the frequency doubling factor and outer operating frequency. As shown in FIG. 4, the storage unit 33 may be a Dtype flip-flop, the reset unit 34 and the initial control unit 35 also may be a D-type flip-flop, while the decoder unit 36 may be a decoder. When the
CPU and system chip 10 convert the frequency after being powered up, the data/address bus will output a data signal 305 and a switch frequency address signal 307 to the storage unit 33 and the decoder unit 36, respectively. The initial control unit 35 receives a POWER GOOD signal output by a power supply of the computer. The decoder unit 36 outputs a trigger signal 308. Then the trigger signal 308 is coupled into the storage unit 33, the initial control unit 35 and the reset unit 34. The storage unit 33 further outputs above-mentioned frequency doubling factor 101 to the CPU and system chip 10 and above-mentioned frequency selection signal 102 to the frequency generator 11.
Additionally, the reset unit 34 outputs a resetting signal 303 provided for resetting the CPU and system chip 10, while the CPU and system chip 10 then outputs a resetting feedback signal 304 to the reset unit 34.
In operation, referring to FIG. 5, when the computer is powered up, the initial control unit 35 outputs an on-off signal 309 with high level (turn off) to the storage unit 33 after receiving an input POWER
GOOD signal 306 (with high level) so that the storage unit 33 then outputs a lower frequency doubling factor signal 101 to the CPU and system chip 10 and a lowerspeed frequency selection signal 102 to the frequency generator 11 to activate the computer host board at a lower speed. Thereby, an abnormal activation due to a high setting frequency can be avoided. After the frequency doubling factor and the operating frequency of the computer host board is modified in the BIOS, the CPU will output the data signal 305 and the switched frequency address signal 307. The switched frequency address signal 307 is sent into the decoder unit 36 to be decoded and identified. If the signal 307 is correct, the decoder unit 36 will output a trigger signal 308 (pulse of low level), which acts as a sequence signal for activating the storage unit 33, the reset unit 34 and the initial control unit 35. After being activated by the trigger signal 38, the initial control unit 35 outputs an on-off signal 309 which has been switched to low level (ON) to the storage unit 33 in order to write and lock the frequency data 305 which is to modify the operating frequency at an input of the storage unit 33, simultaneously, to enable the storage unit 33 to modify the output frequency doubling factor signal 101 and frequency selection signal 102 according to the frequency data signal 305. Furthermore, the trigger signal 308 activates the reset unit 34 shown in FIG. 3 and FIG. 4 to enable the reset unit 34 to output a hardware resetting signal 303 of low level as shown in FIG. 5. Thereby, the CPU and system chip 10 resets the hardware, and then outputs a reset feedback signal 304 which has been switched from a high level to a low level to the reset unit 34 so as to clear the reset state and recover to its original state. After the resetting operation, the CPU and system chip operates according to the switched frequency doubling factor and the outer operating frequency.
The above mentioned operation of switching the frequency is automatically followed by the operation of resetting the hardware for the purpose to avoid errors and failures which possibly occur due to the randomly switched operating frequency. Therefore, the operation of resetting the hardware assures the validity and stability of frequency switch.
Accordingly, the present invention provides an apparatus and method of selecting and modifying the CPU frequency doubling factor and the system operating frequency by means of setting on the screen of the computer, instead of by changing or adjusting the jumper. Also, the present invention is controlled by program and the switching control circuit thereof is of full electronic design so that problems of oxidization and defect control can be avoided. Furthermore, the present invention is activated with power on default at a lower speed so that a problem where the computer can not be normally powered up at a higher setting frequency will be solved.
It is to be understood, however, that even though numerous characteristics and advantages of the present invention have been set forth in the foregoing description, together with details of the structure and function of the invention, the disclosure is illustrative only, and changes may be made in detail, especially in matters of shape, size, and arrangement of parts within the principles of the invention to the full extent indicated by the broad general meaning of the terms in which the appended claims are expressed.
Claims (16)
1. A method for switching an operating frequency of a computer host comprising the steps of:
manually activating a system to enable the system firmware to set a frequency doubling factor and an operating frequency when the system is powered up;
outputting an address signal including said frequency and a frequency to be switched by a data/address bus after the system firmware sets the frequency doubling factor and the operating frequency; and
decoding said address signal and locking said frequency data, whereby to change the frequency doubling factor output to the CPU and chip set and a frequency selection signal output to a frequency generator.
2. A method for switching operating frequencies of a computer host as claimed in claim 1 further comprising the step of activating the system at a lower speed when the system is powered up.
3. A method for switching an operating frequency of a computer host as claimed in claim 2, wherein said step of activating the system at a lower speed is started by means of inputting a POWER GOOD signal.
4. A method for switching an operating frequency of a computer host as claimed in claim 3 further comprising a step of returning to operate according to the set frequency doubling factor and the operating frequency when the address signal is decoded to output a trigger signal, after the step of activating the system at a lower speed.
5. A method for switching an operating frequency of a computer host as claimed in claim 1, wherein the frequency data input by the bus are locked by a register.
6. A method for switching an operating frequency of a computer host as claimed in claim 1, wherein the trigger signal, output after the address signal is decoded, generates a signal for the computer host board resetting its hardware so that the computer host board can return to operate according to the switched frequency doubling factor and operating frequency.
7. An apparatus for switching an operating frequency of a computer host using a frequency selection controller instead of a switch or jumper selector, said frequency selection controller comprising:
a storage unit for storing and locking the frequency data input by the bus to be changed, said storage unit having an first output connected with the CPU and system chip set for outputting a frequency doubling factor and a second output connected with the frequency generator for outputting a frequency selection signal, whereby the frequency doubling factor and the operating frequency of the computer host can be changed according to the locked frequency data; and
a decoder unit for receiving an address signal of the switched frequency input by the bus and decoding and confirming the address signal thereby to output a sequence signal for activating the storage unit.
8. An apparatus for switching an operating frequency of a computer host as claimed in claim 7, wherein said storage unit is a D-type flip-flop.
9. An apparatus for switching an operating frequency of a computer host as claimed in claim 7, wherein said decoder unit is a decoder.
10. An apparatus for switching an operating frequency of a computer host as claimed in claim 7 further comprises an initial control unit arranged between the storage unit and the decoder unit and activated by a
POWER GOOD signal, said initial control unit enabling the storage unit to output a preset low frequency doubling factor and low frequency selection signal so that the system is powered up at a lower speed.
11. An apparatus for switching an operating frequency of a computer host as claimed in claim 10, wherein said initial control unit is a D-type flip-flop.
12. An apparatus for switching an operating frequency of a computer host as claimed in claim 10, wherein the storage unit will lock the input frequency data to enable the computer host board to operate according to the set frequency doubling factor and the operating frequency when the decoder unit inputs an address confirmed signal to the initial control unit.
13. An apparatus for switching an operating frequency of a computer host as claimed in claim 7 further comprises a reset unit activated by the sequence signal output by the decoder unit, said reset unit outputting a signal for the computer host board resetting its hardware.
14. An apparatus for switching an operating frequency of a computer host as claimed in claim 13, wherein said reset unit is a D-type flip-flop.
15. An apparatus for switching an operating frequency of a computer host as claimed in claim 13, wherein said reset unit receives a reset feedback signal from the CPU and system chip to enable the reset unit to recover to its original state.
16. An apparatus for switching an operating frequency of a computer host board substantially as hereinbefore described with reference to and as shown in the accompanying drawings except
Figure 2.
16. An apparatus for switching an operating frequency of a computer host substantially as hereinbefore described with reference to and as shown in the accompanying drawings.
Amendments to the claims have been filed as follows
1. A method for switching an operating frequency of a computer
host board comprising the steps of:
manually booting a computer system to enable a system
firmware to set a frequency multiplication factor and a frequency
selection parameter when said computer system is powered up;
outputting an address signal including data of said frequency
multiplication factor and said frequency selection parameter from a
data/address bus after said frequency multiplication factor and said
frequency selection parameter having been set by said system
firmware; and
decoding said address signal and holding said frequency
multiplication factor and said frequency selection parameter, and
thereby switching an operating frequency of a computer host board.
2. A method for switching an operating frequency of a computer
host board as claimed in claim 1, further comprising a step of booting
said computer system at a low speed when said computer system is
powered up.
3. A method for switching an operating frequency of a computer
host board as claimed in claim 2, wherein said step of booting said
computer system at a low speed is started by means of inputting a
POWER GOOD signal generated by a computer power supply.
4. A method for switching an operating frequency of a computer host board as claimed in claim 3, wherein said computer system turns to operate in an operating frequency according to a set frequency multiplication factor and a set frequency selection parameter when said address signal has been decoded and a trigger signal has been sent after said step of booting said computer system at a low speed having been completed.
5. A method for switching an operating frequency of a computer host board as claimed in claim 1, wherein said frequency multiplication factor and said frequency selection parameter coming from said data/address bus are latched by a register.
6. A method for switching an operating frequency of a computer host board as claimed in claim 4, wherein said trigger signal having been sent after said address signal has been decoded responsively generates a signal for providing said computer host board to proceed a hardware reset operation to make said computer host board operate in an operating frequency according to a switched frequency multiplication factor and a switched frequency selection parameter after said computer system has been reset.
7. An apparatus for switching an operating frequency of a computer host board by using a frequency selection controller instead of a switch or a jumper selector, said frequency selection controller comprising:
a storage unit for storing and holding a frequency multiplication factor and a frequency selection parameter coming from a data/address bus and having a set of first output terminals connected to the input pins of a CPU and system chip respectively and a set of second output terminals connected to the input pins of a frequency generator respectively; and
a decoder unit for receiving an address signal coming from said data/address bus and for decoding said address signal thereby to output a timing signal for activating said storage unit.
8. An apparatus for switching an operating frequency of a computer host board as claimed in claim 7, wherein said storage unit is a D-type flip-flop.
9. An apparatus for switching an operating frequency of a computer host board as claimed in claim 7, wherein said decoder unit is a programmable decoder.
10. An apparatus for switching an operating frequency of a computer host board as claimed in claim 7, further comprising an initial control unit connected between said storage unit and said decoder unit and activated by a POWER GOOD signal generated by a computer power supply to make said storage unit output an internal default frequency multiplication factor and an internal default frequency selection parameter with a low speed so that said computer system is booted at a low speed.
11. An apparatus for switching an operating frequency of a computer host board as claimed in claim 10, wherein said initial control unit is a D-type flip-flop.
12. An apparatus for switching an operating frequency of a computer host board as claimed in claim 1 O, wherein said frequency multiplication factor and said frequency selection parameter coming from said decoder unit are stored in said storage unit and said computer host board is operated in an operating frequency according to said stored frequency multiplication factor and said frequency selection parameter.
13. An apparatus for switching an operating frequency of a computer host board as claimed in claim 7, further comprising a reset unit activated by a timing signal outputted by said decoder unit and said reset unit outputs a signal for providing said computer host board to proceed a hardware reset operation.
14. An apparatus for switching an operating frequency of a computer host board as claimed in claim 13, wherein said reset unit is a D-type flip-flop.
15. An apparatus for switching an operating frequency of a computer host board as claimed in claim 13, wherein said reset unit returns to the previous state after receiving a reset feedback signal coming from said CPU and system chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB9622883A GB2318893B (en) | 1996-11-02 | 1996-11-02 | An apparatus and method for switching an operating frequency of a computer host board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB9622883A GB2318893B (en) | 1996-11-02 | 1996-11-02 | An apparatus and method for switching an operating frequency of a computer host board |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| GB9622883D0 GB9622883D0 (en) | 1997-01-08 |
| GB2318893A true GB2318893A (en) | 1998-05-06 |
| GB2318893B GB2318893B (en) | 1999-05-26 |
Family
ID=10802373
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB9622883A Expired - Fee Related GB2318893B (en) | 1996-11-02 | 1996-11-02 | An apparatus and method for switching an operating frequency of a computer host board |
Country Status (1)
| Country | Link |
|---|---|
| GB (1) | GB2318893B (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2260631A (en) * | 1991-10-17 | 1993-04-21 | Intel Corp | Microprocessor 2X core design |
| GB2287555A (en) * | 1994-02-25 | 1995-09-20 | Motorola Gmbh | An adjustable clock generator system. |
| US5479645A (en) * | 1991-10-11 | 1995-12-26 | Kabushiki Kaisha Toshiba | Portable computer capable of switching CPU clocks |
-
1996
- 1996-11-02 GB GB9622883A patent/GB2318893B/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5479645A (en) * | 1991-10-11 | 1995-12-26 | Kabushiki Kaisha Toshiba | Portable computer capable of switching CPU clocks |
| GB2260631A (en) * | 1991-10-17 | 1993-04-21 | Intel Corp | Microprocessor 2X core design |
| GB2287555A (en) * | 1994-02-25 | 1995-09-20 | Motorola Gmbh | An adjustable clock generator system. |
Also Published As
| Publication number | Publication date |
|---|---|
| GB2318893B (en) | 1999-05-26 |
| GB9622883D0 (en) | 1997-01-08 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PCNP | Patent ceased through non-payment of renewal fee |