GB2316279A - Control circuit for digital mobile TDMA telecommunications device - Google Patents

Abstract

A primer comprising an organotitanate and an epoxysilane, when applied to a substrate, renders curable silicone compositions more adherent to a substrate after the silicone compositions have cured by increasing cohesive failure. The primer contains a cyclosiloxane (especially octamethyl cyclotetrasiloxane) or a linear volatile polysiloxane in place of volatile organic solvents.

Description

CONTROL CIRCUIT Field of the Invention This invention relates to control circuits, and particularly to control circuits for use with digital telecommunications devices.

Background of the Invention A digital telecommunications device is typically arranged to transmit and receive in bursts. For transmission, a sample and hold arrangement is used.

Data from a user interface to be transmitted is sampled and held in a data buffer, until a selected periodic time slot of a Time Division Multiple Access (TDMA) frequency, at which point the stored data is written to an air interface to be transmitted. The buffer must be large enough to hold all the data sampled during the period between successive selected slots. When the selected slot occurs, the existing data in the buffer may then be overwritten with newly sampled data, to be transmitted at the next occurrence of the selected slot, and so on.

A problem with this arrangement is that the writing of the data by the user interface into the data buffer may coincide with the reading of the stored data by the air interface, thereby causing contention in the data buffer and corruption of data.

The same problem occurs in the case of data reception from the air interface, where data written to the data buffer by the air interface during a selected periodic time slot may coincide with the reading of data by the user interface.

Again, data access contention will result, and cause corruption of the data.

Simultaneous access may be handled using special methods to give access priority, but this leads to increased device size and marginal performance.

This invention seeks to provide a control circuit which mitigates the above mentioned disadvantages.

Summarv of the Invention According to the present invention there is provided a control circuit for controlling the exchange of data signals between a user interface and a wireless interface in a digital telecommunications device, comprising: a data terminal for exchanging data signals with the user interface; a wireless terminal for exchanging data signals over the air interface at a selected one of a plurality of periodic time divided slots; a memory coupled between the data terminal and the wireless terminal, for storing data to be exchanged therebetween; addressing means coupled to address the memory when exchanging data between the memory and the wireless terminal; and, a user interface buffer, coupled to the data terminal and arranged for storing the data signals to be exchanged between the user interface and the memory, wherein the user interface buffer is arranged to delay the exchanging of data signals between the user interface and the memory, such that contention between access to the memory by the addressing means and the data terminal is avoided.

Preferably the user interface buffer is arranged to cause the exchange of data between the user interface and the memory to occur between each of the plurality of periodic time divided slots. The user interface preferably further comprises means for monitoring timing signals for the occurrence of the period between each of the plurality of periodic time divided slots.

In this way data access contention and therefore corruption of data in the memory is substantially avoided.

Brief Descnption of the Drawings An exemplary embodiment of the invention will now be described with reference to the drawing in which: FIG. 1 shows a preferred embodiment of a control circuit in accordance with the invention.

FIG.2 shows part of the preferred embodiment of FIG.1.

FIG.2 shows part of the preferred embodiment of FIG. 1.

FIG.3 shows a single frame of a TDMA system in accordance with the invention.

Detailed Desenption of a Preferred Embodiment Referring to FIG. 1, there is shown a control circuit 10. A bus terminal 15 of the control circuit 10 is coupled to the main bus of a portable TDMA telecommunications device (not shown), arranged to communicate with a TDMA base station (not shown) over a plurality of TDMA slots. The main bus provides connection to a microprocessor of the portable device, and typically to other peripherals such as a user interface and memory.

A dual port Random Access Memory (RAM) 20 comprises a control register table 25 for storing a number of sets of control register values and first and second data buffers 27 and 28 respectively for storing data signals. The first and second data buffers 27 and 28 are arranged to hold 40 bytes of data each in a recirculating fashion to be further described below. The RAM 20 has a first port coupled to the bus terminal 15 and a second port to be further described below.

An audio input/output (I/O) terminal 30 is coupled to receive data signals such as digital speech signals from an audio source, typically a microphone and to send data signals to an audio output such as a loudspeaker. A loader circuit 60 and a memory buffer interface 40 together with the audio I/O terminal 30 are coupled to the second port of the dual port RAM 20.

An audio buffer synchronisation circuit 90, is coupled between the second port of the dual port RAM 20 and the audio VO terminal 30. The function of this circuit will be further described below.

The memory buffer interface 40 is directly connected to an air buffer interface 45, which has a control input for receiving a control signal to be further described below, and which provides output signals to a transmission device (not shown) via an air output terminal 50.

A timing input terminal 55 receives first and second timing signals from a TDMA timing circuit (not shown) of the portable device, which is synchronised to the base station in a manner to be further described below.

The first and second timing signals are input to the loader circuit 60. The loader circuit 60 is further coupled to registers 70 incorporating a master counter 75.

The registers 70 and master counter 75 are both coupled to a state machine 80. The state machine 80 has a control output coupled to an output-terminal 85 and to the control input of the air buffer interface 45. Therefore the state machine 80 generates the control signals to control the air buffer interface 45.

With reference now also to FIG.2, the audio buffer synchronising circuit 90 contains an audio word counter 93 coupled to a audio timing signal input 35; which provides data timing information about the audio I/O terminal 30. A guard window detector 95 of the audio buffer synchronising circuit 90 is coupled to the timing input terminal 55, and temporary buffers 97 and a memory access control circuit 98 are coupled between the audio I/O terminal 30 and the second port of the dual port RAM 20.

With reference now also to FIG.3, a single exemplary TDMA frame 100 is shown. The TDMA frame 100 comprising 12 transmit (tax) slots 110 labelled 0 to 11, for base station-to-portable device communication, and 12 receive (R;c) slots 120, labelled 12 to 23 for portable device-to-base station communication. The timing of the slots and of the TDMA frame 100 is determined by the base station, the frame being 10ms in duration, The TDMA timing circuit of the portable device is arranged to detect the start of the frame 100, and therefore to synchronise the frame timing of the portable device with respect to the base station.

An exemplary slot 130 is shown in detail. The slot 130 is 416.7 s in length and comprises five data fields; a synchronisation field 135 of 32 bits, an A field of 48 bits, a CRC (error checking) field of 16 bits, a B-field of 320 bits and an X-field of 4 bits, making a total of 60 bits, having a total length of 364.61us. A guard space of 52. 1cos is therefore left between the fields of neighbouring slots.

One slot of the TDMA frame 100 can hold 40 bytes of data in it's B-field, which is the same amount of data able to be stored in the first and second data buffers 27 and 28. Therefore each of the data buffers 27 and 28 can store the data of one slot B-field.

The synchronisation field 135 is used by the TDMA timing circuit of the portable device to synchronise the frame timing as described above.

In operation, the audio word counter (93) keeps track of the incoming data - from the audio I/O terminal 30 by monitoring the audio timing signal input 35, and flags the buffer full condition when 4-nibbles (two bytes) have been read into the temporary buffers 97.

The guard window detector circuit 95 monitors the timing input terminal 55 and instructs the memory access control circuit 98 to initiate a write sequence to the dual port RAM 20 from the temporary buffers 97 during the guard period 160 between each periodic time divided slot. This is synchronised to occur after the loading of the control registers 70 by the Loader 60.

Since data is only transferred between the memory buffer interface 40 and the dual port RAM 20 during a selected one of the periodic time divided slots and not during the guard space 160, there will not be a contention between this data transfer and that occurring between the audio I/O terminal 30 and the dual port RAM 20.

It will be appreciated that alternative methods to the one described above are possible. For example, the audio buffer synchronisation circuit 90 could be arranged to store other than 2 bytes of data. The transfer of data between the audio buffer synchronisation circuit 90 and the dual port RAM 20 could be arranged for a period other than the guard space 160, such as during a redundant slot.

Claims (4)

Claims

1. A control circuit for controlling the exchange of data signals between a user interface and a wireless interface in a digital telecommunications device, comprising: a data terminal for exchanging data signals with the user interface; a wireless terminal for exchanging data signals over the air interface at a selected one of a plurality of periodic time divided slots; a memory coupled between the data terminal and the wireless terminal, for storing data to be exchanged therebetween; addressing means coupled to address the memory when exchanging. data between the memory and the wireless terminal; and, a user interface buffer, coupled to the data terminal and arranged for storing the data signals to be exchanged between the user interface and the memory, wherein the user interface buffer is arranged to delay the exchanging of data signals between the user interface and the memory, such that contention between access to the memory by the addressing means and the data terminal is avoided.

2. The control circuit of claim 1 wherein the user interface buffer is arranged to cause the exchange of data between the user interface and the memory to occur between each of the plurality of periodic time divided slots.

3. The control circuit of claim 2 wherein the user interface further comprises means for monitoring timing signals for the occurrence of the period between each of the plurality of periodic time divided slots.

4. A control circuit substantially as hereinbefore described and with reference to the drawings.