GB2315621A - Automatic gain control for a receiver in which the need for a digital to analog converter at the output of a feedback loop is obviated by using an integrator - Google Patents

Abstract

An automatic gain control system for adjusting the gain of amplifiers of a radio signal receiver in accordance with an amplitude of discrete time signal samples of a received signal, the gain control system comprising an amplitude measuring unit for measuring the amplitude of the discrete time signal samples, a comparator which operates to compare the amplitude with a predetermined threshold and to generate a gain control signal, and an integrator being connected to the comparator which operates to integrate the gain control signal and to feed the integrated gain control signal to a control input of the amplifiers for amplifying the received signal, thereby providing a reduced complexity gain control system, wherein measurement of the received signal and comparison with a desired amplitude is performed in a digital domain of the receiver, without a need for a digital to analogue converter.

Description

IMPROVEMENTS IN OR RELATING TO RECEIVERS The present invention relates to automatic gain control systems which operate to adjust the gain of amplifiers in radio signal receivers in accordance with power levels of received radio signals.

Automatic Gain Control (AGC) is a known process for adjusting the gain of amplifiers within radio signal receivers in accordance with a power level of a received signal. A receiver for detecting a transmitted radio signal is provided with an AGC system in order to mitigate against 'path loss'. Propagating radio signals experience a loss of power in accordance with a distance travelled, which is known as 'path loss'. An effect of path loss is to reduce a power level of a propagated signal by factor proportional to a fourth root of the power level in accordance with distance travelled between a transmitter and a receiver. For this reason, a signal received by a radio signal receiver at a substantial distance from a transmitter, will have a substantially reduced power level compared with the power level of the signal close to the transmitter. Radio signal receivers are therefore provided with AGC systems to mitigate against the 'path loss' by increasing or reducing the gain of amplifiers within the receiver, such that the power level of the received signal is within a dynamic range of received signal powers from which the receiver is able to recover data communicated by the radio signal.

Modern radio receivers are frequently provided with a combination of analogue and digital components. A typical radio receiver is provided with a radio frequency down converter stage and at least one intermediate frequency stage, both implemented with analogue components. At an intermediate frequency stage, or at a base band frequency stage, the received signal is sampled and converted into a digitised discrete time representation of the analogue received signal. Thereafter all processing within the receiver is performed digitally by a digital signal processor. In order to reduce complexity within such a radio receiver, a number of bits used to represent digital samples of the discrete time representation of the analogue received signal is reduced to a minimum number. In order for the number of bits representative of digital discrete time signal samples to be reduced, a power level of the received signal before being passed through the analogue to digital converter must be controlled by an AGC system. In known receivers, components of the AGC system are formed substantially from analogue components. The AGC system, therefore provides a means whereby such digital receiver implementations may operate to detect radio signals whereas without such an AGC system, such an implementation of a receiver with digital components would be impractical as a result of a requirement for a large dynamic range in the receiver, which could be as much as 80 dBs.

Known Automatic Gain Control systems are comprised of a signal level measurement means, an error amplifier which operates to generate an error signal in accordance with a difference between a level of the signal measured by the signal measurement means and a desired signal level, and a loop filter which operates to filter the error signal before application of the error signal to a gain control element of the receiver for adjusting the gain of the received signal. Some elements of such known AGC systems may be combined.

In many radio signal receivers provided with digital signal processors which operate to process discrete time versions of radio signals as hereinbefore described, it is highly desirable to control a power level of the received signal fed to the analogue to digital converter to a precise level. In particular, where a receiver is required to detect and acquire a spreading code used to spread the spectrum of a spread spectrum radio signal, such control of the power level of the received signal may be particularly advantageous. In such a case AGC systems which operate in accordance with analogue components of the receiver suffer a disadvantage as a result of component inaccuracies and temperature variations, which have an effect of changing signal levels of measurement circuits within the AGC system. As a result, the accuracy of such an AGC system comprised only of analogue components of the receiver is somewhat limited and therefore inappropriate for a receiver which requires high accuracy in detecting a spread spectrum radio signal. For this reason it is highly desirable to provide a receiver with an AGC system wherein signal level measurement and error amplification is provided in a digital domain wherein the received signal is processed on a discrete time signal. However, such an arrangement would require an additional digital to analogue converter in order to provide an AGC control signal from the digital domain into an analogue version of the control signal for application to a gain control element within the analogue components of the radio signal receiver. Digital to analogue converters are expensive.

Automatic gain control systems comprising a combination of analogue and digital components for changing the gain of an amplifier in the analogue domain in accordance with measurements made in the digital domain of a receiver, as hereinbefore described, operate to track a change in the power level of a received signal and adjust the gain of amplifiers in accordance with the power level, thereby arranging for the amplitude of the digital signal samples in the digital domain to substantially remain within a predetermined range. However, where the power of the received signal changes rapidly, such automatic gain control systems have difficulty in tracking and responding to sudden changes in received signals power levels.

It is an object of the present invention to provide a reduced complexity automatic gain control system.

It is a further object of the present invention to provide an automatic gain control system with advantages in tracking rapidly .changing power levels of a received signal.

According to the present invention there is provided an automatic gain control system for adjusting the gain of amplifiers of a radio signal receiver in accordance with an amplitude of discrete time signal samples of a received signal, the gain control system comprising an amplitude measuring unit for measuring the amplitude of the discrete time signal samples, a comparator which operates to compare the amplitude with a predetermined threshold and to generate a gain control signal, and an integrator being connected to the comparator which operates to integrate the gain control signal and to feed the integrated gain control signal to a control input of the amplifiers, thereby providing a reduced complexity gain control system, wherein measurement of the received signal and comparison with a desired amplitude is performed in a digital domain of the receiver, without a need for a digital to analogue converter.

By providing a comparator to compare the amplitude of the discrete time signal samples in the digital domain with a predetermined threshold, a signal generated at the output of the threshold detector indicative of a comparison between the amplitude of the discrete time signal samples and the predetermined threshold will provide an indication as to whether the amplitude of the discrete time signal samples is greater than or less than the predetermined threshold. By further providing an integrator to integrate the signal at the output of the comparator and to feed the integrated signal to the amplifiers in the analogue domain for amplifying the received signal, the receiver is provided with an automatic gain control system without a need for an analogue to digital converter.

The comparator functions effectively as a one bit digital to analogue converter, a result of which is integrated by the integrator. A combination of the comparator and integrator therefore serve to provide the receiver with a sufficient gain control system to track power levels of a received signal.

The automatic gain control system may further comprise a slew rate adjusting means which operates to amplify the gain control signal when the gain control signal has not changed for a predetermined period.

The slew rate adjusting means may comprise a clock, a counter loaded with a pre-determined number, a change monitor means which operates in combination with the gain control signal and the counter and clock, to count the predetermined number of clock cycles during which the gain control signal has remained unchanged, and a gain control amplifier which operates to amplify the gain control signal, when the gain control signal has not changed for the period appertaining to the predetermined number of clock cycles, thereby increasing a rate at which the gain of amplifiers of the receiver are changed One embodiment of the invention will now be described by way of example only with reference to the accompanying drawings, wherein, FIGURE 1 is a schematic block diagram of an automatic gain control system, FIGURE 2 is a schematic block diagram of a digital processing part of the automatic gain control system.

Practically all digital processing in radio receivers is conducted at complex baseband. A complex baseband signal is comprised of in-phase (I) and quadrature (Q) components. Thus it is straightforward to measure a signal power level in accordance with either the modulus (7my2) or modulus squared (12 +Q2) of a received signal sample. Often the latter is simpler to implement since it does not require square root computations.

In a full digital implementation of relevant parts of an AGC system, the measured signal power level would have a predetermined threshold subtracted from it, thereby forming a digital error signal. The digital error signal would thereafter be fed to a digital implementation of the loop filter followed by a Digital to Analogue Converter (DAC) which would drive the gain control element directly. Alternatively, the digital error signal could feed a DAC followed by an analogue loop filter, the output of which would drive the gain control element.

It will be appreciated that, in the latter of these two options, the analogue loop filter will attenuate the quantisation noise at the output of the DAC, permitting the DAC to operate with fewer bits of precision. In fact, for many applications, this effect is such that a one bit quantised DAC is adequate with only one bit quantisation. This DAC is therefore, in fact a comparator. The architecture is shown in the top half, above a dotted line A-A of Figure 1. In Figure 1, a received signal is fed from a conductor 1, to an adjustable amplifier 2, which operates to amplify the received signal and to alter the gain in accordance with a control signal fed via a conductor 3. The amplified received signal is thereafter fed to band pass filter 4, and thereafter to an analogue to digital convertor 5. The received signal represented as discrete time signal samples is fed to a digital AGC processing unit 6, via an initial processing unit 7. The digital AGC processing unit 6, operates to generate two AGC signals AGC,1, AGC~2. The AGC,1 signal is fed via a resistor 8 to an input of an integrator 16. The integrator 16, is comprised of an operational amplifier 9, and an integrating capacitor 10, connected between an output of the operational amplifier 9, and an inverting input ''. The integrator 16, has a DC signal derived from a potential divider utilising resistors 12, 13, connected between voltage rails vi and vcc. Both resistors 12, 13, have substantially the same ohmic resistance given as Rb. An output of the integrator 16, is fed via a conductor 14, to an input of the amplifier 2. A second of the two automatic gain control signals AGC2, is also fed to the inverting input of the operational amplifier 9 via a resistor 15.

The digital AGC processing unit 6, operates to generate the first and second gain control signals, AGC~1 and AGC2. The initial processing unit 7, operates to pre-process the discrete time signal samples of the received signal, and if performed at a non zero IF, may include digital down conversion. The initial processing unit 7, will usually include digital matched filtering of the received signal, which will also achieve selectivity against adjacent channel signals. The input to the Digital AGC Processing unit 6, will be complex baseband. The analogue circuitry to the left of the ADC is intended to be representative only. The bandpass IF filter 4 achieves anti aliasing filtering prior to the ADC 5. The gain control amplifier 2, permits adjustment of the gain of the IF. Typically, there could be several such amplifiers and they could appear at RF and/or at any of several IF frequencies. As is common practice, the gain control characteristic of the amplifier is assumed to approximate to exponential, in that the gain is proportional to the exponential of the control voltage. The integrator 16 implements the loop filter of a 1Type I AGC' loop. Vcc is the ground and odd is the supply voltage for both the analogue and the digital circuitry.

Since the two bias resistors, Rb are equal, the loop will level such that AGC,1 spends as much time atV as it does at Vdd.

In many applications such as, for example, spread spectrum receivers, the input to the digital AGC processing unit 6, will have the characteristics of complex Gaussian noise. In this case, the operation of the above circuit can be understood in terms of the loop settling to the point where the probability of the noise power exceeding the threshold is equal to the probability of the noise power being below it. It is easy to show that the loop will level with the signal power equal to the threshold value divided by loge 2.

Moreover, for this case, it can be shown that the degradation over using a full precision DAC is 3.2 dB. Thus comparing two AGC loops of equal instantaneous loop bandwidth, one with the above circuit, the other using a full precision DAC, the former will have amplitude fluctuations which are 3.2 dB greater than the latter, relative to the level of the signal in each case.

In situations wherein a power level of the received signal is initially very different from a required level, the gain control signal AGC,1 may lead to a relatively slow rate of slewing of the AGC gain from the initial different level toward the final required level. This is because no matter how large an error exists internally to the digital AGC processing unit 6, the gain control signal cannot be greater or less than Vc or Vd. A full precision DAC would work better but even this would not handle large fluctuations in the received signal power level. For this reason the second gain control signal AGC~2 is produced to increase the rate of change of the gain control amplifier 2, in accordance with the first gain control signal AGC,1.

The digital AGC processing unit 6 shown in Figure 1, is shown in more detail in Figure 2, where parts also appearing in Figure 1 bear identical numerical and alpha numerical designations. In Figure 2, the digital discrete time signal is fed from the initial processing unit 7, to an amplitude function unit 20, via a conductor 21. The amplitude function unit 20 operates to generate a signal indicative of the amplitude of each of the digital discrete time signal samples of the received signal fed from the conductor 21. The amplitude of each of the discrete time signal samples is further fed to a positive input of a comparator 22, which operates to compare the amplitude of each of the discrete time signal samples with a predetermined threshold fed to an inverting input 23. An output of comparator 22, serves to generate the first gain control signal AGC~1. Also connected to the output of the comparator 22, is a single stage shift register 24, and a first input of a half adder 25. A second input of the half adder 25, is connected to the output from the delay shift register 24. An output from the half adder 25, is connected to a reset input 26, of down counter 27. Connected to an output of the down counter 27, is a zero detector 28, which operates to generate an enable signal fed to a tri-state buffer 29. The output of the zero detector 28, is also connected to an enable bar input of the down counter 27.

Connected to a clock input of the down counter 27, is a clock signal fed via a conductor 30. An input of the tri-state buffer 29, is further connected to the output of the comparator 22. The output of the tri-state buffer is representative of the second gain control signal AGC2.

It is possible to exploit the noise like characteristics of the 'signal. In the levelled condition, the output of AGC,1 will fluctuate randomly between Kc and Vad. It is highly unlikely to have a long run of outputs at, say, vcc. In this case the probability of a run of length N is 2-N. However, if the signal is much greater than the value for the levelled condition, the probability of a long run of outputs at Vc increases substantially. Similarly for the opposite case.

The elements below the dashed line B-B' of the block diagram in Figure 2 detects runs of unchanged AGC,1 output of length N(a good value for Nis 10). As long as such a run continues, output AGC~2 is made equal to AGC,1 (at all other times it is tri-state open circuit). Examining the elements below line B-B' of Figure 1 we see that this output feeds the integrator 9, by a resistor of value R/k. If we make k, greater than one, for example ten, then the effect of an output on AGC~2 is k times larger than the effect of AGC,1. Thus, when the signal becomes significantly greater or smaller than the required level, an additional slewing signal k, where in this case k is equal to ten, times faster is applied. However, once the signal level falls close to a desired level, AGC~2 is disconnected for all but a small fraction (2-N) of the time and the desired steady state loop bandwidth is restored.

In operation the digital AGC processing circuit shown in Figure 2 operates to provide the gain control signal AGC~1 to the shift register (Z-1) 24. Both output and input of the delay shift register are arranged to feed the half adder. The output of the half adder remains low if AGC~1 does not change and high if the output of the half adder does change. The down counter is fed from the sample clock and counts down from N. If the count reaches zero, this is detected by the zero detector 28, which generates a signal output which goes high and enables the tristate buffer fed from AGC,1. The output signal from the zero detector also serves to disable the counter 27, from counting any further. Thus N consecutive unchanged AGC,1 values will enable AGC~2. As long AGC,1 continues unchanged, AGC~2 will remain enabled. However, as soon as AGC~1 changes, N will be loaded into the down counter, the zero detector 27, will generate an output signal which will go to zero and AGC~2 will be disabled. It will then require a further N consecutive unaltered AGC,1 values before AGC~2 can be re-enabled.

To provide the integrator 16, with a reference signal at the non-inverting input, with which to compare the gain control signal AGC~1, applied to the inverting input, the resistors 12, 13, are provided which form a potential divider. Each of the resistors 12, 13, is arranged to have the value Rb, and therefore to provided a reference signal corresponding to a half of the difference between the voltages Vdd and Vcc. However unless each of the resistors 12, 13, are provided with substantially equal ohmic resistance, the reference signal will not be exactly half of the difference between v and vcc.

In a settled state wherein the AGC system operates to adjust the gain of the received signal so that the amplitude of the discrete time samples of the received signal appertains to a desired level, the gain control signal AGC~1 will substantially oscillate between high and low values. The high and low values of AGC~1 are provided by the threshold detector 22, and as such will be determined by components embodied therein. For example, where the components embodied within the threshold detector 22, comprise TTL logic circuits, the high and low values will correspond to high and low TTL logic voltages. Alternatively, the components embodied within the threshold detector 22, may be CMOS logic circuits or any other circuits. As a result, a mean voltage level corresponding to a settled state of AGC,1, will be determined by the high and low voltages provided by the threshold detector 22, and a rate of transition or slew rate between these voltages.

The term slew is hereby defined as being a process or action of changing a signal from one level to another level.

The reference voltage provided by the potential divider formed from the resistors 12, 13, although half way between the voltages Vdd and vcc, may not in fact correspond to the mean voltage of AGC~1 in a settled state, which corresponds to AGC~1 spending, on average, 50two of the time high and 50% of the time low. The reasons for this are that the rate of change of AGC~1 in common with other digital signals such as TTL signals may be asymmetrical, in that the rate of change of the voltage from high to low may be different to that from low to high. Furthermore, as for example with TTL logic, the high and low voltages do not correspond to the supply level voltages v and v,c, but has a low voltage close to vcc (zero volts) and a high voltage substantially less than the supply voltage Vdd. A combination of these effects may result in there being a substantial difference between the mean voltage level of AGC,1, corresponding to AGC,1 spending, on average, 50% of the time high and 50% of the time low, and the voltage corresponding to exactly half of the supply voltages. As such the combination of effects will to lead to an inaccuracy in the adjusted power level, although this could be compensated by changing the values of resistors 12, 13, for example, to unequal values. However, such a change may be subject to tolerance variations, for example, in switching and temperature effects.

Advantageously therefore, the reference signal for the integrator 16, could be provided by a third signal generated by digital AGC processing unit 6, in accordance with high and low voltages and the rate of change when slewing between the high and low voltages hereinbefore described. For example, the third signal could be generated and arranged to alternate between high and low voltages on each symbol clock cycle. Such an arrangement would provide the third signal with a mean voltage level, which would be substantially the same as the mean level of AGC,1, corresponding to AGC,1 spending, on average, 50two of the time high and 50% of the time low, in the absence of any asymmetry in slewing between high and low voltage levels. The third signal would thereafter be fed to a low pass filter which would operate to provide the reference signal for application to the non-inverting input of the integrator 16, in accordance with a mean voltage level of the third signal. The low pass filter could be implemented as an in expensive resistor capacitor combination, wherein the combination provides a relatively long time constant. In this case, a requirement for resistors 12, 13, would be obviated.

Where the slewing between high and low voltage levels of AGC,1 is asymmetric, then generating a third signal with substantially the same high and low voltage levels in accordance with the symbol rate of the received signal may not completely remove differences between the mean voltage level of AGC,1 corresponding to AGC,1 spending, on average, 50% of the time high and 50% of the time low, and the reference signal. This is because asymmetry in slewing which arises in the case of the AGC~1, arises as a result of transitions which take place on average in the settled state 50% of the time, however, in the previous description it was stated that the transitions would take place once every chip or symbol. Thus, the proportion of the time spent in a given state also spent slewing would be different. For this case a second example of a possible third signal would be to use a divide by two circuit in order to make transitions between voltage levels of the third signal occur half as often. In this case, to a first approximation, the effect of asymmetric slewing on AGC~1 would be accommodated. However, a further extension to this concept would then be to take account of the fact that the fluctuations in AGC~1 are pseudo random and that the effect of asymmetry in slewing will be dependent on a pattern of the number of times spent at the high voltage level and the low voltage level. Hence, by generating the third signal from a pseudo random sequence, then the characteristics of AGC~1 would be more faithfully replicated. One possible implementation for the pseudo random sequence, which could be very short, would be an M sequence. Of course, for the purposes of symmetry, the M sequence would need to augmented to be a power of two and therefore spend as much time at the low voltage level as the high voltage level. An augmented M-sequence is an M-sequence which has been extended by an addition of an extra zero to the sequence such that there are equal numbers of ones and zeros. With such a third signal for generating the reference signal for the integrator 16, a fully self calibrating implementation of the AGC system heretofore described would thereby be provided.

As will be appreciate by those skilled in the art, various modifications may be made to the automatic gain control system as hereinbefore described without departing from the scope of the present invention, in particular the down counter may be an up counter and furthermore two counters may be used which may be loaded with different integer values for counting when AGC,1 is high and when AGC,1 is low.

Claims (12)

CLAIMS:

1. An automatic gain control system for adjusting the gain of amplifiers of a radio signal receiver in accordance with an amplitude of discrete time signal samples of a received signal, the gain control system comprising an amplitude measuring unit 'which operates to generate an amplitude signal representative of the amplitude of the discrete time signal samples, a comparator which operates to compare the amplitude signal with a predetermined threshold and to generate a gain control signal indicative of a result of the comparison, and an integrator being connected to the comparator which integrator operates to integrate the gain control signal and to feed the integrated gain control signal to a control input of the amplifiers, thereby providing a reduced complexity gain control system.

2. An automatic gain control system as claimed in Claim 1, further comprises a slew rate adjusting means which operates to increase the gain control signal when the gain control signal has not changed for a predetermined period.

3. An automatic gain control system as claimed in Claim 2, wherein the slew rate adjusting means comprises a clock, a counter loaded with a predetermined number, a change monitor means which operates in combination with the gain control signal and the counter and clock, to count the predetermined number of clock cycles during which the gain control signal has remained unchanged, and a gain control amplifier which operates to amplify the gain control signal, when the gain control signal has not changed for the period appertaining to the predetermined number of clock cycles, thereby increasing a rate at which the gain of amplifiers of the receiver are changed.

4. An automatic gain control system as claimed in any preceding Claim, wherein the integrator comprises an operational amplifier, a capacitor connected between an output of the operational amplifier and an inverting input thereof, and a reference signal generator for generating a reference signal fed to a non-inverting input of the operational amplifier, and wherein the gain control signal is fed to the inverting input of the operational amplifier, thereby forming the integrated gain control signal in accordance with the reference signal and the gain control signal.

5. An automatic gain control system as claimed in Claim 4, wherein the reference signal generator comprises two resistors connected and arranged to form a potential divider between two conductors, which conductors provide power to the said system, and wherein the reference signal is provided at a junction between the two resistors.

6. An automatic gain control system as claimed in Claim 4, wherein the reference signal generator is a second clock, and a low pass filter connected to the clock, which in combination operate to generate the reference signal in accordance with a mean voltage level of a second clock signal generated by the second clock.

7. An automatic gain control system as claimed in Claim 6, wherein the second clock is arranged to generate the second clock signal with a high clock level and a low clock level, which high and low clock levels are substantially representative of high and low signal voltage levels of the gain control signal.

8. An automatic gain control system as claimed in Claims 6 and 7, wherein the second clock signal frequency is a fraction of the symbol rate of the received signal.

9. An automatic gain control system as claimed in Claims 6, 7, or 8, wherein the second clock is arranged to generate the second clock signal with slew rates from the low to the high clock levels, and from the high to the low clock levels, which slew rates are substantially representative of slew rates from low to high and from high to low signal voltage levels of the gain control signal.

10. An automatic gain control system as claimed in Claims 6 to 9, wherein the second clock is a pseudo random number generator, and the second clock signal is a pseudo random binary sequence.

11. An automatic gain control system as claimed in Claim 10, wherein the pseudo random number generator is an augmented M-sequence generator, and the pseudo random binary sequence is an augmented M-sequence.

12. An automatic gain control system as hereinbefore described with reference to the accompanying drawings.