GB2308908A

GB2308908A - Memory cell array

Info

Publication number: GB2308908A
Application number: GB9626916A
Authority: GB
Inventors: Soon Won Hong
Original assignee: Hyundai Electronics Industries Co Ltd
Current assignee: SK Hynix Inc
Priority date: 1995-12-29
Filing date: 1996-12-24
Publication date: 1997-07-09
Anticipated expiration: 2016-12-24
Also published as: DE19654561B4; GB2308908B; GB9626916D0; JPH09191094A; DE19654561A1; JP2966363B2; KR970051170A

Description

2308908 MEMORY CE.I.], AIMAY The present invention relates to a memory

cell array, and more particularly to a memory cell array which can reduce the chip area by allowing four unit cells to use a single bit line in common.

In general, the flash memory device having both functions- of an electrical programming and an erasure is consisted of peripheral circuits and a memory cell array.

The memory cell array is consisted of a plurality of memory cells each of which is selected by word line and bit line signals and data are stored on the memory cells. A program operation to store the dala into the memory cells is accomplished by injecting electrons into each floating gate of the memory cells, while an erasure operation to erase the data stored on the niernory cells is accomplished by discharging the Injected elt,cLi-oiis. Each of the memory cells has also a gate electrode of a stack or spill structure.

A memory cell array which is consisted of memory cells having a gale electrode of stack structure and the programming methoel thereof will be expiained below by reference to FIG.1 and FICY.2.

BAD ORIGINAL A F1G.1 Illustrates it circuit diagram of it conventional cell array in(] FIG.2 illustrates a layout of the conventional mernory cell A first through W" bit lines BLI to BILN and a fil-si Lilt-()LIPTll Rill] word llites W1,1 to WLM are crossed to each other and each of the hi-st ffirough M"' word lines WLI to WLM is connected to each gale electrode of 'i plurality of memory cells. Each of the first through N'l' bit lines BIA to Bl,N is commonly connected to the drain of two neighboring niciiioi-,. cells, while the source electrode of the two memory cells is connected to each of the first through K'l' source lines SL1 to SILK which is disposed parallel to the first through N'l' bit lines BL1 to BLK As it result, the conventional siructure of memory cell array has a limit to reduce the chip size because 1WO Unit cells use a single bit line contact in common.

The program operation of the memory cell array will be explained as follows.

For example, in case the memory cell MCA shown lit FIGA is to be programmed, a bias voltage for program is applied to the s-econd word line W1-2, the second bit line BL2 and the second source llne. SI.2. Then M ilic rnemory cell array formed as above, as the drains of the Lwo meniors, cells are commonly connected and the commonly conllucted draill Is connecled to the bit line which is formed of melhal using a single coniact hole, the size of the device depends on the number of contact holes and [lie itrea occupled by them. In order to reduce the number of the coniact holes, the source of the two memory cells each of which neighbors the fit-S[ BAD ORIGINAL it N'l' bit lines BLI to BLN is connected to a coninioll 1111C CSL formed its it diffusion layer, as shown lit FIG.2. Ill this case, however, when it program bias voltage Is applied to each of [lie second word line WL2, the second bit line BL2 and the common source hne CSL so as to program the memory cell MCA shown in FIG.1, the niciliory cell MCA and the memory cell MCB the drains of' which are cornmoniv connected to the second bit line BL2 are both programmed. Therefore, in order to program only the memory cell MCA, a blas voltage has to bc selectively applied only to the source of the memory cell MCA using it select gate transistor (not shown). Accordingly, the conventional construction has a problem in that the chip area can not be reduced because the conventional construction requires the select gate transistor alld the decoder circuit for driving it.

Accordingly, it is an object of the preseni invention to provide a memory cell which can solve the above menlioned probleni, bY allowillgy a program bias voltage to be selectively applied to odd and even numbers of source lines with the first and second decoders.

It is another object of the present invention to provide a cell iti-ray which can reduce the chip size, by allowing foul. unit cells- to use a single bit line contact.

To accomplish of tile objects, a memory cell array according to 1he BAD ORIGINAL A0 present invenilon comprising.' a pluralily of word lines: a plurality of memory cells each gale electrode of which is connected to the plurality of word lines; it plurality of bit lines to cross with the word lines'. a plurality of source lines in which each source electrode of the memory cells is connected thereto respectively; a first decoder connected to odd numbers of source lines among the source lines, for applying a bias voltage to the odd numbers of the source lines; and a second decoder connected to an even number of source lines among the source lines for applying a bias voltage to the even number of source line.

For fuller understanding of the nature and object of the invention, reference should be had to the following detailed description iaken in conjunction with the accompanying drawings in which:

F1G.1 is zt circuit diagram of it conventional memory cell array, F1G.2 Illustrates a layout of the conventional memory cell array; F1G.3 Illustrates a circuit diagram of a memory cell array according to Llie present invention; BAD ORIGINAL 9) -,1 - v FIGA Illustrates a layout of a Memory cell array accordingr to [lie prescril invention; F1G.5 is cell array F1G.6A along, the FIG.7 Is X3-X3 in FIG5; FIG.8A along the F1G.9A along the an enlarged view of the group of basic cells arnong the niernory shown in FIGA; and FIG.613 are sectional views of the memorv cell array taken lines X1-X2 and X2-X2 in F1G.5; a sectional view of the memory cell array iaken alonk) the 1111e and FIG.8B are sectional views of the memory cell array taken lines X4-X4 and X5-X5 in FIG5; and FIG.913 are sectional views of the memory cell array taken lines Y1-Y1 and Y2-Y2 in FIG5; F1G.10 is a sectional view of the memory cell array taken alongr the line Y3-Y3 in FIG5; and FIGAIA and F1G.1113 are sectional views of the rnemory cell arra.v taken along the lines Y4Y4 and YS-Y5 inn F1G.5.

Similar reference characters refer to sirnilar parts in the several VMws ot, the drawings.

The present invention will be described below in detail by reference to ihe accompanying drawings.

F1G.3 is a circuit diagram of the memory cell according lo the 7 BAD ORIGINAL A0 preselit The I'li-st through N'l' 1)11 lines BLI to 1M.N and the firsi ffirough NI'l' word lines WLI to WIM are crossed to each other and each of the I'll-sl through M"' word lines WIL1 to WILM is connected to Lhe gratu clecirode of a plurality of memory cells. Each of the first through N" bit lines 13LI to, 13LN is commonly connected to the drain of two nciglil)()i-itiky ni(,iiior, cells, while the source electrode of the two memory cells is connected to cach of the first through W" source lines SL1 to SLK formed as a)unction layer and parallel to the first through Mb bit lines BLI to BLN. And the odd numbers of the source lines such as the first, third K-P" source lines SLI, SL3. SLK-1W is a even number) are connected to the first decoder (odd decoder; 1). Even numbers of the source lines such as the second, fourth. Kti' source lines SL2, SL4. SILK are connected to the second decoder (even decoder; 2).

A program method using the memory cell formed thus will bc explained as follows.

For example, in case the memory cell MCC shown in F1G.3 is to be programmed, let a greater voltage Vdd than OV be applied to the second IAL line BL2, let a greater voltage Vpp than the voltage Vdd supplied to the second bit line 131.2 be applied to the second word line W1.2, lel OV he applied from the second decoder 2 connected to the second source line SI-2 and let 1he output of the first decoder 1 turned to be a floating state.

AIso If the memory cell array is constructed according to the present G T BAD cawm$- a# invention, it can reduce thickness of tile field oxide f11111 and silliplify tile processes because [lie word lines are formed in [lie active re,171011.

FIGA is it layout of the memory cell array according to tile preseni invention, FIG.5 is an enlarged view of a gyroup of basic cells, nmong ill(. memory cell shown in FIGA, FIG.6A and FIG.613 are sectional views of th memory cell array taken along the lines X1-X2 and X2 X2 in FIG.5. FIG.7 Is a sectional view of the memory cell array taken along), the llne X3-X3 in FIG.5. FIG.SA and FIG.813 are sectional views of the memory cell array taken along the lines X4-X4 and X5-X5 in FIG.5. FIG.9A and FIG.913 are sectional views of the memory cell array taken along the lines Y1-Y1 and Y2-Y2 in FIGS F1G.10 is a sectional view of the memory cell array taken along the line Y3-Y3 in FIGS FIG.11A and FIG.1113 are sectional views of the memory cell array taken along the lines Y4-Y4 and Y5-Y5 in FIG.S.

The memory cell array according to the present invention is consisted of the combination of a plurality of basic cell groups 500 wherein four unll cells 100, 200, 300 and 400 use a single bit line contact 22 in each basic cell group.

In the basic cell group 500, the first unit cell 100 is formed of a first floating gate 12A, it first control gate ISA, a fit-A source 14A and a common drain 13. The second unit cell 200 is formed of a second floating gate 12B, a second control gate 18B, the first source 14A and the common drain 13. The third unit cell 300 is formed of a third floating. gnile 12C, a 7 - BAD ORIGINAL 0 a) J1 first control sjatc ISA, it second source 1413 and tile collin-toll draill 13. The fOurth unit cell 400 is formed of a fourth floaling gale 12D, tile second control grate 18B, 1he second source 14B and the common drain 13.

[ii the basic cell group 500, the first floating gat.e 12A and lhe -, econd floating gate 12B are arranged longitudinally with a second field oxide fill-t-1 2111 sandwiched therebetween and the third floiiiinl gate 12C and the fourth floating gate 12D are arranged longitudinally with it third fleld oxide film 21C sandwiched therebetween. When the basic cell group 500 is combined longitudinally to electrically isolate the neighboring basic cell groups 500, the first field oxide film 21A is formed on the side of the first and third floating gates 12A and 12C and the fourth field oxide film 21D is also formed on the side of the second and fourth floating gales 12B and 12D.

In 1he basic cell group 500, the first and second floating gate 12A and 12B use the first source 12A in common and the third and fourill floating gales 12C and 12D use the second source 14B in common, wherein ill case the basic cell group 500 is combined longitudinally, the first. source line SLI is formed in a longitudinal direction due to the combination of Lhe first source 14A and the second source line SL2 is formed due to the combination of the second source 14B.

Each of 1he first, second, third and fourth floating gates 12A, 12B, 12C ancl 12D is electrically isolated from the semiconductor subs.trate 11 lw it gilte oxide film 17.

BAD ORIGINAL jo In the basic cell group 500, [lie first control gale ISA Is formed to cover a portion of the first source 14A, the first floating gate 12A. a portion of the common drain 13, a portion of the third floating. grate 12C and the second source 14B in a longitudinal direclion. The second control krate 1811 is formed to cover a portion of the first source 14A, the second floating' gate 12B, a portion of the common drain 13, a portion of the fourth floating gate 12D and the second source 14B in a longitudinal direction. In case the basic cell group 500 is combined horizontally, the first word hne WIL1 is formed in a horizontal direction due to the combination of the first control gate ISA and the second word line WL2 is formed due to 1he combination of the second control gate 18B.

Each of the first and second control gates 18A and 18B is electrically isolated from each of the first, second, third and fourth floating gates 12A, 12B, 12C and 12D by a dielectric film 16 and also is electrically isolated from each of the common drain 13, the first source 14A and the second source 14B by a thermal oxide film 15.

In the basic cell group 500, an interlayer insulating film 19 is formed on the entire surface of the structure in which the first and second control gates 18A and 18B are formed. A wire 20 is then formed al the conlact portion of the common drain 13 through a metal contact process. whell the basic cell group 500 is combined in a longitudinal direction, the first bit line BLI is formed by the combination of the wire 20. Then the first bit 1111C BLI serves to make the common drains 13 in each of lhe cell group 500 BAD ORIGINAL 0 j bc (.1ectrically connected.

According to the above mentioned embodiments. the menior y cell arrav of [lit, preseni invention is consisted of a first through W1' source fines S1-1 through SLK formed in a longitudinal direction, a first through M"' word lines WLI through WILM formed in a horizontal dircellon and a first through N'l' bit lines BLI through BLN formed in a longitudinal direction, in which a plurality of basic cell groups 500 are combined in a horizontal and longitudinal directions with four unit cells 100, 200, 300 and 400 using a single bit line contact 22 in each cell group 500.

Accordingly, the present invention has an outstanding effect which can simplify the device operation by applying selectively a program blas voltage to Llic odd and even lines of the source lines by the first and second decoders and also can reduce the chip size by making four unit cells use a single bit line contact in common.

BAD ORIGINAL jo - 10

Claims

CIAIMS:

1 A memory cell array comprising it plurality of word lines:

it plurality of memory cells each gate electrode of which r, connected to the plurality of word lines; a plurality of bit lines to cross with said word lines; a plurality of source lines in which each source electrode of said memory cells is connected thereto respectively; a first decoder connected to odd numbers of source lines among said source lines, for applying a bias voltage to the odd numbers of said source lines; and a second decoder connected to an even number of source lines among said source lines for applying a bias voltage to said even number Of source line.

2. A memory cell array comprising; a unit cell in which a floating gate, a control gate, it source and it drain are formed on a semiconductor substrate; and a basic cell group in which four unit cells form a single group, sald four unit cells using said drain in common, wherein said basic cell group is combined plurally in a longitudinal and horizontal directions. 3. The memory cell array claimed in Claim 2 wherein, by combing sald basic cell group, a plurality of the source lines are formed in it longitudinal direction, a plurality of the word lines are formed in it horizontal direction, 11 - BAD ORIGINAL J1 and a plurality of 1he 1)11 lines are formed in it longitudinal direction. -1. The memory cell array claimed in Claim 3 wherein sald odd source lines aniongr said plurality of the source lines are connected lo the first decoder and even source lines among said plurality of [lie source hnes ill-e connected to the second decoder.

The memory cell array claimed in Claim 2 wherein said float' r gitte 1 ing j -, electrically isolated from it semiconductor substrate by a gate oxide film. 6. The memory cell array claimed in Claim 2 wherein said control gate is electrically isolated from said floating gate by a dielectric film.

7. The memory cell array claimed in Claim 2 wherein said control gate is electrically isolated from each of source and drains by a thermal oxide film.

8. A memory cell array comprising; it basic cell group in which a first, second, third and fourth unit cells are formed to use a single bit line contact in common, wherein said basic cell group is combined plurally in a longitudinal and horizontal directions.

5). The memory cell array claimed in Claim 8 wherein, by combining said basic cell group, a plurality of the source lines are formed in it longitudinal direction, a plurality of the word lines are formed in a horizontal direction, and it plurality of bit lines are formed in it longitudinal direction.

10. The memory cell array claimed in Claim 9 wherein odd source lines aniong said plurality of the source lines are connected to the and even source lines of said plurality of the source lines are first decoder connected to BAD ORIGINAL A tile second decoder.

The memory cell array claimed in Cialm 8 wherein, in salel basic cell group, said first unit cell is formed of a first floating gate, a fii-sL control gate, a first source and a common drain on it semiconduclor substrate, sald second unit cell is formed of a second floating gate, a second control grate', said first source and said common drain on said semiconductor substrate, said third unit cell is formed of a third floating gatc, it first control a second source and said common drain on said semiconductor substrale, and said fourth unit cell is formed of a fourth floating gate, said second control gate, said second source and said common drain on said semiconductor subsirate.

12. The memory cell array claimed in Claim 11 wherein said first floating gate and said second floating gate are arranged longitudinally with a second field oxide film sandwiched therebetween and said third floating gate and said fourth floating gate are arranged longitudinally with a third fic-1d oxide, film sandwiched therebetween.

13. The memory cell array claimed in Claim 11 wherein, when sald basic cell group formed of said first, second, third and fourth unit cells Is combined longitudinally to electrically isolate the neighboring basic cell groups, a first field oxide film is formed oil Ihe side of sald firsi. and third floating gates and a fourth field oxide film is also formed oil the side of said second and fourth floating gates.

14. The memory cell array claimed in Claim 11 wherein each of sald firsl' BAD 0RtGINAL second, 1hird and fourth floating gates 1 1 1 1 Is from said sem icond uc tor substrate by it gate oxide film.

15. The memory cell array claimed in Claim 11 wherein salel fit-st control gate Is electrically isolitted from each of said first and third floating gales by a dielectric film and is electrically isolated from each of said commori drain, said first source and said second source by a thermal oxide film.

16. The memory cell array claimed in Claim 11 wherein saicl second control gate is electrically isolated from each of said second and fourth floating gates by a dielectric film and is electrically isolated from each of said common drain, said first source and said second source by a thermal oxide film.

16. A memory cell array substantially as hereinbefore described with reference to Figures 3 to 11b.

Y BAD ORIGINAL.0 - 14