GB2308792A

GB2308792A - Vertical deflection stage

Info

Publication number: GB2308792A
Application number: GB9526609A
Authority: GB
Inventors: Chun Hsing Wu; Kim Heng Chong
Original assignee: Thomson Multimedia SA
Current assignee: Vantiva SA
Priority date: 1995-12-28
Filing date: 1995-12-28
Publication date: 1997-07-02
Also published as: GB9526609D0

Description

Vertical Deflection Circuit for a TV Set The present invention relates to a vertical deflection stage of a television set, especially to a deflection stage where a DC shift during changing of vertical amplitudes is reduced or can nearly be avoided.

In a common TV set, the vertical height adjustment and the center adjustment of pictures shown on a screen must be performed before the product leaves the factory or during a service mode. This alignment, which is performed either manually or computer aided, is necessary to compensate for component tolerances. The adjustment of the picture center and the adjustment of the vertical height of said picture are dependent on each other, so that when the vertical height of the amplitude increases, the average DC level and thereby the center is shifted vertically.

For this reason the center adjustment, i.e. the DC level gets misaligned during height adjustment and must be readjusted. In practice, first the picture center is adjusted by varying the DC level and afterwards the picture height is adjusted by changing the vertical amplitude.

In known systems, the abnormal DC shift during the changing of vertical amplitudes causes that the DC level and afterwards the vertical amplitude must be readjusted. Sometimes it may even happen that these steps must be repeated several times.

It is already known to improve the adjustments by compensating the shift of the DC level during the height adjustment by software procedures used for automatic adjustment devices. But the compensation of the DC vertical shift by the software control is imperfect, so that a further readjustment is normally required.

DE-OS 37 43 352 Al shows a clocked vertical deflection stage with a processor wherein the long term change or long term drift of the vertical picture position is eliminated by the integration of the voltage of the deflection coil which is applied to the feedback input of the processor.

Therefore short term DC drifts during the adjustement of the vertical amplitudes are not eliminated.

It is therefore an object of the present invention to provide a vertical deflection stage, wherein the abnormal DC shift during the changing of the vertical amplitudes in the adjustment procedure is decreased or eliminated.

This object is solved by the subject matter of claim 1. Preferred embodiments are subject of the dependent claims.

The present invention comprises a vertical stage circuit of a TV set, a monitor or thelike comprising a ramp generator, a buffer stage and a power amplifier, wherein a resistor is provided between the ramp generator and the power amplifier.

There is a significant compensation of the DC vertical shift by just adding the feedback resistor to the ramp amplitude control in the vertical deflection stage. Also the vertical deflection stage according to the invention does not rely on the additional software in the compensation of the abnormal vertical DC shift during the vertical amplitude changes. This is shown by measurements of a preferred embodiment: I. Without software compensation and without feedback resistor Max. vertical amplitude, output DC level = 14.98 V Min. vertical amplitude, output DC level = 10.16 V.

In this case the DC level shifts in a range of 4.82 V during the changing from minimum to maximum vertical amplitude.

II. Without software compensation and with feedback resistor applied: Max. vertical amplitude, output DC level = 12.48 V Min. vertical amplitude, output DC level = 12.97 V.

Therefore, the use of the feedback resistor decreases the difference in DC levels to 0.49 V during the changing from minimum to maximum vertical amplitude. Further advantages of the invention are the improved stability of the DC level at the output and the elimination of additional software for compensating the abnormal DC shift.

Preferably the feedback resistor is connected to the ramp amplitude control. Further the ramp generator of the circuit is driven by a signal delivered by a TV processor. This driving signal of the circuit is fed to the power amplifier via a resistor. The output of the buffer stage is provided to the inverting input of the power amplifier and the non-inverting input of the power amplifier is connected to a reference voltage. Further the circuit according to the invention comprises a control bus for delivering the control signals. This control bus may be realsied e.g. as so-called I2C-Bus as it is described e.g. in the data sheet of PHILIPS integrated circuit (IC) TDA 4685, March 1991.

A preferred embodiment of the invention will now be explained with reference to the accompanying drawing, wherein: Fig. 1 shows a circuit schematics of the inventive vertical deflection stage.

Fig. 1 shows the vertical deflection stage of a TV set, where said deflection stage is mainly realized by an integrated circuit IC, for example the TDA 1771. In the following, the description of those parts of the circuit shown in the diagramm, which are not relevant for the elimination of the DC shift problem, is ommitted.

The integrated circuit IC comprises a ramp generator 11, a buffer stage 12, a power amplifier 14, a voltage regulator 13, a thermal protection 15 and a flyback generator 16.

Vertical pulses -V are supplied from a not shown TV-processor via terminal 20 and resistor 21 to the input on pin 3 of the integrated circuit IC. This pin 3 is internally connected to the input of the ramp generator, who produces a sawtooth signal at the frequency of the vertical pulses -V.

The signal -V is further used as a clock pulse for the power amplifier 14.

The power stage 14 is driven by negative-going pulses at vertical delivered by the TV processor.

The output signal of ramp generator 11 feeds a buffer stage 12 whose task is to deliver the ramp under low impedance to pin 7. The sawtooth present under the low impedance on pin 7 is then fed via a resistor 22 to pin 8, which is the inverting input of the power output stage 14. The non-inverting input of the power amplifier 14 is internally connected via a resistor 23 to a reference voltage derived from the internal voltage regulator 13.

The output of the push-pull amplifier 14 is on pin 1. During the first half of the vertical scan, a "push" transistor inside amplifier 14 switches off while a "pull" transistor inside amplifier 14 switches on and sinks the current from capacitor 24 via a resistor 25, the capacitor 24 and the transformer 17. The sawtooth current has now reverse polarity and keeps on decreasing to more negative values.

The sensing voltage from the resistor 25 is added to this waveform via a resistor 26 and the resulting signal is fed back via a resistor 27 to the inverting input (pin 8) of the power amplifier 14. The feedback loop will then shape the output current as desired and ensure amplitude and shape stability with time and temperature.

The vertical centering is done by a control bus, e.g I2C bus. The upper portion of the vertical pulses -V can be varied by the bus and this is used by a resistor 28 to change the DC level at the junction of the resistor 26 and the resistor 27. Changing the DC level at this point will alter the DC level at pin 8 and consequently the DC level of the output current (vertical shift).

Adding an additional feedback resistor 29 with its first terminal connected to the junction of the resistor 26 and the resistor 27 and with its second terminal connected to the ramp amplitude control via a resistor 30 and pin 4, will enable the ramp generator 11 to supply the desired sawtooth current and improve the stability of the DC level at the output 1.

Claims

1. Vertical stage circuit for a TV set comprising a ramp generator (11), a buffer stage (12) and a power amplifier (14), characterized in that a resistor (29) is provided between the ramp generator (11) and the power amplifier (14).

2. Circuit according to claim 1, wherein the feedback resistor (29) is connected to the ramp amplitude control input of said ramp generator (11).

3. Circuit according to one of the preceding claims, wherein the output of the buffer stage (12) is provided to the inverting input of the power amplifier (14).

4. Circuit according to claim 3, wherein the non-inverting input of the power amplifier (14) is connected to a reference voltage generated by a voltage regulator (13).

5. Circuit according to one of the preceding claims, further comprising a control bus for delivering the control signals.