GB2308233A

GB2308233A - Gate electrode formation

Info

Publication number: GB2308233A
Application number: GB9626113A
Authority: GB
Inventors: Jae-Sung Choi
Original assignee: Hyundai Electronics Industries Co Ltd
Current assignee: SK Hynix Inc
Priority date: 1995-12-15
Filing date: 1996-12-16
Publication date: 1997-06-18
Anticipated expiration: 2016-12-16
Also published as: KR970053905A; CN1155159A; DE19652070A1; CN1172378C; GB9626113D0; GB2308233B; KR100203896B1; DE19652070C2; JPH1032334A

Description

2308233 GATE ELECTRODE AM MSTROD FOR TRE FORMATION TREREOF

BACKGROUND OF Tax INVENTION

Field of the Invention

The present invention generally relates to a gate electrode of transistor in a semiconductor device, and more particularly to a gate electrode having a structure where 10 a tungsten ailicide layer is stacked on an amorphous layer.

Description of the Prior Art

Generally, before the formation of source and drain electrodes, a gate electrode in metal oxide semiconductor field effect transistor, is formed on a semiconductor substrate having gate oxide thereon. In addition, the gate electrode is formed through patterning of polysilicon layer. Currently, however, the polysilicon layer, has been substituted for amorphous silicon or a stacked structure where metal silicide overliea polysilicon, in order to enhance its electrical and/or physical properties.

Fig. 1 is a partial sectional view of a semiconductor device having the structure where tungsten silicide is stacked on polysilicon according to conventional art.

Referring to Fig. 1, in the conventional gate structure, gate oxide of S'02 12 is formed on a 1 semiconductor subatrate 10, and polysilicon 14 and tungsten silicide 16 are stacked thereon in that order.

Polycrystalline silicon (hereinafter, referred to as polysilicon or Polysi) is a material with crystalline property, and its thin films are made up of small single crystal regions(grains) separated by grain boundaries. It is of interest to note that as-deposited Poly-Si films can be amorphous or polycrystalline, but subsequently exhibit a polyerystalline structure if subjected to elevated 10 temperatures after deposition.

Polycrystalline silicon layer 14 is mainly formed by a chemical vapor deposition method, where source for the formation of polysilicon is ailane SiH, gas. In case that the above method in applied to, average size of grain 15 ranges from 0.2 to 0.3Mm.

A tungsten ailicide layer 16 can be formed selectively by chemical vapor deposition method or physical deposition one. In case that chemical vapor deposition method is applied for the formation of tungsten silicide, a 20 semiconductor substrate 10 having objective layer of polysilicon for the formation of tungsten silicide is exposed to an atmosphere containing WF, gas. At this time, some amount of fluorine atoms in W. gas penetrates into the surface of the polysilicon layer 14, thereby existing in 25 the tungsten silicide layer 16 that is formed.

Fluorine atoms contained in tungsten silicide layer 16 during subsequent thermal annealing, penetrate into gate 2 oxide 12 via polysilicon layer 14. This is due to the existence of many penetration paths which exist because of the small size of the polysilicon grains. As a result, the thickness of gate oxide 12 becomes increased, and the electrical properties of the gate electrode 12 are deteriorated.

Meanwhile, in case where tungsten silicide 16 is formed on amorphous silicon layer which is formed by chemical vapor deposition using silane gas of SiH4, grain size of amorphous silicon formed, is larger than that of polysilicon. Nevertheless, the penetration of a large amount of fluorine atoms into gate oxide continues to occur because the grain size of amorphous silicon is still relatively small at 0.5 gm.

is SMY OF TEM INVENTION Accordingly, it is an object to provide a gate electrode and method for the formation thereof capable of preventing the deterioration of electrical properties and increase in thickness of the gate electrode, in a stacked structure of polysilicon layer and tungsten silicide layer.

According to the present invention, a gate electrode has a polysilicon layer consisting of very large grains on gate oxide, wherein the polysilicon layer minimizes penetration paths of impurities toward the gate oxide.

BRIEF DZ5CRIPTION OF THE DRAWINGS 3 The novel features believed characteristic of the invention are set forth in the appended claims. The invention itself, however, as well as other features and advantages thereof, will be beat understood by reference to the detailed description which follows, read in conjunction with the accompanying drawings, wherein:

Fig. 2 is a partial sectional view of a semiconductor device having the structure where tungsten silicide is stacked on polysilicon according to an embodiment of the present invention.

DETAILED DESCRIPTION OF TEM INVENTION

Hereinbelow, preferred embodiment of the present invention is described referring to the attached drawing.

Fig. 2 is a partial sectional view of a aemiconductor device having the structure where tungsten silicide is stacked on polysilicon according to embodiment of the present invention.

Referring to Fig. 2, a semiconductor device is provided, which a gate oxide 22 is f ormed on a semiconductor substrate 20, amorphous silicon layer 24 having larger grains and tungsten silicide layer concaining 4 is a few amount of fluorine atoms are patterned and stacked thereon in that order. Herein, said tungsten silicide used is WSi2.

The amorphous silicon layer 24 is formed by chemical vapor deposition using disilane gas of Si.R,, as source for the formation, where constituent grains of the amorphous silicon 24 range from 2 to 3pm in size. The size of the grain is 10 times larger compared to that of the polycrystalline silicon according to the conventional case.

to As a result, said polycryatalline silicon layer 24 decreases the number of penetration paths into gate oxide 22 to a least 1/10 to that of the polycrystalline silicon used as the conventional gate electrode. A.9 a result, the thickness of gate oxide 22 does not increase, and electrical properties are deteriorated.

The gate oxide 24 is formed by a thermal growth of exposing a semiconductor substrate 20 of single crystalline silicon at an atmosphere of 0. gas and a predetermined temperature.

Afterwards, amorphous silicon layer 24 is formed by a chemical vapor deposition method of exposing the substrate of a first state having gate oxide 22 thereon at a predetermined temperature and pressure, thereby having large grain size of 2 to 3 gm. it is preferable that the pressure range should be of 0.1 torr to any value from io to 90 torr.

Lastly, a tungsten silicide layer 26 is formed by a chemical vapor deposition method of exposing the substrate 20 of a second state having gate oxide 22 and amorphous silicon layer 24 thereon in that order in an atmosphere containing WF, gas and -at a predetermined temperature and pressure. By thermal reactions at the above conditions, tungsten atoms are first decomposed from WF., and then reacts with amorphous silicon, resulting in the formation of tungsten silicide layer 26. During the formation of tungsten silicide layer 26, fluorine atoms decomposed from to WF, gas penetrate into the amorphous silicon layer 24. As a result, some of fluorine atoms exists in said tungsten silicide layer 26.

Fluorine atoms in tungsten silicide are penetrate again into the underlying gate oxide 22 during a subsequent thermal process, but the penetrated amount is remarkably decreased due to the considerable decrease in the penetration paths of fluorine atoms. This decrease is because constituent grains become large in size, and thereby decrease the number of penetration paths of fluorine atoms into gate oxide 22. As a result, the increase in thickness of gate oxide and deterioration of electrical properties are minimized.

From results obtained from experiments, it was observed that the increase in thickness of said gate oxide 22 is minimized to a range of SA to 10A, which is decreased by 2001r when compared to the conventional case. In addition, from results obtained from an experiment where 6 constant current was applied to gate electrode, it was observed that the electrical properties were also enhanced by 200k compared to that of the conventional gate electrode.

As described previously, the present invention, in a gate electrode with polycide structure that polycrystalline silicon and tungsten ailicide is stacked on gate oxide in that order, substitutes the polycrystalline silicon for amorphous silicon. and thereby can minimize the penetration of fluorine atoms contained in the tungsten silicide into the gate oxide. As a result, increase in thickness and depression in electrical characteristic of gate oxide can be minimized.

Other features, advantages and embodiments of the ji invention disclosed herein will be readily apparent to those exercising ordinary skill after reading the foregoing disclosures. In this regard, while specific embodiments of the invention have been described in considerable derail, variation and modifications of these embodiments can be effected without departing from the spirit and scope of the invention as described and claimed.

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Claims

MAT 13 CLAIMED IS:

I. A gate electrode comprising: a gate oxide formed on a semiconductor substrate; 5 an amorphous silicon layer formed on said gate oxide by a chemical vapor deposition using disilane gas; and a tungsten silicide layer formed on said amorphous silicon layer. containing a few amount of impurity, wherein said amorphous silicon layer has a grain size at such a degree that penetration of said impurity into said oxide during a subsequent thermal process, is decreased.
2. The gate electrode in accordance with claim 1, wherein said grain size ranges from 2 pm to
3 pm.

Is 3. The gate electrode in accordance with claim 1. wherein said impurity is fluorine atoms.
4. A method for forming a gate electrode comprising the steps of: providing a semiconductor substrate where gate oxide is formed thereon; thermally annealing said semiconductor substrate inserted in a reactor for a chemical vapor deposition, to form an amorphous silicon layer on said gate oxide; and forming tungsten eilicide layer on said amorphous silicon layer.

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5. The method in accordance with claim 4, wherein said tungsten silicide in WS12.
6. The method in accordance with claim 4, wherein pressure of said reactor ranges from 0.1 torr to any value from 10 to 90 torr.
7. The method in accordance with claim 4, wherein temperature of said reactor ranges from 4500C to 5800C.

In 9