GB2307569A - Indirect addressing by use of direct addressing instructions - Google Patents

Description

2307569 A Method for Replacing Indirect Address According to the

addressing method of a conventional NTU (Micro processing unit), the indirect addressing method thereof is to be done by using an indirect register (such as an index register) and a data register (such as a data block register) so as to obtain an actual address. The actual address is substantially the sum of the implied value of the data register and the value stored in the indirect register; therefore. when performing data access, some space in the data register must be taken, and a considerable time will be wasted, i.e., the efficiency of use will be reduced.

The indirect address register and the virtual address according to the present invention are deemed special register in real application; such register address placed in the memory address is derived from the method of memory mapping FO, and is expanded to the current special register, such as a timer/counter, an interrupt control register, and an FO register. Such mapping method used in the micro processors may include the IC of M68000 series,, and in the micro controller may include the IC of Intel 8051 series; particularly, such method is mostly used in the micro-controller, and its advantages are as follows:

(1). When a register address uses a memory address, no additional circuit upon designing a special register is required for decoding operation, i.e., requiring only the circuit of the original memory for decoding without providing additional instruction and instruction-decoding circuit; therefore, such method can simplify the IC considerably.

(2). In a micro-controller and a micro-processor there are more operation requirements to the aforesaid special register; for example, when an FO doing bit operation (to set a bit or to clear a bit), such circuits used in the special register and the memory separately may 1 only be used for the special register, i.e., some functions will be limited. If the special register and the memory address are used together, the aforesaid new fimctions will expand to the memory, the fimctions of the memory will be increased considerably.

The conventional instruction upon being decoded will be divided into direct addressing and indirect addressing, which then have their instructions completed through diflerent flow charts as shown in FIG. 1.

conventional time sequence (refer to FIG. I):

Accordmig to the example of two-level pipeline structure:

FETCH DECODE+ EXECUTION FETCH DECODE EXECUTIONI In that case,, the time for DECODE and EXECUTION will limit the fimctions of the whole micro-processor.

FETCH+ EXECUTION DECODE FETCH+.: DECODE 1 EXECUTIONI In this case, 0 signals after DECODE must be recorded for 3o EXECUTION use.

The conventional addressing mode and the instruction operation method usually can provide a powerful function; the circuit required by a more complex instruction would be more difficult to design, and would require longer designing time; in other words, it would be much difficult to use the Pipeline and Super scale technique to 2 increase the functions as a whole; therefore, an idea of RISC (Reduced Instruction Set Computer) has been proposed so as to have the instructions of complex functions divided into the most simple instructions by means of statistics and analysis. Because of simplicity, such can provide a higher efficiency, can be modified easily, and can be arranged in a regular order. Therefore, the pipeline and super scale technique can be used easily to provide a higher function. The present invention is deemed to conform to the aforesaid simplicity in terms of changing instructions, i.e., the time sequence order can easily be used for the pipeline technique to increase efficiency; the aforesaid advantages can not be provided by the conventional instruction decoding; such replacing method is deemed having industrial value in the field of developing high-efficiency microprocessor.

This invention relates to a method for replacing indirect address, and particularly to a method for reading and writing an actual register after obtainin an actual address code by means of a virtual address and an indirect register connected lines, and through an address code converting process.

The prime object of the present invention is to provide an efficient indirect addressing method, i.e., to read and write a data with the method without wasting the data register space and the operation time. The prime feature of the method is able to read and write a virtual address by means of an indirect address register, i.e., be g able to read and write an actual register designated through an indirect address register.

The method for replacing indirect addressing according to the present invention is different from the conventional instruction decoding method because of the instructions used being all direct addressing instruction; thereupon indirect addressing mode has had the virtual address OOH changed into the actual address before the instruction decoding; therefore, the design for the operation and the control element in the micro-processor having been simplified into the direct addressing mode only.

3 The instruction decoding method according to the present invention as shown in FIG. 2:

The advantages of the present invention are as follows:

(1). The instruction compilation need not distinguish direct addressing instruction and indirect addressing instruction; in other words, the same number of instructions can provide versatile lo instructions upon encoding instructions, and all such instructions can provide the fimctions of direct addressing and indirect addressing, i.e., without reducing the addressing functions upon the instructions being increased.

(2). Since the instructions did't distinguish between the direct addressing instruction and the indirect addressing instruction, the instruction-decoding circuit will be more simple than the conventional circuit.

(3). Regarding the time sequence, the present invention is deemed having better flexibility than that of the conventional decoding circuit.

(4). By using the virtual address OOH as the method of judging the indirect address. the code OOH is deemed having advantages of easy identification and replacing; it can simplify both the design circuit and the actual circuit. Since such address can only occupy the starting address of the memory, it would aflect the integrity of the memory little.

An embodiment of the invention is described by way of example with reference to the drawings, in which:

FIG. 1 is a conventional of decoded time sequence.

FIG.2 is the decoding method of the present invention.

4 FIG.3 is a diagram of an embodiment according to the present invention, showing a method for replacing indirect addressing.

FIG.4 is a flow chart of the embodiment according to the present invention.

FIG.5 is a brief virtual address detecting circuit in the embodiment according to the present invention.

FIG.6 is a brief circuit of the indirect address register and the address code converting circuit in the embodiment according to the present invention.

Referring to FIG.3, the diagram of the method for replacing indirect addressing comprises a virtual address region 10, an indirect address register 20, and an actual register 30. An address signal (addr) is coupled into the virtual address region 10, and it will pass through the reference relation (ref) between the indirect address register 20 and actual register 30; then, a data will be sent out through "data ouC,that is the actual address. In fact. the aforesaid "ref' is done through a series of circuits of detection and conversion; such "ref' is described as follows: Referring to FIGA, a flow chart of the present invention, it shows that when an instruction is processed, an instruction code 40 will be transmitted into a virtual address detecting circuit 50 to find out whether the instruction is using an indirect addressing or not; then an indicating signal "ind" from the virtual address detecting circuit 50 will be sent out to the indirect address register 80 to determine whether such indirect address register 80 is to be used or not. The address code "addr" of the virtual addressing detecting circuit 50 is coupled to the address code converting circuit 60; the output terminal of the indirect address register 80 is connected with the address code converting circuit 60 for decoding so as to obtain an actual address 70.

According to the embodiment of the present invention, OOH is used as the virtual address, and the virtual address detecting circuit 50 can be simplified into a multi-input NOR gate as shown in FIG.5, which is a brief diagram of the virtual address detecting circuit of the present invention. When an address code is OOH, the indicating signal "ind" will be FUGH so as to convert the address in the indirect address register, and to trigger the address code converting circuit; then. the decoding step therein will provide an actual address to replace the virtual address.

As shown in FIG. 6, the indirect address register 80 includes a D-type flip-flop (or D-type locking unit) and a NAND gate. The address code converting circuit includes an inverted and a NAND gate.

The features of the present invention are described as follows:

Time sequence arrangement of the present invention (referring to FIG. 2):

According to the example of two-level pipeline structure:

FETCH+ DECODE2+i DECODE 1 EXECUTION FETCH + DECODE2+1 DECODE 1 EXCUTION 1 When the time of DECODE and EXECUTION limits the functions of the whole microprocessor, the DECODE 1 may be put in the FETCH CYCLE.

IFETCH DECODE EXECUTION FETCH DECODE EXECUTION In the event of FETCH time being too long (longer than that of DECODE and EXECUTION), the DECODE 1 and DECODE 2 may be combined together and put in the EXECUTION CYCLE.

3 D 6 As described above, according to the present invention, the operation and the control unit in a microprocessor have already been designed and simplified into a direct addressing mode. In the conventional instruction decoding method, the direct addressing and the indirect addressing will be divided upon decoding, and then difilerent processing steps will be used to complete the functions of an instruction.

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Claims (6)

Claims:

1. A method for replacing indirect addressing comprising the steps of.

an instruction code being transmitted to a virtual address detecting device to judge said instruction code being indirect addressing; an indicating signal generated and being transmitted to a indirect address device to active said indirect address device; an address signal from said virtual address detecting circuit being transmitted to an address code converting device; output of said indirect address register also being transmitted to said address code converting circuit for decoding to cirtain an actual address.

2. A method for replacm"g indirect addressing as claimed in claim 1, wherein "OOH" is used as a virtual address.

3. A method for replacing indirect addressing as claimed in claim 1, wherein said indirect address register includes a D-type locking unit 25 and a NAND gate.

4. A method for replacing indirect addressing as claimed in claim 1, wherein said address code converting circuit includes an inverter and a NAND gate.

5. A method for replacing indirect addressing as claimed in claim 1, in which said virtual address detecting circuit is able to simplified into a NOR gate with multi-input terminals.

6. The method of claim 3, in which said D-type locking unit is a Dtype flip-flop.

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