GB2397984A - Architecture for increasing density of channel bank in a digital carrier system - Google Patents

Abstract

A double density channel bank architecture compatible with an existing D4 backplane and D4 channel units transmits or receives pulse code modulated (PCM) data on a pulse amplitude modulated (PAM) bus, while simultaneously transmitting or receiving PCM data on a PCM bus. Increased density channel units (CU) 100 are configured for insertion into card slots and may utilise a codec 177 and a digital/analogue converter (DAC) 176. The channels A, B may be split in groups A1, A2, B1, B2 to increase capacity.

Description

ARCETECII FOR INCREA SING D rNSITY OF GHANNF.I BANK

IN DIGITAL COMER SYSTEM

Field of the Invention:

The invention relates to a method and apparatus for increasing the density of a channel barl: in a T-1 or other digital carrier system.

s Background of the Invention:

In a T-1 digital comer System., a voice signal is sampled. TEle resulting pulse amplitude modulated (PAM) signal is converted to an 8-bit pulse code modulated (PCM) digital signal which is interleaved with 23 other channels for transmission over a T-1 line at a bit stream rate of 1.544 megabits per second (Mbps). T-1 signals are processed in a lo channel bank such as the channel bank 20 depicted in Fig. 1. In a conventional digital channe! bandy 24 channels Are collectively referred to as a digroup. Channel banks typically comprise =-o digloups A and B to create a 48-ch^-el framework for transntting and receiving on two duplex T-1 carders.

As shown in Fig. 1, the channel bay comprises a chassis 24 having physical card i' slots 26 in o which at leas: 48 channel unit (Cog) cards 28 can be nserted, as well as a number of common equipment cards 30 described below. A chassis 24 typically has four rows of card slots with receive physical card slot locations per row. Two rows of MU cards can constitute a digroup which uses the 24 channels of a T-1 connected tO the channel bum The Flu cards 28 and the common equipment cards:0 corrununicate with each other via a backplane which comprises a pulse amplitude modulated (PAD bus for analog signals and a pulse code modulated (PCM) bus for digital signals. The backplane 32 is,''lustra ed in Fig. 2 w ith respect to two curds 28 from t\NTO shelves inserted in the chassis 24. The cards have edge connectors 34 with pins 36 that are electrically connected to terminals 38 on the backplane when the cards are inserted into the physical c-d s10.5 36 of the ch-lel basil: chassis 7A, to Fig. 3 depicts CUs and corurnon equipment associated with a conventional D4 channel bank 40 for illustrative purposes. Twenty-four channel units 42Ai through 42A24 and twenty-four channel units 42B' through 42B24 constitute the voice/data circuits of digroups A and B. Each channel unit in the digroup A is connected to a transmit unit A (IU A) 44A and to a receiver unit A MU A) 46A. Sirnilarl,v, each channel in the digroup is B is connected tO a transmit unit B (TU B) 44B and to a receiver unit B (RU B) 46B.

Each digroup A and B has an alarm control unit (ACID 48A and 48B, respectively. The cor.ron equipment also includes a line interface It trier n 50, a trunk processing ''nit ECU) 52, a transmit pre-equaer 545 an office interface unit 56, a -to-DC converter 58 and a power distribution unit (badly) 60.

The central office floor space of regional Bell Operating Companies (/BOCs) is increasingly in short supply. The ongoing addition of bully D4 bars to meet increasing consumer demands for telecommunications service, as well as the increasing number of non-RBOC carriers that are co-located within the same office, has exhausted available room or floor space in some central offices. Accordingly, a need exists for a channel 2s bank with increased density, that is, a channel bank which can process more channels (e.g., more than 48 channels) than conventional channel banks in relation to the amount of room a channel bank occupies in a central office or other RBOC facility. A number of channel banks and channel unit cards have been proposed which allow a reduction in the physical size of a channel bank. These channel banks and cards, however, are disadvantageous because they are not easily retrofitted into existing D4 bays, and do not allow for the use of existing channel unit cards and cormnon equipment. Thus, a need exists for a channel bank architecture which increases the number of T-1 channels hallowed thereby, End -w-l-nch a1SG Sllv-wa fc,r plug-"lld-plav u?,,ades to erg C4 bays.

Surnrnary of the Invention: In accordance with the present invention, a double density channel bank architecture is provided tO overcome the problem of drn;rshing central office space to accommodate additional channel banks.

In accordance -wi-Lh one aspect of the present nve,ltion, the double density channel bank architecture is compatible with an existing D4 backplane, as well as existing lo D4 channel units and a number of common equipment components. Double density channels units and common unit components ale provided which can be inserted into an existing channel bank for upgrading tO accommodate additional channels per slots.

i In accordance with another aspect of the present invention, a channel unit is configured to transmit or receive PCM data on the p old bus of a channel bank, while is simultaneously transmittir.g or receiving PCt/r data on the PCM bus. One double dens ty chnnel'n;t can therefore provide data for two transmit and two receive T-l timeslots to increase the capacity of a D4 channel bank from 48 channels or two duplex T-1 carriers lo 56 charnels or four duplex - -. earners.

In accordance with yet another aspect of the present invention, the channel bank architecture provides ti ning of the PCM data on the PAM bus to avoid bus contention when an adjacent conventional channel unit provides an analog sample on the PAM bus.

A method of increasing the number of digital carrier channels processed in a channel bank is provided comprising the steps of: (1) formaLLir,g a first sisal for digital transmission on a first carrier channel if the first signal is not digital; (2) formatting a Is second signal for digital ransrnission on a second carrier channel if the second signal is not digital; (3) providing a portion of the second signal on a pulse code modulated bus of the channel bank; and {4.) provid;mg a portion of the first signal on a pulse amplitude modulated bus of the channel bank, the pulse amplitude modulated bus being operable to transport analog signals from Analog cards in the charnel bank, the portion of the first signal being provided on the pulse amplitude modulated bus using selected timing to avoid bus contention with the analog signals. r

In a channel bank having a chassis comprising card slots for receiving charnel units alga common equipment components and operable cG provide sisals to duplex digital comers, the common equipment comprising receive mnits5 transmit units, a line interface unit and a trunk processing unit, the channel bank having a backplane comn.sing a pulse code modulated bus and a pulse amplitude modulated bus, the channel Àn;ts provi:r.g a Single subscriber circuit for transmitting and receiving signals via a single duplex channel on one of the duplex digital carriers, an improved channel bank zircon texture Provides increaser! clensitv of subscriber circuits in the channel bank without changing the card slots and the chassis. The improved charnel bank architecture lo comprises an increased density channel unit configured for insertion in one of the card slots, the increased density channel unit being operable to provide a portion of a first second signal on the pulse code modulated bus of the channel bank and a portion of a second on the pulse amplitude modulated bus substantially simultaneously to support two of the subscriber circuits in the corresponding one of card slots.

Brief Description of the Drawings:

Able various aspects, advantages and novel fa--lres of the present invention PUTT be more really comprehended from the following detailed description when read in conjunction with the-appended drawings, in which: JO Fig. 1 is a front view of an exemplary channel bank; Fig. 2 is a cross-sectional view of two channel unit cards in the channel bank of Fig. 1; Fig. 3 is a block diagram of a conventional D4 channel bank comprising common unit components and channel units; Fig. 4 is a block diagram of a double density channel It constructed in accordance with an embodiment of the present invention; Fig. 5 is a block dial of double density common unit components constructed in accordance with an embodiment of the present invention lo operate with one or more of the double density channel units depicted in Fig. 4, as well as with conventional analog and digital channel units; and Figs. nA and 6B are diagrams iuslraling lirrlirlg waveforms for transmit and receive comnonems of the double density channel unit of Fig. 4.

Throughout the drawstring figures, like reference numerals will be understood to refer to like parts arid components.

Detailed Description of the Preferred Embodiments:

Figs. 4 and 5 depict a channel unit (Cu') 100 and common urn' components 102, respectively, which are constructed in accordance with an embodiment of the present invention. With reference tO Fig 5, the common unit components 102 generate and lo transmit signals to CUs indicated generally a: 104 (e.g., voice and data CUs, as well as CUs 100 of the present invention) and receive signals from the CUs 104. The signals are generally indicated at 106 in Figs. 4 and 5. The signals 106 are preferably compatible i-h a D4 backplane. Thus, the common mat components 102 we cor..patble with CUs of the present invention, as well as wash conventional analog and digital channel is Digits such as those depicted in Fig. 3.

In accordance with the present invention, the double density CU 100 and the common unit components 102 are operable to provide PC]vI data lo the PAM bus while, at the some rime, -mowing conventional analog chorine! 1 nits to provide PAM signals on the PAlv3: bus. The double density CU 100 therefore provides PCM data to both the PAM bus and the PGM bus tO double the T-1 or other carrier channel capacity that is available per physical card slot 26 in a conventional channe! bank 20. Accordingly, the double density Clu 100 and the common unit components iO2 use existing backplane buses and physical card slots in a channel bay (e.g., a digital D4 channel bank) to support, for example, 96 circuits for channel bank chassis 24, as compared with the 48 non-concentrated circuits per chassis supported by a conventional channel bank 20. The double density CU lOO and the common unit components 102 of the present invention preferably do not increase the operating speed of any backplane circuit to maintain compatibilitywith an existing channel bank chassis, as -v-ell as to rue any high frequency roll-off associated with multi-layer backplanes in channel banks.

The double density CU 100 of the illustrated embodiment is a Dial Pulse Terminate/Foreign Exchange (DPT/FXO) channel unit which serves two subscriber lines. The DPT/FXO CU 100 provides either a standard DPT interface or a standard FX ne'4zce over a D4 ca, ier System for each of the two subscriber lines. It is to be understood that different types of the double density CU 100 can be used such as a CU iOO configured to be an office channel unit (OCI1) incorporating 2-wire digital data s system (DDS) technology. Signaling over the D4 carrier system can be programmed for compatibility with different types of far end devices such as a D4 channel bank or an SLC-96 bark The DPT/FXO CU 100 can he used with a DPO channel unit, for example, to provide a Direct Inward Dial (DID) link, with a digital private branch exchange (PBX), or with a 2FXS-type CU at the far end of the digital carrier to provide a lo foreign exchange link With reference to Fig. 4, the double density CU 100 of the present invention comprises an application specific integrated circuit (ASIC) iO8, and two channel unit modules 110 and 12 that are essentially mirror images of each other and are hereinafte referred to odd and even modules 110 and i12, respectively. one ASIC iO8 receives and is transmits the signals 106 with respect to the common unit components 102 and -Lhe backplane of the channel bark The odd and even modules 110 and 112 are connected to the telephone r etwol-k Ma respecr-ve pairs 114 and 116 of tip m and ring (R) lines.

With reference to Fig. 5, the conunon unit components 102 comprise two additional digital DS1 circuits connected to the backplane and described below which are not supported in existing common units; otherwise, no changes to the backplane of a channel bank are needed to implement the present invention. A number of standard D4 common units are used such as an ACU, a PDU, an office interface unit (OILS), and TPIJ equalizers. For illustrative purposes, The ACE 118 is shown in Fig. 5, along with selected common equipment. The receive unit (RU), the transmit unit (111) and the IT.3U of conventional common unit equipment are replaced with a double density RU 120, a double density Mu 122 and a double density TPU i24, respectively, in accordance with the present invention. In addition, a modified L.IU 126 is used in lieu of a conventional LET. The modified LIU 126 incorporates modifications to one circuit path and supports two channels.

As stated previously, the PC/r and PAM buses of a D4 backplane are used in accordance with the present invention to simultaneously transmit two bytes of PCM data betv;7een flat Conner. ur,it combo tents In: Ond fee double denim, channel cards 190.

In contrast, conventional D4 systems use either the PHI bus to transmit an analog sample or the PCM bus to transmit one byte of data. The double density RU 120 and the double density TU 122 use conventional analog-todigital and digital-to-analog converters, as indicated by the digitaiianaiog (/A) switches 98 and 130, to support both conventional channel units that do not use two or more time slots or channels, as =..'ell as provide PC M support of both channels in a double density CU loo.

To avoid TIRES issues, a double density channel bank architecture having double density common unit components 102 and double density channel cards 100 in lo accordance with the present invention divides each standard D4 digroup A and B into two separate digroups, that is, A1 and A2, and B1 and B2. The digroups A1 and B1, for example, use a DS1 interface on the modified LiU which is similar to the DS1 interface on a conventional LIU. The digroups A2 and B2 use additional DS1 interface leads which are connected in accordance with an embodiment of the present invention to t5 previously unused pins on the channel bank RU edge connector and on the channel bank TU edge connector. Accordingly, the double density TU 122 services the digroups A1 and A2 and Opel ares as a To tinsel it LTrJ for the 1;gro,p 9. The double dens ty RU 1?0 services the digroups A1 and A2 and operates as a Receive LIU for the digroup A2. The double density TU 122 also services the digroups Bl and B2 and operates as the Transmit LIU for the digroup B2. The double density RU 120 also services digroups B1 and B2 and operates as the Receive LIU for the digroup B2.

Tulle double density RU in Fig. 5 has the r'lnctionaLty of a conventional superframe/extended superfrarne (So/ ESF) LIU. The additional DS1 interface leads are preferably connected to the pins 51 and 52 of the RU edge connector which are unused a conventional channel band:. the double density channel batik of the present invention preferably uses conventional sequential time slot counting. Thus, backplane traces normally used by a conventional TPU to force IU and RU sequential rime slot courting, or DID or D2 time slot counting Ore available in the double density channel bank to establish a communication low bem-een the double deposit RU 12n and the so double density ID 122 through the double density TPU 124, as illustrated via the internal control modules 132 and 134. The outgoing, additional DS1 transmit leads are connected to pins on the channel bank llJ edge connector (e.g., pins 51 and 52) that are not used in a conventional channel bank.

In accordance with the presert invention, a charnel bank such IS a D4 channel bank is upgraded using two double density RUs 120, two double density TUs 122, a modified LIT 126 fund a double density TPU 124. Pig. 5 illustrates one double density MU 120 and one do-utile derlsi^Ly- 1 122 for use with a divided digroup A1 and id. It is to be urderstood that another double density RU/TU pair is used for the divided digroup B1 and B2 which also operate with the modified LIU 126, the double density - r _. À À . À . . _. 1 l u and one AU 16 aeplctea m rig. a, along with omer common equipment such to as a PDU 60 and so on. Each digroup A1, A2, B1 and B2 provides signals for separate transmit and receive T-1 pairs. Thus, the channel bank architecture of the present invention supports four duplex T-1 carriers, that is, two more duplex T-1 carriers titian a conventional D4 channel bank. Fig. 5 illustrates two duplex T-1 carriers provided by the divided digroup A1 and A2, for example.

is The operation of the common unit components 102 illustrated in Fig. 5 in connection with a double density CU 100 (Fig. 4) or other CU will now be described.

The double density T u 122 receives signals (e.g., DSO data) from customer premises equipment (CPE) via the CUs 104. The double density R(J 120 receives signals from the network (e.g., an OSS) for delivery to a customer via T and R leads connected to a channel unit. The double density CU 100 operates in accordance with transmit sequence control leads (e.g., TSP and TSC:3 and a clock signal (e.g., TDCLK) provided by the frame timing generator 136 to decode its channel strobe using TSP and TSQ and to transmit data onto IPCM in a respective one of multiplexed time slots (e.g., 24 time slots) of a rnultickannel digroup (e.g., digroup A1). lithe clock signal is 1.544 MU and 2< the t.-lsrl-ssion of eight bits per Probe corresponds to one 64 Imps /DSn-) channel for T-1 line. The double density TU 122 collects 192 bits, that is, eight bits from each of 24 channels, from the IP(= bus, appends a framing bit using a superfrarne (SF) framer and demuliiplexer 140 and outputs the resulting PC::M stream onto the PC1 bus 132.

For receiving operations, incoming T-1 carrier signals from one of the two T-1 receive carriers for the divided digroup A1 and A2 are received via the modified LIU 126 or the double density RU 120, which provide LIU functions for digroup A2, as stated above. The SF framer and demultiplexer 142 converts the extended superframe formatted sisals to superframe folnatted signals, as necessary. The double density:RU synchronizes itS timing with the DS1 framing pattern of the received signal and supplies charnel 'it control signals E.g., ASP, PQ and PiViD) to the channel writs s usage the frarlle timing generator 138 LO aglow each channel units LO decode ilS channel select strobe and extract its corresponding byte of data from RPC The TP.4 and RPAM provide additional buses with which analog channel units deliver and receive pulse amplitude modulated samples of analog signals to and from, respectively, the double density TU 122 and the double density RU 120.

to The double density RU 120 and the double density TIC 122 operate with conventional CUs. As stated previously, the channel bay architecture of the present invention doubles the density of a conventional channel bank by providing two channels (e.g., hereinafter referred to as odd and even time slots) per physical card slot location.

In such an arrangement, a conventional CU uses odd tLme slots, for example. The even time slot for that physical slot is not used. Thus, if only conventional C:Us are connected to slots in a shelf, the T1 associated with that digrroup (e.g. digroup A1) has traffic only in the odd-numbered time slots (i.e., time slots 1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21 and 23).

If a double density CU 100 is used in the first physical card slot of a channel bank in lieu of a conventional CU, time slots 1, 2, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21 and 23 are used.

In a conventional D4 channel bank PAM and PCM samples occur at slightly different times. As a result, a potential incompatibility exists when a conventional unit is inserted hereto ale adjacent Cal d slot in the charnel bunk chassis with. respect to 2 double density CU 100 of the present invention. The double density channel bank architecture of clue present in-velltio,l therefore,llodicles backplane vperaioll to avoid bus contentlu 2s by phase shifting the delivery and sampling of even channel PC2vI data presented on the PAM: bus. The placement of PCM data on the PAM bus in the transmit and receive directions is timed in accordance with the present invention to avoid bus contention, as illustrated in the timing diagrams in Figs. 6A and 6B.

With reference to Figs. 6A and 6B, clock signals TDCLK and RDCLK are provided in the transmit and receive directions. Signals TSQ and TSP in the transmit direction and signals RSQ, RSP and RWD in the receive direction operate as address 1O f decoders to indicate which digroup channel has access to the PAM bus indicated as TPAM or RPAM in Figs. 6A and 6B. The signals Two and RWD indicate when signals are provided to the prim bus. For illustrative purposes, the Two signal and the RWD signal are active high. Two active high T.71) periodic are illustrated in Fig. 6A. T he first active high period indicates the t;-=lsr,lit tulle for a panicky double density- CU 10.

The next active high period for the IBID signal corresponds to the next card slot location (e.g., a convention CU could place an analog sample on TPAM during this acLl-v-e l-gh peiicic). cccii-i-lgly, P<vI 3-La prefeiabl-; apoa:-s Oil hc 11-AM b-u.s beginning at the falling edge of the previous active high Two signal and ending at the lo falling edge of the current Two to avoid bus contention with any analog sample being provided on TPAM during the next Two window. Similari, PCM data preferably appears on the RPAM bus after the falling edge of the previous RWD signal and ends before the leading edge (i.e., falling edge) of the current RWI) Lo avoid bus contention.

Switches are provided to isolate the C:U circuits from the TPAM and RPAM buses to is avoid having any residual PCM signal on the bus for the next sample. The PCM data is provided "n the transmit Ad receive directions to the TPCI and RPCLl buses, respectively. Thus, as stated previously, each double density MU 100 can transmi7- Do bN,,tes of data substantial\simultaneously on She channel bank PAM and PCM buses to double the capacity of the double density CU 100 and therefore the channel bank The channel bank architecture of the present invention is useful for RBOC CO applications and therefore preferably employs external timing. The divided digroups (i.e., A1 and A2, and B1 and B2) are frame synchrored to each other to facilitate robbed bit signaling. lFor the odd chamel in each divided digroup, signaling bits in the receive :'irection are received 'Isis g n4 backplane sig.nls RFA and RFR to retrieve the signaling bits from RSAB during the eighth bit position. Transmit signaling for the odd channel is inserted in the eighth bit position and placed on TPCM during the sixth and twelveth frames, as determined using the signal TFCC. The even change! in each d vided digroup uses the RFA and RFB signals to extract receive signaling bits from the RT'AM bus during the eighth bit position. Transmit signaling for the even channel is inserted in the eighth bit position and placed on TPAM during the sixth and twelveth frames, as determined using the same signal TFCC.

In a conventional D4 channel bank, a CU uses the 1 lead to inform common units wne-Lher the Go' is an analog or voice circuit (e.g., NO), a data circuit (e.g., INEN=1), or a double density CU 100 operable in accordance with the present invention. For a double density CU 100, TNEN preferably toggles between " l " and "0" every 125 microseconds. A "1/0" signature is preferably used fur double density CU cards 100. The double density CU 100 has on-board codecs 118 and 120 (Fig. 4) Lo provide a PCM output for both the odd and even channels.

F7-7 I Mel '';thec Bee p'^.7ided ok 7-he Awe 7eci7,rRU ion The Doyle density 'ID 122 to select SF/ESF or AMI/B8ZS operating for the A2 and B2 digroups.

710 At and B1 provisioning is accomplished at the modified LIT 126 in a conventional manner. The double density TO 122 provides switches tO select DS 1 attenuation.

The double density CU 100 components will now be described with reference tO Fig. 4. The "even" and "odd" designations are used herein tO refer to the functional capabilities of respective channels provided on a double density CU 100.

In addition tO the ASIC 108, two processors are provided on the double density CU 100 Dig. 4) for each of the odd fund even channels. Odd microprocessors 146 and i48 are provided on the double density Cu i00 and preferably operate irldepe.ldel.-ly of the even microprocessors 150 and 152 provided for the even channel. The main processors 146 and 150 each operate in accordance with one of three state machines, depending on a number of selection switches described below. The processors 146 and Bach' reed the scaled A/D signals from the odd TR and T scalers 154 and 156, and the even TR and T scalers 158 and 160, as well as monitor the signaling from the backplane 32 via the ASIC 108 and provide appropriate outputs. The processors 146 and also examine the settings of mode switches indicated generally at 162 and 164, :5 respectively, and set the build out capacitance (BGC) and aiignmem tone status accordingly. Outgoing signaling information is echoed on the RA and RB front panel LED's via the LED drivers 166 and 168 corresponding to the odd and even circuit modules 110 and 112. During trunk processing, the processors 146 and 150 receive timing information from the -48 SP and -48 SD leads through level conversion circuitry, as well as the RSAB lead, tO first idle and then busy the line during trunk processing.

The idlelbusy codes generated to the far end depend on signaling mode option settings. l2 E

A number of inputs to the processors 146 and 150 are multiplexed. For example, Do Be.-iches 170 and 172, option awiehea described below, SP said sin infor'aiion leads, and the Tip and Ring voltages sensed via a level converter 174 are all multiplexed on preferably six pins of the processors 146 and L50. The information that is read or written by the processor 146 and 150 is determined by how the pins are configured.

The second processors 148 and 152 in Fig. 4 monitor the attenuation switches and program the digital-to-analog converters ACs) 176 and 178 to provide the proper attenuation in the voice path. The transmit sand receive dip switches 180 and 182 are multiplexed onto the data lines of the corresponding DAC 176 and 178 in a manner t0 similar to that used to multiplex information on the main processor 146 and 150. In addition to reading dip switches and writing the attenuation information, during remote alignment with tone selection, the second processors 148 and 152 each send samples at an 8 kHz rate to the corresponding DAC 176 and 178 to provide a 1 ldIz tone to the PAM interface to the far end, that is, the hybrid interface 184 and 186.

is The hybrid interface 184 and i86 in Fig. 4 provides the interface between the external Tip and Ring leads to the switch, and the attenuation circuitry. It splits two-way transmission on Me external pc Tic the Transom t and Receive paths used internally on the card. Two access points on the maintenance access connector (MAC) of the CU card allow customer access to the Tip and Ring leads for testing purposes. The hybrid interfaces 184 and 186 each have respective switches 185 arid 187 for selecting the interface impedance, as well as means indicated at 188 and 189 for applying Build Out Capacitance (BOC) to compensate for line capacitance and keep the hybrid interface balanced. The processor 1476 and 150 compares on-hook and off-hook A/D converter measurements. 'Ihe result is used to reference a cable that provides a three bit BOC ot tput.

The DACs 176 and 178 in Fig. 4 provide programmable losses to be inserted in the tNVO signal paths following the hybrid interfaces 184 and 186, respectively. The DACs 176 and 178 include multiplying DAC chips that set the gains. In accordance with the present invention, the DACs 176 and 178 are used in an unconventional manner in that they receive one digital input at initialization and use the input to multiply with the analogsignal continually. The corresponding second processor 148 and 152 samples the

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user attenuation selection from the dip switches 180 and 182 approxLrnately once per second and sends the information to the DAC 176 and 178. Codecs 178 and 179 perform the transmit encoding (i.e., A,'D conversion) and the receive decoding (.e., DiA conversion), as vrell as the transmit and receive filtering.

Two Nodules, that is, a TPCll-on-TPAM module 191 and an RPCIM-on-RPAM module 190 are provided as backpd;^ie inte'ace circuitry which are similar to the PCM on-PAM interface that is used on existing D4 cards. Analog switches, controlled by TFET and RFET, provide isolation between PCM signals and PAM signals on the PAM bus when the double density CJ 10v is -used wl- .Cunrl^rrl nil voice channel units.

i0 Switching the mode switches 170 and 172 from a current mode, that is, one of loop start (LS), ground start (GS) or dial pulse terminating (DPT) mode, momentarily to another mode and then back to the desired mode activates remote alignment. During remote aligurnent, the processors 146 and 152 force signaling in the transmit direction to be LCF to force activation of the far end TG relay. This allows the installer to connect is test equipment and measure loss. The RA and RB leads flash on and off once per second to let the installer know that the double density CU 100 is in the remote alignment mode. ne double density' CU 100 also sends a 1 kHz, O dBmO tone tO the far end, bypassing the voice signal, as wen as a similar tone tO -he T),/T)T6TC- pear to help identify cable pair location. Remote alignment continues until the user momentarily moves the switch away from the desired operating mode, or 20 minutes elapses.

The tone generators 171 and 173 in Fig. 4 are each enabled by their corresponding processor 146 and 150 when a user selects the remote al gnment with tone feature. Able processor 146 and 150 sends a signal to the corresponding processor 148 and 152, which performs uke actual tone generation. The tone is inserted in the T=alisrllit 1V41- lLipl-ong DAr stage hear removing the voice signal from the input to the DAC 176 and 178, and using the DAC 176 and 178 as a standard digital code-to-analog signal conversion block. Ike processor 148 and 152 writes samples to the DAC 176 and 178 at an 8 kHz rate. The tone level coin be calibrated along with the transmit leve adj,srmet, but can also be permanently set by a component value during card production. 14 F

he scalers 154 and 156 and the scalers i58 and lou in rig. sample both Tip voltage and Tip voltage minus Ring voltage and provide scaled down signals to the main processor 146 and 150, respectively. By monitoring the two signals, each processor 146 and 150 has the ability to determine when external events occur on the Tip and Ring interface For example, the following events can be detected: Tip Ground COG), Loop Current Feed (LCF) , Reverse Loop Current Feed (RLCF), and ringLng. The information 1 ' 1 ' 1 ' is used wltnn the processor state machine.

As indicated at 192 and 193 of Fig. 4, a loop closure (LC) optocoupler and ring ground (RG) relay are activated by processor 146 and 150. The processor sends Loop 0 Closure and Ring Ground signals to the device connected on the Tip and Ring interface during the handshaking sequence to establish a call.

Multiprocessing in the processors 146 and 150 of Fig. 4 is preferably achieved by using a round robin scheduler to run several tasks. An interrupt service routine handles the software time critical tasks. Upon power-up, the processor 146 and 150 does a self check of its PI sand ROIL The firmware of the processors 146 and 150 preferably administers one of three separate state machines in normal operation. The three states rraclrles consist of a Loop Start FX maclLur.e, a C-round Start FX machine, and a DPT machine. The Loop Start machine is a subset of the Ground Start machine. Both the Ground Start and Loop Slart machines send and receive stanclard D4 FX codes. The DPT machn e follows the standard D4 DPT codes.

The processor i46 and 10 uses one external hardware interrupt, which is connected to the TFET line from the ASIC 108. TFET and 1lFET (which is input tO a counter from the ASIC 108) provide the transmit rind receive frame timing, respective\.

2s One pulse occurs for each frame (125 us). The processor 146 and 150 is Interrupted on each TFET pulse, at which time the TFET counter (e.g., a counter in software) is updated, and the RFET counter (e.g., a hardware counter) is checked. The transmit and receive signaling bits can transition once every- super me, or 12 st.anda,d frames. It.e interrupt is processed within one frame in order tO maintain synchror i7ation Thus, the interrupt service routine occurs once every 125 us and is completed within 125 us.

The processor 146 Hind 150 examines option switches upon power-up, and then again once per half-second. The mode switch 170 and 172 is first read upon power-up to determine in which stare machine to operate. The processor 146 and 150 reexamines the state once per half-second to determine if the user has changed the setting. If a change is fourld, the processor resets itself, components are reinitialired, and processing in accordance with the new state riachiile coll-=iences.

The processor 148 and 152 examines the attenuation switches once per half second and programs the desired attenuation into the transmit and receive hardware circuitry. L ne remote aiignmen: state determined by the positiol of 'Lilt {flu he w-iLCh 1, u 0 and 172 is also exanuned each half-second, and, if remote alignment mode has been selected, the processor enters this state. During remote alignment mode the signaling to the far end is forced to the busy code to enable ser,Tice personnel to connect equipment and make voice measurements. In addition, if the tone option is selected, the processor 146 and 150 signals the corresponding processor 148 and 152 to enable a precision tone is generator and bypass the normal transmit and receive voice information. A change in the mode switch position or a timeout after 20 minutes cancels the remote alignment mode.

The RG relay and LC optocoupler are controlled by the processor i fib and Mu.

The state machine determines their activation. The RG relay, when activated, connects a ground on the ring lead and is used to signal the switch that a call is being initiated. ILe LC optocoupler causes a loop to be placed from Tip to Ring, which draws current from the switch, signaling the switch that a line is being used.

si,,r.a;TIg iS sent and received via the ASIC 108. The processor 146 and 150 samples the receive signaling once every twelve frames and sends transmit signaling once 2s e-very wel-v-e Antics. Sisal ': ,g is ser.t,/recei'e;n pi! former, that is, two bits each designated A and B. In order to produce the toggling bit state required for some LSAS codes, the processor 146 and 150 alternately sends a 1 and then a 0 on one (or both) of the bits as required for transmit signaling. Il.e A and B LED's are set to follow the received signaling.

The processor 146 and 150 receives information from the TG, I.CF, RLCF, and ringing detectors, some of which are detected from the A/D inputs, and uses the information to cin-ve the state rnachirle. The TO -- lfQaLioll is lll-lliplexed with Low, and indicates when the office end has battery and/or Tip Ground. RLCF is used for DPT to indicate when the office battery is reversed. Ringing indicates when an incoming call is available from the switch.

With regard to planning, the channel bank architecture of the present invention collects alarms detected by the double density RU 120 and passes them to the existing ACuJ 118 which, in turn, utilizes the existing D4 capacity to report audible and visual office alarms. In this manner, the existing ACU Alarm Cut Off (ACO) capability can silence alarms. The double density RU edge connector pins 54 and 27 are also connected to a set of dry relay contacts that are closed to provide an indication of the new DS1 alarm. The LID functionality built into the double density RU 120 is utilized to detect out of frame and yellow alarm states on the new DS 1 and illuminate corresponding red "AR" and yellow "AY" LEDs on the double density RU front panel. The new DS1 of the double density RU also responds to ESF payrioad loopbacks commands by 5;.inating a green front panel T R T ED and sending a tnunk processing indication to the double density channel units.

The double density I: iota or Me present invention prefei-ably responds to + processing in the same manner as standard D4 channel units. Double density C[J 100 and common unit components 102 of the present invention preferably do not activate the signals RNDIS, SP and SD and do not allow the condition corresponding to when RFA and REB are both high. Thus, a problem can arise when standard D4 channel units are used in a channel bank that has been upgraded using the double densitj'J 100 and common unit components 102 of the present invention. The signals RNDIS, SP, SD, RFA rind RFB are bussed to all channels for both shelves. If, for example, the DS1 to di-oup i31 fails, RNDIS can disable standard channel splits in, digroups 1 and B2 even though the DS1 to Group B2 is operational To such disablement, the double density RU i20 can selectively terminate RPCM, by sending all one's, and REAM, by send zero volts, while sending an idle si;llalirlg paelll to the ll charnel units.

Upon detection of carrier loss, the double density RU 120 can freeze and revert back to the previous A signaling bit, assuring that the A bit was valid, as well as set the b bit to all channel units. The double density RU 120 can also send all l's in the PCM l streams and zero volts on PAM Ir. accordance witch -he present invention, the double density RU 120 generates a MUX-OUT-OF-SYNCH signal when the T-1 fails. The double density CU loo is operable tc enter truant prccessing when the signal is detected on both channels. This eliminates trunk processing in the channel units and shifts that process to the double density RU 120.

The double dens ty channel bank architecture of the present invention does not support two original D4 maintenance capabilities, that is, (1) the ability to inject and send a digital milliwatt simultaneously to all 24 channels of a digroup; and (2) the ability to shift time slots by twelve positions dunr g a loophack. This capability was intended to lo simplify the alignment of fire voice cards (e.g., a tone injected into 2-wire port 1 can be monitored at 2-wire port 13, and so on). These capabilities, however, are seldom used because their use requires an entire digroup to be taken out of service.

The double density channel bank architecture of the present invention supports the standard Loop Terminal (L17) and Loop Line (LL) loopLacks for the new DS 1 via the double density TU 122 and the double density RU 120 front panel pin jacks. A pin ping is inserted in both double density TU and double density RU LT jacks to initiate a Line LoopLack These loopLacks are available for the original DS1 via standard ACU 118 front pane! controls. To inif-iate a new DS1 loopLack a first pin plug is inserted in either the double density RU 120 or the double density TU 122. A second pin plug is then inserted in the neighboring double density TU 122 or double density RU 120. Because of this need to insert two pin plugs to initiate a new DS1 loopLack, the double density RU 120 and double density TU 122 backplane interface design avoids damage, "latch up" or other problems during this process.

In normal operation, the double density TU 122 passes new DS1 TNEN 2s inAforArnAation to the double density RU 120 via the TPU DID control bus, and the Thy D2 control bus is held a-. "0". Dug a Red alarm, the double density RU 120 changes the D2 control bus to a " 1" to instruct the double density TU 122 to send TCLK over the D2 bus to the double densityIlJ 122 to indicate that a payload loopDack is in process. The double density TU 122 detects TCLK, removes INEN from the DID bus, and then accepts DS1 TPCM (the payload that the double density RU has placed on the DID bus. The double density RU also prevents false yellow alarms when the new DS 1 is in ESF mode, that is, it responds only to the ESF yellow alarm bit). Front panel proNTiQioAnng of the neNsT DS1 prevents the need to JisnJ?t e.is,ng senTice in Order to change or set up digroup configurations or perform diagnostic tests.

The double density channel bank architecture of the present invention addresses the RBOC need for higher density, plug-and-play, cost effective doubling of available RBOC facility floor space for DID, FX, voice messaging and digital PBX termination circuits. The double density channel bank architecture of the present invention operates Wits exist=." DSO wiring and supports existing D4 services via existing circuit packs, thereby preserving existing RBOC equipment investment and design changes to 0 accommodate less common services. Automatic BOG and loop length adaptation are integrated into a standard channel unit package (e.g., a D4 channel unit) to provide a fast, i simple, plug-and-play upgrade to existing CO D4 bays.

Although the present invention has been described with reference to a preferred embodiment thereof, it will be understood that the invention is not limited to the details is thereof. Various modifications and substitutions have been suggested in the foregoing description, and others will occur to those of ordinary skill in the art. All such substitutions are intended to be embraced within the scope of one invention as defined in the appended claims.

Claims (16)

1. C: [aims: 1. In a channel bank having a chassis comprising card slots for

   receiving charmer unite and common equipment components and operable Lo provide signals to duplex digital carriers, the common equipment comprising receive units, transmit splits, and a line interface unit, the channel bank having a backplane comprising a pulse code modulated bus and a pulse amplitude modulated bus, the channel units providing a single subscriber circuit for transmitting and receiving signals via a single duplex channel on one of said duplex digital carriers, an improved channel bank architecture to provide increased density of subscriber cots 1 said channel bank without changing said card i0 slots and said chassis, said improved channel bank architecture comprising: an increased density channel unit configured for insertion ire one of said card slots, said increased density channel unit being operable to provide a portion of a first second signal On said pulse code modulated bus of said channel bank and a portion of a second on said pulse amplitude modulated bus substantially simultaneously to support two of said subscriber circuits in the corresponding one of card slots.
2. 2. An mproved charmer bank architecture as claimed in claim 1, wherein said pulse amplitude modulated bus is operable to transport analog signals from analog cards in said chaurlel bank said increased density channel bank being operable to provide said portion of said second signal on said pulse amplitude modulated bus using selected tinting to avoid bus contention with said analog signals.
3. 3. An improved channel bank architecture as claimed in claim 1 or 2, further comprising at least one of an increased density receive unit arid increased density transmit unit provided in lieu of a corresponding one of said receive unit and said transmit mnit to connunicate with said increased density channel unit, at least one of said increased densityreceive unit and said increased densit,Ttransmit unit having a digital carrier connected thereto in addition to said duplex digital carriers supported by said channel bank ! 20
4. 4. An improved channel bank architecture as claimed in claim 3, wherein said duplex digital carriers each transport frames comprising a selected number of duplex channels, wherein said channel bank operates with at least one group A comprising said selected number of channels. said improved channel battle architecture comprising at least one of said increased density transmit unit and at least one of said increased density receive unit each having a digital canter connected thereto and being operable to support the division of said group A into divided groups A1 and A2, said divided groups A1 and A2 together providing at least twice said selected number of ckarmels per said frame, said increased density channel unit being operable to perform at least one of transmitting and lo receiving operations using at least two of said selected number of channels per frame.
5. 5. An improved channel bank architecture as claimed in claim 4, wherein said channel bank operates with a group B comprising another said selected Amber of channels, said improved channel bank architecture comprising a second said increased s density transmit unit and a second said increased density receive Unit each having a digital carrier connected thereto and being operable to support the division of said group B into Divided groups B1 and B2, said divided groups B1 and B2 together prov:dg at least twice said another selected number of channels per said frame, said divided groups A1, A2, B1 and B2 being substantially syncororiized per said frame for transport via corresponding ones of said duplex digital carriers and said digital carriers connected to said increased density receive unit, said increased density transmit unit, said second increased density receive unit and said second increased density transmit unit.
6. 6. An improved channel bank architecture as claimed in claim 4, wherein said increased density channel units use consecutive said channels of one of said divided groups A1 and A2 and said channel units use alternate ones calf said ckaAmneLs of one of said divided groups A1 and A2.
7. 7. An improved channel bank architecture as claimed in claim 1, wherein said bacllane cornpl-ises a control signal for ndicat'<lg which of a plurality of channel weir is inserted in at least one of said card slots thereof, said plurality of charnel UltS comprising a digital channel unit operable to use only said pulse code modulated bus, an analog channel unit, and said increased densitychannel unit.
8. 8. gin channel unit in a channel bank for transporting digital carriers, the charmer bank having a plurality of shelves for receiving respective channel units, the channel bank having a backplane comprising a pulse code modulated bus and a pulse amplitude modulated bus and being operable to transport backplane signals between the charnel Its and common equip. rnent in the channel bank, the channel unit comprising: a channel UL-llt peace connected to said back-plalle for receiving at least one of o said bacllane signals from and transmitting at least one of said backplane signals to said common equipment; a first circuit module configured for connection to a first telecommunications link and being connected to said channel unit interface; and a second circuit module configured for connection to a second teieConunications lLnk and being connected to said channel unit interface; whe.rer1 said first cat module comprises a first codec corrected to said channel on t irterface and a first digital/ana]. og converter connected between said first telecommunications link: and said first codec, said first digital/analog converter and said fast codec being ope -able to traspo t a flimsy call signal be.-v.reen said backplane and said first telecommunications linls: said second circuit module comprises a second codec connected to said channel unit interface and a second digital/analog converter connected between said second telecommunications link and said second codec, said second digital/analog converter and said second codec being operable to transport a second calf signal bet-w-eer1 said backplane and said second telecommunications link; and said first circuit module providing a portion of said first call signal on said pulse code modulated bus substantiallysimultaneouslywhile said second circuit module provides a portion of said second call signal on said pulse amplitude modulated bus.
9. 9. A channel learnt as cl2'Tned IT] claw 8, wherein said channel unit is iri a first card slot, said second circuit module being operable to process bacl;plane signals from said 1 22 common equipment to determine selected timing operations, said selected timing operations controlling the transport of said at least a portion of said second call signal on said pulse amplitude bus to avoid bus contention with analog signals provided thereon by one of said respective channel units a different one of said card slots.
10. 10. A channel unit as claimed in claim 9, wherein said second channel unit comprises switching devices controlled in accordance with said selected timing operations to provide said at least a portion of said second call signal from said second codec to said pulse amplitude modulated bus via said channel unit interface.
11. 11. A channel unit as claimed in claim 8, wherein said first communication link and said second communication link each comprise tip and ring wire pairs.
12. 12. A channel unit as claimed in claim 8, wherein said common equipment comprises a multiplexer for providing said first call signal and said second call signal on one of said pulse code rlAodu7^ated bus and said pulse a...plitude modulated bus and is operable to generate an indicator signal indicating when said multiplexer is out of svnchrormT.7tion5 and said common equipment further comprises a trunk processing unit, said channel unit commencing rink processing via said IrUnLA processing unit when said indicator signal is received by both said first circuit module and said second circuit module.
13. 13. A channel bank for transporting digital carriers comprising: a plurality of card slots for receiving one of a channel unit and common equipment, said common equipment being operable with a plurality of said chanrAel units and a backplane comprising a pulse code modulated bus and a pulse amplitude modulated bus and being operable to transport backplane signals between said channel units and said corr mon equip.neAnt, said pulse amplitude modulated bus and said pulse code modulated bus each comprising channels, said common equipment comprising at least one receive CAAAAt at least one trans.-n;^t U^=^it and at least one line interface tan t operable IO transport cat] signals for subscriber circuits supported by said channel traits on respective said channels on at least one of said pulse amplitude modulated bus and said pulse code modulated bus, said common equipment being configured to support a group X consisting of a selected number of said cnamlels per a selected n- us^llbei- of said card slots, said receive unit being connected to at least a first digital carrier and said backplane, said transmit unit being connected to at least a second digital carrier and said backplane, said line interface unit being connected to at least a duplex digital carrier and said bacl plane, said receive unit and said transmit unit being operable to process said call signals from at least one of said channel units inserted in one of said card slots units of group X, said one of said charnel UDlltS te'illg collfigUred to Support at least two different lo said subscriber circuits, said receive unit and said transmit unit transporting portions of said call signals from said at least one of said channel units on said pulse amplitude modulated bus and said pulse code modulated bus substantially simultaneously to allow division of said group X into divided group X1 and divided group X2 for support of at least twice said selected number of said channels when each of said card slots in said Is group X has one of said channel units, said divided group X1 being transported via said duplex digital carrier, said divided group X' being transported via said first digital carrier and said accord digital carrier.
14. 14. A channel bank as cla nned 1 clarion 13, -therein said portions of said call s';gr.^s from said at least one of said channel units and transported on said pulse amplitude modulated bus are provided thereon to avoid bus contention with analog signals provided on said pulse amplitude modulated bus by another one of said channel units, said another one of said channel units being inserted in an adjacent one of said card slots Nxilh respect to said at least one of said channel urn-es.
15. 15. A charmer unit as claimed in claim 13, Therein said one of said channel units comprises a first circuit module and a second circuit module to process respective ones of said two subscriber circuits, and said receive unit comprises a multiplexer for providing said call signals on one of said pulse code modulated bus and said pulse - amplitude modulated bus, and said change! band; further comprises a trunk processing unit COImeCted tO said receive unit and said transmit 'nit, said receive -at being operable to generate an indicator signal indicating when said multiplexer is out of synchronization, said at least one of said channel units commencing trtmk processing via said trunk processing asillg said indicator signal is received by both said first circuit module and said second circuit module. s
16. 16. A channel bank architecture substantially as described herein with reference tO Figs. 4-6 of the drawings. i