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GB2396759A - Clock noise reduction method and apparatus - Google Patents

Clock noise reduction method and apparatus Download PDF

Info

Publication number
GB2396759A
GB2396759A GB0325380A GB0325380A GB2396759A GB 2396759 A GB2396759 A GB 2396759A GB 0325380 A GB0325380 A GB 0325380A GB 0325380 A GB0325380 A GB 0325380A GB 2396759 A GB2396759 A GB 2396759A
Authority
GB
United Kingdom
Prior art keywords
clock signal
charge
circuit
noise reduction
noise
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
GB0325380A
Other versions
GB0325380D0 (en
Inventor
Brian W Amick
Claude R Gauthier
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sun Microsystems Inc
Original Assignee
Sun Microsystems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US09/846,757 external-priority patent/US6429722B1/en
Priority claimed from US09/847,495 external-priority patent/US6462604B1/en
Application filed by Sun Microsystems Inc filed Critical Sun Microsystems Inc
Publication of GB0325380D0 publication Critical patent/GB0325380D0/en
Publication of GB2396759A publication Critical patent/GB2396759A/en
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/125—Discriminating pulses
    • H03K5/1252—Suppression or limitation of noise or interference
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/16—Modifications for eliminating interference voltages or currents
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/10—Distribution of clock signals, e.g. skew
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/16—Modifications for eliminating interference voltages or currents
    • H03K17/161—Modifications for eliminating interference voltages or currents in field-effect transistor switches
    • H03K17/162—Modifications for eliminating interference voltages or currents in field-effect transistor switches without feedback from the output circuit to the control circuit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00346—Modifications for eliminating interference or parasitic voltages or currents
    • H03K19/00361—Modifications for eliminating interference or parasitic voltages or currents in field effect transistor circuits

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Nonlinear Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
  • Electronic Switches (AREA)

Abstract

A circuit for reducing the noise associated with a clock signal for a flip-flop based circuit has been developed. The circuit includes a charge control portion that stores charge at a pre-determined time of the clock cycle and a dump control portion that releases the stored current also at a pre-determined time of the clock cycle. The charge is released onto the power grid of the system served by the clock signal. A method of reducing the noise of a clock signal distribution system for a flip-flop based circuit has been developed. The method first inputs a synchronized clock signal into a noise reduction circuit. The noise reduction circuit then begins to store charge upon receipt of the signal. Finally, the noise reduction circuit dumps the charge onto the system power grid at an appropriate time in conjunction with the clock signal.

Description

GB 2396759 A continuation (74) Agent and/or Address for Service: D Young &
Co 21 New Fetter Lane, LONDON, EC4A 1 DA, United Kingdom
GB0325380A 2001-05-01 2002-04-30 Clock noise reduction method and apparatus Withdrawn GB2396759A (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/846,757 US6429722B1 (en) 2001-05-01 2001-05-01 Clock noise reduction method
US09/847,495 US6462604B1 (en) 2001-05-02 2001-05-02 Clock noise reduction apparatus
PCT/US2002/013523 WO2002091577A2 (en) 2001-05-01 2002-04-30 Clock noise reduction method and apparatus

Publications (2)

Publication Number Publication Date
GB0325380D0 GB0325380D0 (en) 2003-12-03
GB2396759A true GB2396759A (en) 2004-06-30

Family

ID=27126667

Family Applications (1)

Application Number Title Priority Date Filing Date
GB0325380A Withdrawn GB2396759A (en) 2001-05-01 2002-04-30 Clock noise reduction method and apparatus

Country Status (4)

Country Link
KR (1) KR20040007520A (en)
AU (1) AU2002303544A1 (en)
GB (1) GB2396759A (en)
WO (1) WO2002091577A2 (en)

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4752703A (en) * 1987-04-23 1988-06-21 Industrial Technology Research Institute Current source polarity switching circuit
US5198699A (en) * 1988-09-09 1993-03-30 Texas Instruments Incorporated Capacitor-driven signal transmission circuit
JP3608361B2 (en) * 1997-12-26 2005-01-12 株式会社日立製作所 Low noise semiconductor integrated circuit device
JP3878320B2 (en) * 1998-03-25 2007-02-07 株式会社ルネサステクノロジ Output circuit, pulse width modulation circuit, and semiconductor integrated circuit
JP2997241B1 (en) * 1998-07-17 2000-01-11 株式会社半導体理工学研究センター Low switching noise logic circuit
US6388503B1 (en) * 2000-09-28 2002-05-14 Intel Corporation Output buffer with charge-pumped noise cancellation

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
Not yet advised *

Also Published As

Publication number Publication date
WO2002091577A3 (en) 2004-04-08
GB0325380D0 (en) 2003-12-03
AU2002303544A1 (en) 2002-11-18
WO2002091577A8 (en) 2003-04-10
KR20040007520A (en) 2004-01-24
WO2002091577A2 (en) 2002-11-14

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Legal Events

Date Code Title Description
WAP Application withdrawn, taken to be withdrawn or refused ** after publication under section 16(1)