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GB2381679A - Method and apparatus for a digital clock multiplication circuit - Google Patents

Method and apparatus for a digital clock multiplication circuit

Info

Publication number
GB2381679A
GB2381679A GB0302538A GB0302538A GB2381679A GB 2381679 A GB2381679 A GB 2381679A GB 0302538 A GB0302538 A GB 0302538A GB 0302538 A GB0302538 A GB 0302538A GB 2381679 A GB2381679 A GB 2381679A
Authority
GB
United Kingdom
Prior art keywords
circuits
clock multiplication
multiplication circuit
digital clock
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
GB0302538A
Other versions
GB0302538D0 (en
GB2381679B (en
Inventor
Kin Mun Lye
Jurianto Joe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
National University of Singapore
Original Assignee
National University of Singapore
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by National University of Singapore filed Critical National University of Singapore
Publication of GB0302538D0 publication Critical patent/GB0302538D0/en
Publication of GB2381679A publication Critical patent/GB2381679A/en
Application granted granted Critical
Publication of GB2381679B publication Critical patent/GB2381679B/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/60—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers
    • G06F7/68—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers using pulse rate multipliers or dividers pulse rate multipliers or dividers per se
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Pure & Applied Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Mathematical Physics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Manipulation Of Pulses (AREA)
  • Oscillators With Electromechanical Resonators (AREA)
  • Inductance-Capacitance Distribution Constants And Capacitance-Resistance Oscillators (AREA)

Abstract

A clock multiplication technique includes driving two oscillatory circuits by an input signal. One of the circuits has an inverted input. The oscillatory circuits are characterized by a transfer function having an unstable region bounded by two stable regions. Oscillations produced during operation of each of the circuits in the unstable regions are combined to produce a signal whose frequency is a multiple of the input frequency.
GB0302538A 2000-08-04 2000-08-04 Method and apparatus for a digital clock multiplication circuit Expired - Fee Related GB2381679B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/IB2000/001164 WO2002013385A1 (en) 2000-08-04 2000-08-04 Method and apparatus for a digital clock multiplication circuit

Publications (3)

Publication Number Publication Date
GB0302538D0 GB0302538D0 (en) 2003-03-12
GB2381679A true GB2381679A (en) 2003-05-07
GB2381679B GB2381679B (en) 2004-07-28

Family

ID=11003964

Family Applications (1)

Application Number Title Priority Date Filing Date
GB0302538A Expired - Fee Related GB2381679B (en) 2000-08-04 2000-08-04 Method and apparatus for a digital clock multiplication circuit

Country Status (7)

Country Link
JP (1) JP2004506370A (en)
KR (1) KR20030028557A (en)
CN (1) CN1454410A (en)
AU (1) AU2000264633A1 (en)
CA (1) CA2417021A1 (en)
GB (1) GB2381679B (en)
WO (1) WO2002013385A1 (en)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6630897B2 (en) 1999-10-28 2003-10-07 Cellonics Incorporated Pte Ltd Method and apparatus for signal detection in ultra wide-band communications
US6452530B2 (en) * 1999-10-28 2002-09-17 The National University Of Singapore Method and apparatus for a pulse decoding communication system using multiple receivers
US20010031023A1 (en) * 1999-10-28 2001-10-18 Kin Mun Lye Method and apparatus for generating pulses from phase shift keying analog waveforms
US6907090B2 (en) 2001-03-13 2005-06-14 The National University Of Singapore Method and apparatus to recover data from pulses
US6498572B1 (en) * 2001-06-18 2002-12-24 The National University Of Singapore Method and apparatus for delta modulator and sigma delta modulator
US7054360B2 (en) 2001-11-05 2006-05-30 Cellonics Incorporated Pte, Ltd. Method and apparatus for generating pulse width modulated waveforms
US20030112862A1 (en) * 2001-12-13 2003-06-19 The National University Of Singapore Method and apparatus to generate ON-OFF keying signals suitable for communications
US6724269B2 (en) 2002-06-21 2004-04-20 Cellonics Incorporated Pte., Ltd. PSK transmitter and correlator receiver for UWB communications system
CN103929153B (en) * 2013-01-11 2016-12-28 北大方正集团有限公司 A kind of frequency doubling treatment method and device
CN115801822B (en) * 2022-10-12 2025-07-22 河南油田工程科技股份有限公司 Oil gas production cloud platform data acquisition terminal

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5107264A (en) * 1990-09-26 1992-04-21 International Business Machines Corporation Digital frequency multiplication and data serialization circuits
JPH1174766A (en) * 1997-08-27 1999-03-16 Sony Corp Clock pulse multiplier

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5107264A (en) * 1990-09-26 1992-04-21 International Business Machines Corporation Digital frequency multiplication and data serialization circuits
JPH1174766A (en) * 1997-08-27 1999-03-16 Sony Corp Clock pulse multiplier

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
GaAs IC Symp. Portland, Oreg., 13-16 Oct. 1987, pp 61-64 *

Also Published As

Publication number Publication date
CN1454410A (en) 2003-11-05
GB0302538D0 (en) 2003-03-12
KR20030028557A (en) 2003-04-08
GB2381679B (en) 2004-07-28
AU2000264633A1 (en) 2002-02-18
JP2004506370A (en) 2004-02-26
WO2002013385A1 (en) 2002-02-14
CA2417021A1 (en) 2002-02-14

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Legal Events

Date Code Title Description
PCNP Patent ceased through non-payment of renewal fee

Effective date: 20050804