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GB2374697A - Data storage system having point-to-point configuration - Google Patents

Data storage system having point-to-point configuration Download PDF

Info

Publication number
GB2374697A
GB2374697A GB0207148A GB0207148A GB2374697A GB 2374697 A GB2374697 A GB 2374697A GB 0207148 A GB0207148 A GB 0207148A GB 0207148 A GB0207148 A GB 0207148A GB 2374697 A GB2374697 A GB 2374697A
Authority
GB
United Kingdom
Prior art keywords
directors
data transfer
point
transfer section
data storage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
GB0207148A
Other versions
GB0207148D0 (en
Inventor
David L Black
Stephen D Macarthur
Richard Wheeler
Paul C Wilson
Mark Zani
Farouk Khan
Christopher S Maclellan
John K Walton
Kendell A Chilton
William Tuccio
Robert Thibault
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
EMC Corp
Original Assignee
EMC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US09/606,730 external-priority patent/US7007194B1/en
Priority claimed from US09/606,734 external-priority patent/US7073020B1/en
Application filed by EMC Corp filed Critical EMC Corp
Publication of GB0207148D0 publication Critical patent/GB0207148D0/en
Publication of GB2374697A publication Critical patent/GB2374697A/en
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/382—Information transfer, e.g. on bus using universal interface adapter
    • G06F13/387—Information transfer, e.g. on bus using universal interface adapter for adaptation of different data processing systems to different peripheral devices, e.g. protocol converters for incompatible systems, open system

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Information Retrieval, Db Structures And Fs Structures Therefor (AREA)
  • Information Transfer Between Computers (AREA)

Abstract

A system interface (160) includes a plurality of first directors (180), a plurality of second directors (200), a data transfer section (240) and a message network (260) which operates independently of the data transfer section. The data transfer section includes a cache memory (220) coupled to the plurality of first and second directors as is the message network. The first and second directors control data transfer between the first directors and the second directors in response to messages passing between the first directors and the second directors through the messaging network to facilitate data transfer between first directors and the second directors. The data passes through the cache memory in the data transfer section. The system interface operates to transfer data between a host computer/server (120) and a bank of disk drives (140).

Description

(57} A system interface {160) includes a plurality of first directors
{180), a plurality of second directors {200), a data transfer section (240) and a message network (260) which operates independently of the data transfer section. The data transfer section includes a cache memory {220) coupled to the plurality of first and second directors as is the message network. The first and second directors control data transfer between the first directors and the second directors in response to messages passing between the first directors and the second directors through the messaging network to facilitate data transfer between first directors and the second directors. The data passes through the cache memory in the data transfer section. The system interface operates to transfer data between a host computer/server (120} and a bank of disk drives (140).
GB0207148A 2000-06-29 2001-06-27 Data storage system having point-to-point configuration Withdrawn GB2374697A (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/606,730 US7007194B1 (en) 2000-06-29 2000-06-29 Data storage system having point-to-point configuration
US09/606,734 US7073020B1 (en) 1999-01-04 2000-06-29 Method for message transfer in computer storage system
PCT/US2001/041175 WO2002003387A2 (en) 2000-06-29 2001-06-27 Data storage system having point-to-point configuration

Publications (2)

Publication Number Publication Date
GB0207148D0 GB0207148D0 (en) 2002-05-08
GB2374697A true GB2374697A (en) 2002-10-23

Family

ID=27085321

Family Applications (1)

Application Number Title Priority Date Filing Date
GB0207148A Withdrawn GB2374697A (en) 2000-06-29 2001-06-27 Data storage system having point-to-point configuration

Country Status (3)

Country Link
JP (1) JP4885406B2 (en)
GB (1) GB2374697A (en)
WO (1) WO2002003387A2 (en)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7467238B2 (en) 2004-02-10 2008-12-16 Hitachi, Ltd. Disk controller and storage system
JP4405277B2 (en) 2004-02-16 2010-01-27 株式会社日立製作所 Disk controller
US20050216625A1 (en) * 2004-03-09 2005-09-29 Smith Zachary S Suppressing production of bus transactions by a virtual-bus interface
CN103398719B (en) 2004-03-23 2017-04-12 咕果公司 Digital Mapping System
WO2005094466A2 (en) * 2004-03-23 2005-10-13 Google Inc. Generating and serving tiles in a digital mapping system
US20060236032A1 (en) * 2005-04-13 2006-10-19 Campbell Brian K Data storage system having memory controller with embedded CPU
US8010407B1 (en) 2006-11-14 2011-08-30 Google Inc. Business finder for locating local businesses to contact

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4484262A (en) * 1979-01-09 1984-11-20 Sullivan Herbert W Shared memory computer method and apparatus
US4800483A (en) * 1982-12-01 1989-01-24 Hitachi, Ltd. Method and system for concurrent data transfer disk cache system
US5335327A (en) * 1988-10-12 1994-08-02 Hitachi, Ltd. External memory control techniques with multiprocessors improving the throughput of data between a hierarchically upper processing unit and an external memory with efficient use of a cache memory
US5689728A (en) * 1988-08-30 1997-11-18 Hitachi, Ltd. Controller of paths for data transfer in system having external memory device
US6134624A (en) * 1998-06-08 2000-10-17 Storage Technology Corporation High bandwidth cache system
GB2366425A (en) * 2000-03-31 2002-03-06 Emc Corp Data transfer via a cache under control of an independent message network

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3264465B2 (en) * 1993-06-30 2002-03-11 株式会社日立製作所 Storage system
JP3195489B2 (en) * 1994-03-03 2001-08-06 株式会社日立製作所 External storage control device and bus switching control method
CA2153445C (en) * 1994-09-08 2002-05-21 Ashok Raj Saxena Video optimized media streamer user interface
JPH10333836A (en) * 1997-05-29 1998-12-18 Hitachi Ltd Disk array controller
JPH11177589A (en) * 1997-12-12 1999-07-02 Canon Inc Data transfer device, data processing method of data transfer device, and storage medium storing computer readable program
JP3657428B2 (en) * 1998-04-27 2005-06-08 株式会社日立製作所 Storage controller
US6061274A (en) * 1999-01-04 2000-05-09 Emc Corporation Methods and apparatus for message transfer in computer storage system

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4484262A (en) * 1979-01-09 1984-11-20 Sullivan Herbert W Shared memory computer method and apparatus
US4800483A (en) * 1982-12-01 1989-01-24 Hitachi, Ltd. Method and system for concurrent data transfer disk cache system
US5689728A (en) * 1988-08-30 1997-11-18 Hitachi, Ltd. Controller of paths for data transfer in system having external memory device
US5335327A (en) * 1988-10-12 1994-08-02 Hitachi, Ltd. External memory control techniques with multiprocessors improving the throughput of data between a hierarchically upper processing unit and an external memory with efficient use of a cache memory
US6134624A (en) * 1998-06-08 2000-10-17 Storage Technology Corporation High bandwidth cache system
GB2366425A (en) * 2000-03-31 2002-03-06 Emc Corp Data transfer via a cache under control of an independent message network

Also Published As

Publication number Publication date
JP4885406B2 (en) 2012-02-29
WO2002003387A2 (en) 2002-01-10
GB0207148D0 (en) 2002-05-08
JP2004502263A (en) 2004-01-22
WO2002003387A3 (en) 2003-06-05

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Legal Events

Date Code Title Description
WAP Application withdrawn, taken to be withdrawn or refused ** after publication under section 16(1)