GB2371138A - Field progammable gate array hard disk system - Google Patents
Field progammable gate array hard disk system Download PDFInfo
- Publication number
- GB2371138A GB2371138A GB0207720A GB0207720A GB2371138A GB 2371138 A GB2371138 A GB 2371138A GB 0207720 A GB0207720 A GB 0207720A GB 0207720 A GB0207720 A GB 0207720A GB 2371138 A GB2371138 A GB 2371138A
- Authority
- GB
- United Kingdom
- Prior art keywords
- fpga
- hdd
- data
- hard disk
- gate array
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/0604—Improving or facilitating administration, e.g. storage management
- G06F3/0607—Improving or facilitating administration, e.g. storage management by facilitating the process of upgrading existing storage systems, e.g. for improving compatibility between host and storage device
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7867—Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
- G06F3/0661—Format or protocol conversion arrangements
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0673—Single storage device
- G06F3/0674—Disk device
- G06F3/0676—Magnetic disk device
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Human Computer Interaction (AREA)
- Computer Hardware Design (AREA)
- Signal Processing For Digital Recording And Reproducing (AREA)
Abstract
An FPGA/HD assembly is self-contained by integrating with the FPGA with the HDD assembly, with the HDD storing the in-circuit programming for the FPGA, and modifying the FPGA to cooperate with any selected interface under the control of the embedded controller in the HDD. The in-circuit programming data is stored directly on a selected partition of the HDD, leaving as much space as needed for any other data traditionally stored on the HDD. The controller would locate the specific in-circuit data and locate the appropriate soft core into the FPGA upon receiving a command identifying the bus which is to be interfaced within any selected operation.
Description
AUK Patent Application 'g,GB,,,2 371 138 HA (43) Date of Printing by UK
Office 17.07.2002 (21) Application No 0207720.4 (51) INTCL7 HUSK 19/177, G06F 13/00
(22) Date of Filing 20.09.2000 (52) UK CL (Edition T) (30) Priority Data G4H HU H13D (31) 60154881 (32) 20.09.1999 (33) US
(56) Documents Cited by ISA (86) International Application Data US 5941813 A US 5619728 A PCT/US00/25846 En 20.09.2000 US 5600845 A (87) International Publication Data (58) Field of Search by ISA
WO01/22425 En 29.03.2001 INT CL7 G06F, G11C, HOlJ (71) Applicant(s) Seagate Technology LLC llucorporated in USA - Delaware) 920 Disc Drive, Scotts Valley, CA 95066, United States of America (72) Inventor(s) William S Hers (74) Agent and/or Address for Service Miller Sturt Kenyon 9 John Street, LONDON, WC1N 2ES, United Kingdom (54) Abstract Ttie Field progammable gate array hard disk system
(57) An FPGA/HD assembly is self-contained by integrating with the FPGA with the HDD assembly, with the HDD storing the in-circuit programming for the FPGA, and modifying the FPGA to cooperate with any selected interface under the control of the embedded controller in the HDD. The in- circuit programming data is stored directly on a selected partition of the HDD, leaving as much space as needed for any other data traditionally stored on the HDD. The controller would locate the specific in-circuit data and locate the appropriate soft core into the FPGA upon receiving a command identifying the bus which is to be interfaced within any selected operation. FPGAD /d , Syntax Dala: I / 1394 2 etertace. VEGA USB 0 _ _ D ua vda P' e t L VOS-4no..
T -!. / l. m .,,,. rPGA À o . CD This international application has entered the national phase early.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US15488199P | 1999-09-20 | 1999-09-20 | |
| PCT/US2000/025846 WO2001022425A1 (en) | 1999-09-20 | 2000-09-20 | Field programmable gate array hard disk system |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| GB0207720D0 GB0207720D0 (en) | 2002-05-15 |
| GB2371138A true GB2371138A (en) | 2002-07-17 |
| GB2371138B GB2371138B (en) | 2003-12-10 |
Family
ID=22553211
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB0207720A Expired - Fee Related GB2371138B (en) | 1999-09-20 | 2000-09-20 | Field progammable gate array hard disk system |
Country Status (7)
| Country | Link |
|---|---|
| JP (1) | JP2003510705A (en) |
| KR (1) | KR20020035606A (en) |
| CN (1) | CN1391695A (en) |
| AU (1) | AU7597600A (en) |
| DE (1) | DE10085014T1 (en) |
| GB (1) | GB2371138B (en) |
| WO (1) | WO2001022425A1 (en) |
Families Citing this family (34)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6711558B1 (en) | 2000-04-07 | 2004-03-23 | Washington University | Associative database scanning and information retrieval |
| US7139743B2 (en) | 2000-04-07 | 2006-11-21 | Washington University | Associative database scanning and information retrieval using FPGA devices |
| US7716330B2 (en) | 2001-10-19 | 2010-05-11 | Global Velocity, Inc. | System and method for controlling transmission of data packets over an information network |
| US7711844B2 (en) | 2002-08-15 | 2010-05-04 | Washington University Of St. Louis | TCP-splitter: reliable packet monitoring methods and apparatus for high speed networks |
| AU2004290281A1 (en) * | 2003-05-23 | 2005-05-26 | Washington University | Intelligent data storage and processing using FPGA devices |
| US10572824B2 (en) | 2003-05-23 | 2020-02-25 | Ip Reservoir, Llc | System and method for low latency multi-functional pipeline with correlation logic and selectively activated/deactivated pipelined data processing engines |
| KR100954010B1 (en) * | 2003-11-06 | 2010-04-20 | 엘지노텔 주식회사 | Programmable Multimedia Device in Data Processing System |
| CN1333349C (en) * | 2003-12-23 | 2007-08-22 | 华为技术有限公司 | System and method for loading on-site programmable gate array |
| US7602785B2 (en) | 2004-02-09 | 2009-10-13 | Washington University | Method and system for performing longest prefix matching for network address lookup using bloom filters |
| EP1859378A2 (en) | 2005-03-03 | 2007-11-28 | Washington University | Method and apparatus for performing biosequence similarity searching |
| US7702629B2 (en) | 2005-12-02 | 2010-04-20 | Exegy Incorporated | Method and device for high performance regular expression pattern matching |
| US7636703B2 (en) | 2006-05-02 | 2009-12-22 | Exegy Incorporated | Method and apparatus for approximate pattern matching |
| CN100433697C (en) * | 2006-06-01 | 2008-11-12 | 东南大学 | Multi-channel high-speed data processor and processing method |
| US7921046B2 (en) | 2006-06-19 | 2011-04-05 | Exegy Incorporated | High speed processing of financial information using FPGA devices |
| US7660793B2 (en) | 2006-11-13 | 2010-02-09 | Exegy Incorporated | Method and system for high performance integration, processing and searching of structured and unstructured data using coprocessors |
| US10229453B2 (en) | 2008-01-11 | 2019-03-12 | Ip Reservoir, Llc | Method and system for low latency basket calculation |
| US8374986B2 (en) | 2008-05-15 | 2013-02-12 | Exegy Incorporated | Method and system for accelerated stream processing |
| CA2744746C (en) | 2008-12-15 | 2019-12-24 | Exegy Incorporated | Method and apparatus for high-speed processing of financial market depth data |
| CN101673101B (en) * | 2009-09-27 | 2011-06-22 | 电子科技大学 | A FPGA reconfigurable device with online programming |
| CN101808027B (en) * | 2010-03-31 | 2011-11-23 | 哈尔滨工业大学 | Data receiving, storing and forwarding device suitable for various ports |
| JP6045505B2 (en) | 2010-12-09 | 2016-12-14 | アイピー レザボア, エルエルシー.IP Reservoir, LLC. | Method and apparatus for managing orders in a financial market |
| CN102685609A (en) * | 2011-09-28 | 2012-09-19 | 朱良学 | Multi-protocol soft-core digital interphone |
| US10121196B2 (en) | 2012-03-27 | 2018-11-06 | Ip Reservoir, Llc | Offload processing of data packets containing financial market data |
| US10650452B2 (en) | 2012-03-27 | 2020-05-12 | Ip Reservoir, Llc | Offload processing of data packets |
| US9990393B2 (en) | 2012-03-27 | 2018-06-05 | Ip Reservoir, Llc | Intelligent feed switch |
| US11436672B2 (en) | 2012-03-27 | 2022-09-06 | Exegy Incorporated | Intelligent switch for processing financial market data |
| US9633097B2 (en) | 2012-10-23 | 2017-04-25 | Ip Reservoir, Llc | Method and apparatus for record pivoting to accelerate processing of data fields |
| EP2912579B1 (en) | 2012-10-23 | 2020-08-19 | IP Reservoir, LLC | Method and apparatus for accelerated format translation of data in a delimited data format |
| US9633093B2 (en) | 2012-10-23 | 2017-04-25 | Ip Reservoir, Llc | Method and apparatus for accelerated format translation of data in a delimited data format |
| GB2541577A (en) | 2014-04-23 | 2017-02-22 | Ip Reservoir Llc | Method and apparatus for accelerated data translation |
| US10942943B2 (en) | 2015-10-29 | 2021-03-09 | Ip Reservoir, Llc | Dynamic field data translation to support high performance stream data processing |
| EP3560135A4 (en) | 2016-12-22 | 2020-08-05 | IP Reservoir, LLC | LEARNING PIPING FOR HARDWARE ACCELERATED MACHINERY |
| DE102018123494A1 (en) | 2017-11-17 | 2019-05-23 | Samsung Electronics Co., Ltd. | MEMORY DEVICE DESIGNED TO UPGRADE A FIELD-PROGRAMMABLE GATE ARRAY, AND OPERATING METHOD THEREFOR |
| CN113312098B (en) * | 2020-04-01 | 2022-08-12 | 阿里巴巴集团控股有限公司 | Program loading method, device, system and storage medium |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5600845A (en) * | 1994-07-27 | 1997-02-04 | Metalithic Systems Incorporated | Integrated circuit computing device comprising a dynamically configurable gate array having a microprocessor and reconfigurable instruction execution means and method therefor |
| US5619728A (en) * | 1994-10-20 | 1997-04-08 | Dell Usa, L.P. | Decoupled DMA transfer list storage technique for a peripheral resource controller |
| US5944813A (en) * | 1993-08-03 | 1999-08-31 | Xilinx, Inc. | FPGA input output buffer with registered tristate enable |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0718751A3 (en) * | 1994-12-23 | 1997-02-12 | Ibm | Electronic circuit apparatus employing small disk drive with reconfigurable interface |
-
2000
- 2000-09-20 DE DE10085014T patent/DE10085014T1/en not_active Withdrawn
- 2000-09-20 KR KR1020027003625A patent/KR20020035606A/en not_active Abandoned
- 2000-09-20 GB GB0207720A patent/GB2371138B/en not_active Expired - Fee Related
- 2000-09-20 CN CN 00815913 patent/CN1391695A/en active Pending
- 2000-09-20 JP JP2001525707A patent/JP2003510705A/en active Pending
- 2000-09-20 AU AU75976/00A patent/AU7597600A/en not_active Abandoned
- 2000-09-20 WO PCT/US2000/025846 patent/WO2001022425A1/en not_active Ceased
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5944813A (en) * | 1993-08-03 | 1999-08-31 | Xilinx, Inc. | FPGA input output buffer with registered tristate enable |
| US5600845A (en) * | 1994-07-27 | 1997-02-04 | Metalithic Systems Incorporated | Integrated circuit computing device comprising a dynamically configurable gate array having a microprocessor and reconfigurable instruction execution means and method therefor |
| US5619728A (en) * | 1994-10-20 | 1997-04-08 | Dell Usa, L.P. | Decoupled DMA transfer list storage technique for a peripheral resource controller |
Also Published As
| Publication number | Publication date |
|---|---|
| AU7597600A (en) | 2001-04-24 |
| CN1391695A (en) | 2003-01-15 |
| WO2001022425A1 (en) | 2001-03-29 |
| JP2003510705A (en) | 2003-03-18 |
| WO2001022425A9 (en) | 2002-11-21 |
| GB0207720D0 (en) | 2002-05-15 |
| DE10085014T1 (en) | 2003-04-30 |
| KR20020035606A (en) | 2002-05-11 |
| GB2371138B (en) | 2003-12-10 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PCNP | Patent ceased through non-payment of renewal fee |
Effective date: 20080920 |