GB2361852A - Turbo coded trellis code modulation - Google Patents
Turbo coded trellis code modulation Download PDFInfo
- Publication number
- GB2361852A GB2361852A GB0010330A GB0010330A GB2361852A GB 2361852 A GB2361852 A GB 2361852A GB 0010330 A GB0010330 A GB 0010330A GB 0010330 A GB0010330 A GB 0010330A GB 2361852 A GB2361852 A GB 2361852A
- Authority
- GB
- United Kingdom
- Prior art keywords
- encoder
- prob
- iteration
- turbo
- values
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
- H03M13/39—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes
- H03M13/3905—Maximum a posteriori probability [MAP] decoding or approximations thereof based on trellis or lattice decoding, e.g. forward-backward algorithm, log-MAP decoding, max-log-MAP decoding
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/23—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using convolutional codes, e.g. unit memory codes
- H03M13/235—Encoding of convolutional codes, e.g. methods or arrangements for parallel or block-wise encoding
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/25—Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM]
- H03M13/258—Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM] with turbo codes, e.g. Turbo Trellis Coded Modulation [TTCM]
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
- H03M13/2957—Turbo codes and decoding
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
- H03M13/39—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes
- H03M13/3961—Arrangements of methods for branch or transition metric calculation
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
- H03M13/39—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes
- H03M13/3988—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes for rate k/n convolutional codes, with k>1, obtained by convolutional encoders with k inputs and n outputs
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/65—Purpose and implementation aspects
- H03M13/6561—Parallelized implementations
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/65—Purpose and implementation aspects
- H03M13/6577—Representation or format of variables, register sizes or word-lengths and quantization
- H03M13/6583—Normalization other than scaling, e.g. by subtraction
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0045—Arrangements at the receiver end
- H04L1/0052—Realisations of complexity reduction techniques, e.g. pipelining or use of look-up tables
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0045—Arrangements at the receiver end
- H04L1/0055—MAP-decoding
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0056—Systems characterized by the type of code used
- H04L1/0064—Concatenated codes
- H04L1/0066—Parallel concatenated codes
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0045—Arrangements at the receiver end
- H04L1/0047—Decoding adapted to other signal detection operation
- H04L1/005—Iterative decoding, including iteration between signal detection and decoding operation
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0056—Systems characterized by the type of code used
- H04L1/0059—Convolutional codes
- H04L1/006—Trellis-coded modulation
Landscapes
- Physics & Mathematics (AREA)
- Probability & Statistics with Applications (AREA)
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Error Detection And Correction (AREA)
Abstract
An encoder for turbo coded trellis code modulation comprises an encoder data block for storing incoming data, and at least two recursive systematic convolutional encoders, said convolutional encoders being connected to receive data in parallel from said encoder data block. The decoder also employs a parallel implementation.
Description
2361852 Parallel Turbo Trellis-Coded Modulation
Field of Invention
This invention relates to the field of digital communications, and in particular to an encoder and decoder for use in the implementation of a turbo trellis-coded modulation 5 scheme.
Background of the Invention
Turbo code has attracted a lot of interest due to its larger coding gain. See for example, "Application of Turbo Codes for Discrete Multi-Tone Modulation", Hamid R. Sadjapour, AT&T Shannon Labs., 1996. Turbo code consists of two or more convolutional constituent codes separated by an interleaver acting on the input sequence of the first encoder. In a digital subscriber loop (DSL) system, Turbo code can be used to replace trellis code to get better Bit-Effor Rate (BER) performance. However, when the constellation size increases, the coding gain advantage of turbo code starts to reduce. This is because the redundant bits makes the constellation size even larger.
Our co-pending patent application of even date describes how turbo code can be used to code only the least significant bit (LSB) in the constellation and thereby achieve better performance than currently used trellis-coded modulation, such as We! code. The achievable data rate is only a couple of dB away from Shannon capacity.
An object the invention is to provide a fast implementation of an encoder and decoder for turbo trellis coded modulation.
Summary of the Invention
According to the present invention there is provided encoding apparatus generating a turbo trellis code modulation signal, comprising an encoder data block for storing incoming data, and at least two recursive systematic convolutional encoders, said convolutional encoders being connected to receive data in paraflel from said encoder data block.
The described parallel implementation structure reduces the implementation cycle for both encoder and decoder. Also, the memory (RAM) requirement for the turbo decoder can also be saved by 113 in the case of a three bit parallel implementation.
The invention also provides decoding apparatus for a turbo coded trellis code modulation signal, comprising a pair of decoders performing forward and backward iteration on an input signal, and interleaver and de-interleaver, each decoder taking at n soft bit inputs for each turbo decoder iteration, where n is an integer greater than 1.
Brief Description of the Drawings
The invention will now be described in more detail, by way of example only, with reference to the accompanying drawings, in which:- Figure 1 is a block diagram of an encoder for turbo trellis code modulation; Figure 2 is a block diagram of a parallel implementation of the encoder, Figure 3 shows a typical RSC encoder; Figure 3b shows a parallel RSC encoder in accordance with the principles of the invention., Figure 4 is a block diagram of a parallel turbo decoder; Figure 5 illustrates the operation of the decoder; Figure 6 illustrates the implementation of the forward iteration; Figure 7 shows a detail of Figure 6; and Figure 8 illustrates the implementation of backward iteration.
Detailed Description of the Invention
Parallel Encoder The general constellation encoder structure for a turbo trellis-coded modulation scheme is shown in Fig. 1 for cases x> 1 and y> 1. The input binary word u = (u,,, u,,-,,..., ul) determines two binary words v = (vz,-y,, vo) and w = (wy-1,., wo) (where z' = x+y- 1), which are used to look up two constellation points in an encoder table.
Encoder data block 10 receives a portion of the data from an input bit stream and stores it in memory. The lowest order bits are read out of encoder data block and passed to recursive systematic convolutional encoders RSC1 and RSC2.
The turbo encoder formed by block 20 is a systematic encoder with coding rate 314 punctured at rate 112. The turbo encoder consists of two recursive systematic convolutional encoders, RSC I and RSC2. The RSC I takes sequential data from the encoder data block and RSC2 takes interleaved data from the same data block. In this structure, three implementation cycles are required to get a single constellation point, which is mainly due to the implementation requirement of the turbo encoder.
To speed up the process, a parallel encoder structure is presented in Fig. 2. The difference over Figure 1 is that both RSC 1 and RSC2 take three input data shnultaneously and create one error check bit in a single implementation cycle.
A comparison between a normal RSC encoder and a parallel RSC encoder is shown in Fig. 3, where Fig.3 (a) is a normal 8 state RSC encoder and Fig. 3(b) shows a parallel implementation. The parallel encoder takes only one implementation cycle for every three input bits. Although Fig.3 (b) shows the same encoder as Fig.3 (a), it is not necessary that the parallel encoder be derived from a normal RSC encoder.
Parallel Turbo Decoder The decoding procedure for turbo trellis-coded modulation consists of following steps:
1. Soft decode for the least significant bit (LSB); 2. Hard decoder for the most significant bits (MSB).
3. Decode the MB using turbo decoder algorithm 4. Determine all data bits.
In order to decode the LSB (third step), the parallel turbo decoder takes three soft-bit inputs for each forward (a) and backward (0) iteration. In this way, only 113 cycles are used for each turbo decoder iteration and the memory requirements for storing (x and values are also reduced by a factor of three.
The parallel turbo decoder is shown in Fig.4. It consists of two decoders 40, 42, and an interleaver 41, and deinterleaver 43.
Fig.5 shows a detail of decoder 40 (decoder 42 has the same structure). The decoders 40, 42 consist of blocks for calculatingy values, blocks for performing iteration, and a soft bit 5 output block.
The first step in the decoding operation as shown in Fig.5 is to take three soft bits P3k(O), PUM, P3k+1 (0), P3k+1 (1) 9 P3k+2 (0), P3k+20) to form eight probability values (a normal turbo decoder has only two values because it contains only one bit of information): pk000, pk001, pk010, pk01 1, pk100, pk101, Pl'I 10, and pkI 11. For example, p k 000 = log [ P ro b( b3 k -= 0, b3 k + 1---2 0, b3 k + 2 0) 1 In general, = PWO) + P3k + 1 (0) + P3k + 2(0) Pkj 0=mni=000, 00 1,..., 111) can be obtained as p 3k + 2= rrinl = log[Prob(b3k= mb3k+l= n,b = P3k(nl)+P3k+l(n)+P3k+2(1) With Pkj and the corresponding error check bit (Pck(O), Pek(W, the valueyj (Rk, S', S) can be obtained as yj (Rk, s', s) = log (Pr(dk=j, Sk=s, Rk 1 Sk- 1 =S')) = Pj k + Pck(O where j=000, 001,.., 111 and m=0 or 1 depending on the error check bit when transferring from state s' to s. Rk represents the received information.
With yj (Rkp S', S), the forward iteration (a) iteration with LOG-MAP algorithm) can be implemented as shown in Fig.6, where the normalization block puts all yj (Rk, S', S) into the center of the dynamic range with the same normalization factor so that the whole dynamic range in a fixed point implementation can be utilized.
The same principle is applied to the output OCk(s), i.e., all Uk(s) at different state s (for the same iteration k) are normalized with a same normalize factor so that they are all located in the center of dynamic range. The determination of normalization factor is the same as that used in the normal turbo decoder implementation. The difference in the forward iteration is that each state s at iteration k (M(s)) is determined by eight previous states ((X'k-l(S'000), OC'k- I(S'001),.... CC'k-1 (s', I,% each corresponding one input yj (Rks S% S) value (in a conventional turbo decoder, each state at iteration k is determined by only two previous states because the input is only one bit information). The LOG-ADD OPERATION in Fig.6 is shown in Fig. 7, which consists of a max operation and a look-up table.
The backward iteration has the same structure as the forward iteration and is shown in 10 Fig. 8.
After finishing forward and backward iteration, the soft bit outputs are calculated in two steps as follows:
first calculate eight p j k values for j =000, 00 1,...' I 11 as k P j = MAX (S' s,) [yj(Rk, S, S')(Xk - I (S')Dk(s)] Then the soft output is the combination of p j 3k values, such as P 3k (0) = prob(b 0)= Pkoo + Pk 10 + P k k 0 3k= 0 0 100 + Pilo 3k 1)= Pk 1 + Pk k k Po (1) = prob(b3k= 00 oil + Piol + Pill P 3k+ 1 (0) = prob(b 0) = pk k k k 0 3 k + 1 000 + Pool + Ploo + P loi 3k+ I k k k 10 + P k Po (1) = prob(b3k + 1 = 1)= Polo + poll + Pi ill P 3k+ 2 (0) = p ro b (b 0) = Pk k P k 10 + P k 0 3k+2= 000 + Pool + o Oil P 3k+ 2 (1) = prob(b k o + P k k P k 0 3k+2= 1)= Plo 101 + Pilo + ill At the last iteration, the soft error check bits are also outputted as:
P 3k+ Z (1)= prob(b 3k +Z= 1) c C = MAX(S' s')[Yckl (Rk, S, S,)(Xk - 1 (S')P VSA 3k+ 2 3k +2 PC (0)= prob(bc = 0) MAX(S,s')[YckO(Rk,S,S")(k-I(S")0k(s)I where ^ickO(Rk, St s') and YM(Rk, s, s') represent the transferring probability from state s' to s with error check bit (at time 3k+2) being 0 and 1 respectively.
The blocks described above can be implemented in a digital signal processor using standard digital processing techniques known to persons skilled in the art of digital signal processing.
The described techniques increase the implementation speed of the turbo encode and decoder and result in significant memory savings in the parallel decoder.
The invention is applicable to a decoder with a variable coding rate.
Claims (16)
1. An encoder for turbo coded trellis code modulation comprising an encoder data block for storing incoming data, and at least two parallel recursive systematic convolutional encoders, said recursive systematic convolutional encoders being connected 5 to receive data in parallel from said encoder data block.
2. An encoder as clairned in claim 1, wherein each said parallel recursive systematic convolutional encoder comprises a first set of adders, each adder connected to receive a plurality of data streams from said encoder block, a second set of adders connected to the outputs of the respective adders of the first set of adders, and delay units for feeding the 10 outputs of said second set of adders to their inputs in a recursive arrangement.
3. An encoder as claimed in claim 2, wherein each said parallel recursive systematic convolutional encoder further comprises a further adder connected to receive the some of said data streams from said encoder block and the outputs of some of said delay units, the output of said further adder providing the output of said recursive systematic 15 convolutional encoders.
4. An encoder as claimed in claim 2, wherein said output represents an error check bit.
5. An encoder as claimed in claim 2, wherein said data streams represent the least significant bits of said encoded data.
6. Decoding apparatus for a turbo coded trellis code modulation signal, comprising a pair of decoders performing forward and backward iteration on an input signal, and interleaver and de-interleaver, each decoder taking at n soft bit inputs for each turbo decoder iteration, where n is an integer greater than 1.
7. Decoding apparatus as claimed in claim 6, calculates 2 n probability values and 25 obtains the corresponding error check bit therefrom.
8. Decoding apparatus as claimed in claim 7, wherein each decoder comprises a normalization unit and a unit for performing a log-add operation to performing said iteration.
9. Decoding apparatus as claimed in claim 8, wherein unit for performing a log-add operation comprises a look-up table and a maximum operation unit.
10. A method of decoding a turbo trellis coded modulation signal, comprising: taking a number n of soft input bits, where n is an integer greater than 1, determining the probability values for the possible combinations of said n bits; and performing forward and backward iteration on said input bits in parallel to generate the decoded output.
11. A method as claimed inplaim 10, comprising first obtaining the value yj (Rks S'p S) 9 where -yj (Rk, s', s) = log(Pr(dk=j, Sk=s, Rk 1 Sk-l=s'))= Pj k + Pck(M) normalizing the values yj (Rk, s', s), and performing forward and backward iteration on the values yj (Rk, S', S).
12. A method as claimed in claim 11, wherein all the values yj (Rk, s', s) are normalized with the same normalization factor so that they are located in the center of dynamic range to permit the use of fixed point implementation.
13. A method as claimed in claim 12, wherein in the forward iteration, each state k ((AG)) is determined by 2' previous states.
14. A method as claimed in claim 10, wherein n is 3.
15. A method as claimed in claim 14, wherein after performing forward and backward iteration, the soft bit outputs are calculated in two steps as follows:
p k (i) calculate eight first calculate eight j values for j =000, 00 1,..., 111 as k p j = MAX(s' s,)[yj(Rk, S, S')% - 1 (S")0k(s)l (ii) then derive the soft output as the combination of p j 3k values, such as p 3k (0) = prob(b 0) = pk k p k oo + p k 0 3k= 000 + Polo + 1 110 3k Pk 1 +pk k k PO (1) = prob(b3k= I)= 00 Oil + Piol + Pill p 3k+ 1 prob(b 0) = pk oo +p k oi +p k k 0 (0) = 3k+l= 0 0 loo + P ioi p 3k+ 1 prob(b k + p k k 10 + P k 0 (1) = 3k+l= l)= Polo Oil + pi ill p 3k+ 2 (0) = prob(b k k k k 0 3k+2= 0)= P000 +Pool +Polo +Poll p 3k+ 2 (1) = prob(b k 0 + P k i +p k 10+P k 0 3k+2= l)= P10 10 1 ill
16. A method as claimed in claim 15, wherein at the last iteration, the soft error check bits are also outputted as:
3k+ 2 3k +2 PC (l)= prob(bc = 1) = MAX(S,s-)[Yckl(Rk,SS')0k-1(5')Pk(s)1 3k+ 2 3k +2 PC (0)= prob(bc = 0) = MAX(S,s,)llckO(Rk,S,S')(xk-I(S')Pk(s)I where 'YckO (Rk, s, s') and 'Yckl (Rk, SY S) represent the transferring probability from states' to s with error check bit (at time 3k+2) being 0 and 1 respectively.
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB0010330A GB2361852A (en) | 2000-04-28 | 2000-04-28 | Turbo coded trellis code modulation |
| DE2001120155 DE10120155B4 (en) | 2000-04-28 | 2001-04-25 | Modulation with parallel turbo-rotary coding |
| FR0105764A FR2808390A1 (en) | 2000-04-28 | 2001-04-27 | METHOD AND DEVICE FOR TURBOCODULATED PARALLEL TRELLIS MODULATION |
| CN 01115658 CN1330453A (en) | 2000-04-28 | 2001-04-27 | Parallel turbo grille coding modulation |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB0010330A GB2361852A (en) | 2000-04-28 | 2000-04-28 | Turbo coded trellis code modulation |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| GB0010330D0 GB0010330D0 (en) | 2000-06-14 |
| GB2361852A true GB2361852A (en) | 2001-10-31 |
Family
ID=9890652
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB0010330A Withdrawn GB2361852A (en) | 2000-04-28 | 2000-04-28 | Turbo coded trellis code modulation |
Country Status (4)
| Country | Link |
|---|---|
| CN (1) | CN1330453A (en) |
| DE (1) | DE10120155B4 (en) |
| FR (1) | FR2808390A1 (en) |
| GB (1) | GB2361852A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100444524C (en) * | 2002-08-01 | 2008-12-17 | 扎班纳数字资金有限责任公司 | Method, apparatus and system for encoding data bits in a communication system |
| CN103986557B (en) * | 2014-05-23 | 2017-06-13 | 西安电子科技大学 | The parallel block-wise decoding method of LTE Turbo codes in low path delay |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1998052362A2 (en) * | 1997-05-12 | 1998-11-19 | Siemens Aktiengesellschaft | Channel coding method |
| US6023783A (en) * | 1996-05-15 | 2000-02-08 | California Institute Of Technology | Hybrid concatenated codes and iterative decoding |
| WO2000022739A1 (en) * | 1998-10-13 | 2000-04-20 | Interdigital Technology Corporation | Hybrid interleaver for turbo codes |
-
2000
- 2000-04-28 GB GB0010330A patent/GB2361852A/en not_active Withdrawn
-
2001
- 2001-04-25 DE DE2001120155 patent/DE10120155B4/en not_active Expired - Fee Related
- 2001-04-27 CN CN 01115658 patent/CN1330453A/en active Pending
- 2001-04-27 FR FR0105764A patent/FR2808390A1/en not_active Withdrawn
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6023783A (en) * | 1996-05-15 | 2000-02-08 | California Institute Of Technology | Hybrid concatenated codes and iterative decoding |
| WO1998052362A2 (en) * | 1997-05-12 | 1998-11-19 | Siemens Aktiengesellschaft | Channel coding method |
| WO2000022739A1 (en) * | 1998-10-13 | 2000-04-20 | Interdigital Technology Corporation | Hybrid interleaver for turbo codes |
Also Published As
| Publication number | Publication date |
|---|---|
| GB0010330D0 (en) | 2000-06-14 |
| DE10120155A1 (en) | 2001-11-22 |
| DE10120155B4 (en) | 2008-08-28 |
| FR2808390A1 (en) | 2001-11-02 |
| CN1330453A (en) | 2002-01-09 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6769091B2 (en) | Encoding method and apparatus using squished trellis codes | |
| CA2147816C (en) | Punctured convolutional encoder | |
| JP3857320B2 (en) | Parallel connected tail biting convolution codes and decoders thereof | |
| JP3354554B2 (en) | Channel decoder and channel decoding method | |
| CN1207861C (en) | Communication system and method utilizing parallel coding without interleaving | |
| EP1221772B1 (en) | Pre-decoder for a turbo decoder, for recovering punctured parity symbols, and a method for recovering a turbo code | |
| CN1102813C (en) | Error correction with two block codes | |
| US6903665B2 (en) | Method and apparatus for error control coding in communication systems using an outer interleaver | |
| JP2001503588A (en) | Soft decision output for decoding convolutionally coded codewords | |
| EP1119109A1 (en) | Bandwidth-efficient concatenated trellis-coded modulation decoder and decoding method thereof | |
| CA2338919A1 (en) | A simple implementation of turbo decoder | |
| JP3674851B2 (en) | Scaling feedback turbo decoder | |
| US6570927B1 (en) | Method for tail-biting and decoding recursive systematic codes | |
| US6757859B1 (en) | Parallel turbo trellis-coded modulation | |
| CN1376337A (en) | Device and method for normalizing metric value of component decoder in mobile communication system | |
| GB2361852A (en) | Turbo coded trellis code modulation | |
| EP1094612B1 (en) | SOVA Turbo decoder with decreased normalisation complexity | |
| AU756612B2 (en) | Apparatus and method for normalizing metric values in a component decoder in a mobile communication system | |
| CN108880569B (en) | Rate compatible coding method based on feedback grouping Markov superposition coding | |
| CN119865193B (en) | A maximum a posteriori probability decoding method and system for high-rate convolutional codes | |
| CN115333549B (en) | A method for adaptively stopping iterations in Turbo code decoding | |
| Cai et al. | Source-controlled channel decoding using nonbinary turbo codes | |
| Osman et al. | Performance of multilevel turbo codes with group partitioning over satellite channels | |
| WO2001061891A1 (en) | Method and apparatus for decoding recursive convolutional symbols | |
| Buch et al. | Concatenated Reed-Muller codes for unequal error protection |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| WAP | Application withdrawn, taken to be withdrawn or refused ** after publication under section 16(1) |