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GB2356287B - Apparatus and method for packaging different sized semiconductor chips on a common substrate - Google Patents

Apparatus and method for packaging different sized semiconductor chips on a common substrate

Info

Publication number
GB2356287B
GB2356287B GB0017321A GB0017321A GB2356287B GB 2356287 B GB2356287 B GB 2356287B GB 0017321 A GB0017321 A GB 0017321A GB 0017321 A GB0017321 A GB 0017321A GB 2356287 B GB2356287 B GB 2356287B
Authority
GB
United Kingdom
Prior art keywords
semiconductor chips
different sized
common substrate
sized semiconductor
packaging different
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
GB0017321A
Other versions
GB0017321D0 (en
GB2356287A (en
Inventor
Tarun Verma
Larry Anderson
Jon Long
Bruce Pedersen
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Altera Corp
Original Assignee
Altera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Altera Corp filed Critical Altera Corp
Publication of GB0017321D0 publication Critical patent/GB0017321D0/en
Publication of GB2356287A publication Critical patent/GB2356287A/en
Application granted granted Critical
Publication of GB2356287B publication Critical patent/GB2356287B/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H10W70/65
    • H10W70/656
    • H10W72/07251
    • H10W72/07353
    • H10W72/075
    • H10W72/20
    • H10W72/251
    • H10W72/29
    • H10W72/334
    • H10W72/50
    • H10W72/884
    • H10W72/931
    • H10W72/9445
    • H10W72/951
    • H10W90/724
    • H10W90/734
    • H10W90/754
GB0017321A 1999-07-15 2000-07-17 Apparatus and method for packaging different sized semiconductor chips on a common substrate Expired - Fee Related GB2356287B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US14397499P 1999-07-15 1999-07-15

Publications (3)

Publication Number Publication Date
GB0017321D0 GB0017321D0 (en) 2000-08-30
GB2356287A GB2356287A (en) 2001-05-16
GB2356287B true GB2356287B (en) 2004-03-24

Family

ID=22506517

Family Applications (1)

Application Number Title Priority Date Filing Date
GB0017321A Expired - Fee Related GB2356287B (en) 1999-07-15 2000-07-17 Apparatus and method for packaging different sized semiconductor chips on a common substrate

Country Status (1)

Country Link
GB (1) GB2356287B (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10146306A1 (en) * 2001-09-19 2003-01-02 Infineon Technologies Ag Electronic component with semiconducting chip(s) has bearer substrate with at least sectionally parallel conducting tracks on surface facing chip(s) in contact with chip contact surfaces
CN113709970B (en) * 2021-07-16 2022-03-04 北京金百泽科技有限公司 Electronic equipment, PCB and chip packaging structure thereof

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4195195A (en) * 1978-09-28 1980-03-25 The United States Of America As Represented By The Secretary Of The Army Tape automated bonding test board
GB2115607A (en) * 1982-02-05 1983-09-07 Hitachi Ltd Semiconductor device and a method of producing the same
EP0171232A2 (en) * 1984-08-09 1986-02-12 Minnesota Mining And Manufacturing Company Area-bonding tape
US5399903A (en) * 1990-08-15 1995-03-21 Lsi Logic Corporation Semiconductor device having an universal die size inner lead layout
US5637920A (en) * 1995-10-04 1997-06-10 Lsi Logic Corporation High contact density ball grid array package for flip-chips

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4195195A (en) * 1978-09-28 1980-03-25 The United States Of America As Represented By The Secretary Of The Army Tape automated bonding test board
GB2115607A (en) * 1982-02-05 1983-09-07 Hitachi Ltd Semiconductor device and a method of producing the same
EP0171232A2 (en) * 1984-08-09 1986-02-12 Minnesota Mining And Manufacturing Company Area-bonding tape
US5399903A (en) * 1990-08-15 1995-03-21 Lsi Logic Corporation Semiconductor device having an universal die size inner lead layout
US5637920A (en) * 1995-10-04 1997-06-10 Lsi Logic Corporation High contact density ball grid array package for flip-chips

Also Published As

Publication number Publication date
GB0017321D0 (en) 2000-08-30
GB2356287A (en) 2001-05-16

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Legal Events

Date Code Title Description
PCNP Patent ceased through non-payment of renewal fee

Effective date: 20170717