GB2348760A - Edge modulation of wipe solids - Google Patents

Abstract

A signal generator comprises means for producing a ramp signal for each pixel h of a set of pixels. (h=0 to n) on each of a set of video lines v (v=0 to m). The signal , in the line direction and on each of the lines comprises a set of repeated ramps R=Lh' (where h' is a subset of the pixels h). The phase of the sets of repeated ramps is offset from line to line by N+Mv, where L, M and N are coefficients of signed value. The generator further comprises means for transforming the ramp signals to another form, and means for modulating another signal representing an edge of a solid with the transformed ramp signal. Modulation of the entire solid can also be performed while edge modulation by random noise, generated via a random number generator, is also disclosed.

Description

EDGE MODULATION The present invention relates to an edge modulator. Such a modulator is for modulating edges of'solids'used in a video wipe generator of a vision mixer.

A solid is an electrical signal representing a three dimensional surface of a desired shape. It comprises at least one ramp signal and typically comprises a combination of at least two ramp signals which themselves may be modified. It may also comprise a signal defined by a polar coordinate system representing a curved surface.

Reference will now be made to Figures 1 to 3 of the accompanying drawings which show background to the present invention.

Figure 1 illustrates a known simple wipe between two video sources X and Y.

As the wipe proceeds as indicated by arrow W, video X is replaced across the display by video Y (or vice versa). The effect of a wipe is achieved by mixing the video sources X and Y according to KX + (1-K) Y where K is a keying signal. The keying signal K is derived from a'solid'. This will be explained with reference to Figures 2 and 3 i. e. a function having a value depending on the h and v co-ordinates within the picture, where v represents line number and h represents pixel position along a line.

Figure 2 a illustrates a known example of a'solid'which is a simple ramp. As shown in Figure 2, a clip level CP is defined. It will be appreciated that over a field or frame, the clip level defines a plane referred to herein as the clip plane, which will be described in more detail with reference to Figure 4 below. The keying signal K is, in known manner, derived from the solid by applying high gain to the solid and limiting the result, as shown in Figure 2B. The keying signal has two levels 0 and 1. The transition between the levels occurs where the solid intersects the clip plane CP. The position of intersection is varied, to produce the wipe, by adding an offset to the solid.

Figure 3 is a schematic block diagram of a wipe generator of a vision mixer comprising a solid generator, a clip element, a gain element, a limiter and a mixer which mixes video sources X and Y in dependence upon the keying signal K.

The solid generator produces a solid, for example a ramp as shown in Figure 2A.

The clip element applies an offset to the ramp to vary the intersection of the ramp with the clip plane CP as shown in Figures 2A to 2C. Gain is applied to the offset ramp, in the gain element and the result limited in the limiter to produce the signal K. The amount of gain applied may be varied as shown in Figure 2B: that varies the slope of the transition between the limit values of the keying signal K.

The mixer mixes the video sources X and Y according to KX + (1-K) Y.

This is K=1, the output is X, if K=0 the output is Y.

If the gain applied to the solid is unity and the clip offset is zero, the solid and the keying signal are identical.

Although edge modulation is a known effect, it is desired to provide an edge modulator which is flexible in operation and able to provide a large range of modulating signals to provide a large range of edge modulation effects.

According to one aspect of the present invention, there is provided a signal generator comprising means for producing a ramp signal for each pixel h of a set of pixels (h = 0 to n) on each of a set of video lines v (v = 0 to m), wherein the signal, in the line direction and on each of the lines comprises a set of repeated ramps R=Lh' (where h'is a subset of the pixels h) the phase of the sets of repeated ramps being offset from line to line by N+Mv, where L, M and N are coefficients of signed value and means for transforming the ramp signals to another form and means for modulating another signal representing an edge of a solid with the transformed ramp signal.

According to another aspect of the present invention, there is provided a signal generator comprising means for producing a ramp signal for each pixel h of a set of pixels (h = 0 to n) on each of a set of video lines v (v = 0 to m), wherein the signal, in the direction perpendicular to the line direction comprises a set of repeated ramps R=Mv' (where v'is a subset of the lines v) the phase of the sets of repeated ramps being offset from pixel to pixel on the initial line by N+Lh, where L, M and N are coefficients of signed value and means for transforming the ramp signals to another form and means for modulating another signal representing an edge of a solid with the transformed ramp signal.

According to a further aspect of the present invention, there is provided a signal generator comprising a ramp generator for producing a ramp signal for each pixel h of a set of pixels (h = 0 to n) on each of a set of video lines v (v = 0 to m), the generator comprising means for storing coefficients L, M, and N, having signed values, and a feedback value, an accumulator having an adder having first and second inputs and an output, and a register having an input coupled to the output of the adder and an output coupled to the second input of the adder and to the storing means for supplying the feedback value thereto, selecting means for loading the register with a selected one of N and the feedback value and for coupling a selected one of L and M to the first input of the adder, and control means for initially loading the register with, and storing as the feedback value, either N+Lh or N+Mv and for coupling either M or L respectively to the first input of the adder for successively incrementing the value loaded in the register pixel by pixel and means for transforming the ramp signal to another form, and means for modulating another signal representing an edge of a solid with the transformed ramp signal.

The transform of the ramp signal includes providing the ramp signal unchanged in form as the modulating signal. Other transforms include transforming the ramp signal to square form. triangular form, and to sinusoidal from, amongst many other possibilities.

Such a signal generator provides great flexibility. For M=0 choice of L defines the repetition frequency of the ramps in the line direction. For Ln0, choice of M defines the repetition frequency of the ramps in the direction perpendicular to the lines. Choice of N defines the start phase of the ramps at the beginning of the first line (h=0). For a value of L which defines a repetition frequency in the line direction, choice of M defines the phase offset of the ramps from line to line. For a value of M which defines a repetition frequency in the frame direction, choice of L defines the phase offset of the ramps from pixel to pixel. Thus L and M together define the rotation of the ramps.

The transform means allows the modulation pattern defined by the ramps to be changed into other forms. Thus the invention provides a large range of edge modulation signals which are easily changed by choice of L, M and N and which are transformable into other forms. Thus the generator is flexible and provides the user with the possibility of creating many different effects limited only by the range of signals which can be generated.

The present invention also provides a solid generator comprising: a plurality of signal generators according to any preceding aspect, a plurality of ramp generators for producing respective ramps representing edges of a solid, and coupled to respective combining means of the said signal generators to be modulated thereby, and means for combining the modulated ramps to form the said solid.

For a better understanding of the present invention, reference will now be made by way of example to the accompanying drawings in which: Figure I illustrates a wipe; Figure 2 illustrates a solid together with a keying signal : Figure 3 is a schematic block diagram of a known wipe generator; Figure 4 is a diagram illustrating a solid together with a clip level ; Figure 5 is a block schematic diagram of an illustrative ramp generator; Figure 6 illustrates negating a ramp coefficient; Figure 7 illustrates examples of limiting the value of the ramp signal ; Figure 8 is a block diagram of a solid generator system; Figures 9A to E are diagrams illustrating absoluting, negating, lift and combining operations; Figure 10 is a block diagram of a ramp combiner ; Figure 11 is a block diagram of a non-additive mixer of the combiner of Figure 10; Figure 12 is a schematic block diagram of another ramp generator for use in an edge modulator; Figure 13 is a schematic block diagram of an edge modulator; and Figure 14 is a diagram showing edge modulation patterns; Figures 15A to E illustrate the operation of the edge modulator; Figure 16 is a simplified illustration of an example of solid modulation ; and Figure 17 is a schematic block diagram of a circuit for producing a solid modulation waveform.

The ramp generator of Figure 5 produces a solid according to the equation R=Ah+Bv+C where A, B, and C are selectable coefficients, v is line number and h is pixel position along a line. The equation defines a three dimensional ramp R in three dimensional space as shown by way of example in Figure 4. The ramp value R is calculated from A, B and C individually for each pixel h on each line v.

The values are represented by signed numbers, preferably twos complement numbers. As will be explained in more detail hereinafter, the value of h ranges from 0 to n and the value of v ranges from 0 to m.

The lines ~ of a field or frame over which the ramp is produced are selectable and the pixels h within those lines are also selectable provided the lines y are a contiguous set of lines and the pixels h are a contiguous set of pixels. The ramp may be generated in a field or in a frame. For ease of explanation the following description is based on the assumption that a progressively scanned frame is used.

The ramp values R can range from a negative maximum value-M through zero to a positive maximum value +M. The dynamic range DR of a ramp is such that the ramp may effectively be much larger in area than the area of an active frame of a video.

Referring to Figure 4 lines v of a whole progressively scanned TV frame are shown numbered 0, 1,2... m. Pixel positions h of whole lines are shown as 0 to m. An illustrative ramp R is shown which is offset from a reference plane RP at-M by C.

By way of initial and simplified explanation a clip plane represented by plane CP is shown in Figure 4 intersecting the ramp R along a line L. The position at which the ramp intersects the clip plane CP is defined by the offset C. On line v=0 the ramp has slope A. For pixel h = 0 on lines ~, the ramp has slope B. The transition region of the keying signal K occurs along the line L. Where K exceeds the clip plane CP video from one source Y forms part of a displayed image and where K is equal to or less than the clip plane video from another source X forms the other part of the displayed image, as described above with reference to Figures 1 and 3.

The solid generator of Figure 5 comprises registers R1 (INC A), R2 (INC B) and R3 (Start C) for storing preselected values of the coefficients A, B and C. The registers R1, R2 and R3 are coupled to an increment selector SEL1 which selectively couples the registers R1 to 3 to an adder 1 via a register REG1 which is clocked by a pixel rate clock signal HFCK~SYS. Feedback registers FB 1 and FB2 are coupled to another, feedback selector SEL2 which selectively connects the feedback registers FB 1 and 2 and an input of ZERO to the adder 1. The output of the adder is connected to an output register REG2 also clocked by the pixel clock HFCKSYS. The registers R1 to 3 and FB1 and FB2 and the selectors SEL1 and 2 are controlled by a real-time controller which receives line pulses IP~H and frame pulses EP~V and the clock HFCKSYS and produces IncSel and AccSel signals for controlling the selectors SEL 1 and 2. The controller also controls the loading of the coefficients A, B and C into the registers R1 to R3.

A computer 6 generates the coefficients A, B and C and control data for each frame, in advance of the frame, and provides the coefficients and the control data to the real-time controller 2. The controller 2 feeds the coefficients to the registers R1, R2, R3. The computer 6 acts as an interface between operator controls and the controller 2. It generates the coefficients A, B and C in accordance with the setting of the controls by the operator.

The generator operates as follows with reference to Figure 4. The basic principle is that the adder 1 adds an increment from one of the registers R1 to R3 to an accumulated value stored in one of the registers FB 1 and FB2 and feeds the sum back to one of the registers FB 1, FB2 for addition to another increment.

Referring to Figure 4, assume for ease of description that a ramp R is to start at pixel h=0 of line v=0 with an offset C and coefficients A and B. Assume A, B and C are loaded into the registers R1 to R3 once per frame. The controller, on receiving a frame start pulse IPV indicating the start of the active lines of a frame, causes selector SEL1 to select the value C in register R3 and feed it to the adder 1 via the register REG1 on a first HFCK~SYS pulse. At the same time, the selector SEL2 selects the value ZERO and feeds it to the adder 1. The sum C+0 is fedback to the registers FB 1 and FB2 and stored in both of those registers. The sum is also fed to the output register REG2 for outputting on the next HFCK~SYS pulse coefficient (A) is selected from register Rl by selector SEL1, and FB1 is selected from by selector SEL2. Register FB 1 now accumulates successive increments of C+hA along line v=0 for h=0 to n. At the end of the line the store FB 1 contains C+nA. Pulse IP H, indicating the beginning of a new line, occurs and increment B is selected from register R2 by selector SEL1, and selector SEL2 selects the content C of register FB2. Coefficient B from register R2 and C from FB2 are added in adder 1 to produce a new sum B+C which is fed back to both registers FB1 and FB2. Thus both contain the ramp value B+C for the beginning of line v=I at position h=0. The selector SEL2 selects register FBI which now accumulates C+B+hA for h=0 to n along line v=1 until the end of the line when the next IPH pulse occurs. At the end of line v=l the register FBI contains C+B+nA. The selectors again select coefficient B in register R2 and register FB2 to increment the contents of FBI and FB2 to C+2B at the beginning of line v=2. Register FBI then accumulates by A along line v=2 until pulse D-H occurs and registers FBI and 2 are again incremented by coefficient B. The process repeats line by line until the next pulse U-V occurs indicating the end of the frame and the beginning of the next frame. The whole process repeats for each frame.

It will be appreciated that the ramp is built up pixel by pixel in synchronism with the clock signals HFCKSYS.

The foregoing description assumes that the ramp occupies a whole frame. A ramp may occupy only a part of a frame as will be described with reference to Figures 29 to 39, for example.

Inverted Ramps The foregoing description describes ramps in which the value R of the ramp is successively incremented i. e. increased for each addition of a coefficient A or B. The generator of Figure 5 allows a ramp value to be successively decremented to produce an inverted ramp. This is done using a negate circuit 3, comprising an EXOR circuit and the register REG1, and which negates the increments held in the registers RI to R3 after selection by the selector SEL1. The increments are in 2s complement form.

Negating a 2s complement number is done by inverting the bits of the number and adding one. The EXOR circuit inverts the bits of the selected increment in response to a negate control bit negCtrl and the negate control bit is fed into the register REG1 as a carry bit to add one. Thus as shown in Figure 6A for a one dimension of a ramp 60, a positive ramp 60 is produced in the manner described above upto a desired maximum level and then as shown in figure 6B it is successively decremented using the negated increments. The operation of the ramp generator is otherwise unchanged. The negate control bit neg Ctrl is provided by the controller. It is possible to produce an inverted ramp over a frame by negating the coefficient A and/or B.

Limiting Ramps.

In order to prevent over or under flow, a limiter 4 is provided in the feedback path from the adder to the feedback registers FB 1 and FB2. Another limiter 5 is provided at the output of the generator.

Referring to Figure 7 this output limiter 5 may limit a positive extreme ramp value to a positive limit or a negative limit as shown in Figure 7a and 7b or limit a negative extreme value to either a negative or a positive limit as shown in Figures 7c and d. The limiter is controlled by the controller to select the desired limiting property.

Effects of Varying A. B and C Increment A defines the slope of the ramp in the line direction. Increment B defines the slope of the ramp in the frame direction, perpendicular to the line direction. A and B together can have the effect of rotating the ramp in space if they are scaled differently. C offsets the ramp in a direction perpendicular to the line and frame directions. C has the effect of shifting the intersection of the ramp with the clip plane.

By varying C the position of a ramp can be moved in a frame.

Example of a Solid Generation System Combining Rampes Referring to Figure 8, there is shown a simplified block diagram of a solid generation system.

The generation system comprises a plurality of ramp generators 80 as described for example with reference to Figures 5 to 7. The system of Figure 8 has only two, ramp generator (and only one is shown) but there may be many more, for example 8 ramp generators. The ramps are combined in a combiner 86. In the combiner, the ramps are combined in a manner defined by control signals.

Each ramp generator produces a ramp which may be'edge modulated'81 as described with reference to Figures 12 to 15. The ramp may also be subject to absoluting, negating, offsetting and limiting as indicated by blocks 82 to 85. A"box solid"produced by combining two absolute ramps will be described with reference to Figures 9,10 and 11. Ramps may be combined in the combiner 86 as will be described with reference to Figure 10. The level and scale of the solids relative to the clip plane may be adjusted by an adjuster 89. A solid selector 87 selects the solid from the combiner 86 or a solid generated externally.

It will be appreciated that the system of Figure 8 is illustrative only. The techniques of ramp generator, edge modulation and solid modulation, may be used in other solid generator systems as will also be described hereinbelow.

The system is controlled by a controller 802. The controller 802 stores and implements algorithms which define wipe patterns which are selected by a control panel 803.

Figure 9A shows a single ramp which has a dynamic range of-M through to zero to +M. The ramp is represented by (signed) twos complement numbers. An absolute function (82), in known manner, transforms all the numbers representing the ramp to positive numbers, thus producing a ramp as shown in Figure 9B. The ramp of Figure 9B may be negated 83 as shown in Figure 9C, i. e. it is represented by negative numbers. The absolute ramp may be subject to an offset 84 by adding a fixed value to the ramp.

Figure 9D shows the negated, absolute ramp of Figure 9C with an offset. The ramp of Figure 9B may be offset in similar manner.

In general a ramp may be modified by any one or more of absoluting, negating and offsetting.

Figure 9E shows, as an example of a solid, a"square"solid, which is a rectanguiar pyramid formed by combining two ramps shown in Figure 9D, one ramp being at right angles to the other.

An example of a preferred combiner is shown in Figure 10. Two ramps A and B (which may be modified by the processing circuits 81 to 85) are fed to a selector 96 having inputs 0 to 3. Input 0 receives ramp A. Input 1 receives ramp B. Input 2 receives a first combination of the ramps from a first combining circuit 97 and a divide-by-2 circuit 98. Input 3 receives a second combination of the ramps from a second combining circuit 99. The one of the inputs 0 to 3 to be coupled to the output of the selector is selected by a two bit selection signal SEL. The output of the selector 96 is coupled to the output of the combiner 93 via another selector 100 which selects the output of the selector 96 or zero according to a zero select signal. If the select signal SEL is 0 or 1, ramp A or B is passed to the output unmodified. The combiner 93 then acts as a switch or signal router.

The first ramp combining circuit comprises an adder 97 and a divide by two circuit 98. The divide by two circuit has a control input for receiving a divide-by-2 control signal. The divide-by-2 control signal selectively actuates the divide-by-2 circuit 98. Thus input 2 of the selector 96 receives either (A+B) or (A+B)/2.

The second ramp combining circuit 99 is a Non-Additive Mixer also known as a NAM an example of which is shown in Figure 11. Referring to Figure 11, the NAM comprises first second and third selectors 101 102 and 103 and a comparator 104. The comparator compares the instantaneous values of the ramps A and B. If A > B then it outputs logic 0 otherwise it outputs logic 1. The first and second selectors select input 0 or I according to the output of the comparator. The third selector selects the first or second selector according to the value of a POS/NEG signal. The overall truth table of the NAM is: COMPARISON OF RAMPS POS/NEG OUTPUT OF NAM A > B POS A B > A POS B A > B NEG B B > A NEG A For POS/NEG POS, the NAM outputs whichever of A and B is greater at any moment in time, i. e. at any pixel position. For POS/NEG NEG the NAM outputs whichever of A and B is smaller.

Overall, the combiner 93 selects one of the ramps A and B, an additive combination of the ramps, a non-additive combination of the ramps or zero.

Box Soli A'box solid'is a well known solid. Referring to Figures 9,10 and 11, it may be produced by absoluting two ramps at right angles to each other and combining them using a negative NAM function.

The result is a square pyramid as shown in Figure 9E. Another solid may be produced using a positive NAM function. Other solids can be produced using the add function.

Edge Modulation Figure 15B shows one example of an edge modulating signal. The signal comprises a sine wave in the line direction and which repeats on every line of a frame. Figure 15C shows a sine wave which is in the frame direction and which repeats in the line direction. Figure 15D shows a sine wave in the line direction but which is phase shifted from line to line the result being a set of waves having a wavefront WF directed at an angle 6 to the line direction. Figure 15E shows a solid, in this case a simple ramp, combined with a frame of sine waves as shown in Figure 15C which modulates the whole ramp to effect edge modulation at the clip level CP.

The edge modulation function is produced by a ramp generator as shown in Figure 12 which produces a ramp output which is transformed by the circuit of Figure 13 to produce the desired edge modulation wave form. For ease of explanation Figures 12 and 13 will be described initially with reference to the production of a sine modulation signal as shown in Figure 15A.

Referring to Figure 12 the ramp generator comprises an output register REG which is clocked at the pixel rate by a clock signal HFCK~SYS. The output of the register REG is fedback to one input of an adder 121 which has another input coupled by a selector SEL1 to coefficient registers 122 and 123 which store coefficients L and M. The adder is coupled to the register REG via a selector SEL3. Ignoring the selectors, the register REG and the adder 121 form an accumulator which successively adds a selected coefficient to the contents of register REG. The register is not reset: once it has accumulated its maximum value e. g. all'I's it reverts to its minimum value e. g. all'0's. The register REG thus repeatedly outputs a sequence of values.

The selector SEL3 allows the register REG to be preloaded with a value N in a register 124 or the value in a feedback register 125 selected by a selector SEL2. The value stored in register REG is incremented by a coefficient L or M selected by the selector SEL 1.

The generator operates as follows to produce a ramp signal according to the equation R=Lh+Mv+N where h is pixel position along a line, and v is line number. the numbers h and ~ are ordinal ; h=0 to n and v=0 to m.

At h=0 on line v=0, the selectors SEL2 and 3 select the coefficient N from register 124 and preload register REG with N. The register REG outputs N which is feedback to the adder 121 and to the enabled fedback register 125 where it is stored. On pixel h=1 the value N is incremented by value L selected from register 122 by selector SELI, so that register REG contains N+L which is output and fedback to the adder 121, but not to the feedback register 125 which is disabled. The register REG and the adder then accumulate N+hL. Once the register REG contains its maximum value N+hL for the first time it rolls over and repeats the accumulation of hL from zero. The accumulation of hL continues until the end of line v=0. The frequency of repetition of the accumulation of hL depends on the value of L. The start phase of the accumulation depends on N.

At the end of line v=0, the selectors SEL2 and 3 select N and preload register REG again with N which is fedback to the adder 121. If desired, selector SEL1 selects M which is added to N in the adder and stored in the register REG and output and fedback to the adder 121 and also to the now enabled feedback register 125 where N+M is stored. The selector SEL1 now selects L and N+M+hL is accumulated until the register REG reaches its maximum value for the first time on line v=l. The register then rolls over to zero and hL is repeatedly accumulated along line v=1 as before. At the end of line v=l, the selector SEL2 selects N+M from the now enabled feedback register 125 and the register REG is preloaded with N+M via selector SEL3. N+M is output and fedback to the adder. Selector SELI selects M from register 123 and adder produces N+2M which is stored in register REG and output and feedback to the adder and to the now enabled feedback register 125 where it is stored. Thereafter N+2M +hL is accumulated as on the preceding lines. The process repeats on successive lines with the preload value in register REG incremented by M on each line. The effect of M is to shift the phase of the accumulation on each line by an amount dependent on M.

The ramp values R output by the register REG are used to address a look-up table in a ROM 130 of Figure 13 to produce a sine modulation. Although the ROM could be arrange to store a whole sine cycle in this embodiment it stores only one quadrant of a sine wave to minimise the data stored. In this example the value R is an 11 bit twos complement number. The 9 less significant bits are used to address the ROM. The two most significant bits are used to indicate which quadrant is to be produced. Referring to Figure 15A, four quadrants of a sine function are shown at a to ~. Assuming MSBs 00 select quadrant a, then quadrant b (01) is produced by inverting the 9 bit address in inverter 133. Quadrant c (10) is produced by negating the sine function data in negater 134 and quadrant d (11) is produced by both inverting the address and negating the sine-function data.

Referring again to Figure 13, the two MSBs of the 11 bit ramp signal R are fed to logic 132 to indicate which quadrant to produce. Logic 132 then produces a invert (negate) enable signal S, a 1-bit address invert enable signal I, and a 2-bit switch control signal for controlling a selector 136 according to the indicated quadrant. The 9 LSBs of the ramp signal R are fed to the ROM 130 via an address inverter 133 which either inverts the address or does not invert it according to the invert enable signal I from logic 132. The address from the inverter addresses the ROM 130 to produce the desired quadrant. The ROM output data is fed to the negater 134 which negates the sign or not according to the sign negate enable signals form the logic 132. The negater 134 is followed by a gain adjuster 135 which controls the amplitude of the modulation. The modulation is then added to the solid produced by ramp generator 80 in the adder 81 of Figure 8 for example.

Referring to Figure 15B, an example of a sine modulation is shown. This example is produced when N=0, and M=0. The frequency of the modulation is dependent on L. The sine repeats on each line with any phase shift relative to the beginning of each line as provided by N or relative to each preceding line as provided by M. Figure 15C is an example for N=0 and L=0. The sine modulation is in the frame direction. Figure 15D is an example for N=0 and L and M have non-zero values. The sine modulation is directe at an angle which is dependent on L and M. M produces an accumulative phase shift from line to line.

When the modulation of Figure 15C is added to a solid, in this example a simple ramp, the result is as shown in Figure 15E. The clip level intersects the modulated ramp along a line CL which is the projection of the modulation onto the clip level plane. The modulation applies to only one edge. If several edges of a solid are to be modulated, each ramp forming the solid requires to be separately edge modulated before the ramps are combined.

Referring to Figures 13 and 14, edge modulation patterns other than sine functions may be produced. As shown in Figure 14e to h, a triangular modulation may be produced simply by applying inversion and/or negation to the otherwise unmodified ramp signal R. As shown in Figure 14i to 1, a square wave may be produced by selectively negating and/or inverting the two MSBs of the ramp signal.

Referring to Figure 13, these other modulation patterns are produced under the control of logic 132. The logic 132 decodes the quadrant selection to produce a 4 bit number representing decimal 0 to 15 as shown in Figure 14 to choose the combination of negation, inversion and pattern type. The pattern selection signals are applied to a selector 136 to select the sine ROM 130, the ramp itself at input 137, or the square wave pattern produced by logic 138 from the two MSBs of the ramp signal. The edge modulator of Figure 13 also has an input 139 for receiving pseudo-random numbers. The selector is controllable to select the input 139. The effect is an edge modulated by random'noise'. The logic 132 may comprise a 16-bit register operating as a 4 by 4-bit look-up table. The register is programmable via a 16-bit input, to define various edge-modulation patterns.

Solid Modulation Figure 16 illustrates, in simplified form, one example of solid modulation. In this example a box solid 161, (formed by combining absoluted ramps as described above) is combined with the additive sum of two sinusoidal waveforms 162,163 at right angles to each other. In the clip plane, the result will be approximately as shown at 164.

It will be appreciated that solid modulation differs from edge modulation in that it occurs after a plurality of ramps have been combined, and/or it uses a combination of two modulating waveforms.

Thus, solid modulation is modulating an entire solid (in contrast to just an edge) with a modulation waveform, which modulation waveform most preferably is itself a combination of two different waveforms.

In the example of Figure 17, the solid modulation is generated by combining two waveforms generated by generators 170 and 171 as described with reference to Figures 13 and 14. The waveforms are combined by a combiner 172 as described with reference to Figures 10 and 11. The two waveforms which are combined may be any two of the types produceable by a generator of Figure 13. For example a sine wave may be combined with a square wave. Those types are additionally variable in accordance with the values of the coefficients L, M and N. In addition the combiner 172 provides additive and non-additive combinations. Thus a very large number of different modulations can be produced.

Although Figure 17 combines only two waveforms, more than two could be combined. The solid modulator may be additional to the edge modulator or may be provided instead of the edge modulator.

Solid modulation may be applied to a solid which has no edge modulation or to a solid which has edge modulation.

Claims (21)

1. CLAIMS 1. A signal generator comprising means for producing a ramp signal for each pixel h of a set of pixels (h = 0 to n) on each of a set of video lines v (v = 0 to m), wherein the signal, in the line direction and on each of the lines comprises a set of repeated ramps R=Lh' (where h'is a subset of the pixels h) the phase of the sets of repeated ramps being offset from line to line by N+Mv, where L, M and N are coefficients of signed value and means for transforming the ramp signals to another form, and means for modulating another signal representing an edge of a solid with the transformed ramp signal.
2. 2. A signal generator comprising means for producing a ramp signal for each pixel h of a set of pixels (h = 0 to n) on each of a set of video lines v (v = 0 to m), wherein the signal, in the direction perpendicular to the line direction comprises a set of repeated ramps R=Mv' (where v'is a subset of the lines v) the phase of the sets of repeated ramps being offset from pixel to pixel on the initial line by N+Lh, where L, M and N are coefficients of signed value and means for transforming the ramp signals to another form, and means for modulating another signal representing an edge of a solid with the transformed ramp signal.
3. 3. A signal generator comprising a ramp generator for producing a ramp signal for each pixel h of a set of pixels (h = 0 to n) on each of a set of video lines v (v = 0 to m), the generator comprising means for storing coefficients L, M, and N, having signed values, and a feedback value, an accumulator having an adder having first and second inputs and an output, and a register having an input coupled to the output of the adder and an output coupled to the second input of the adder and to the storing means for supplying the feedback value thereto, selecting means for loading the register with a selected one of N and the feedback value and for coupling a selected one of L and M to the first input of the adder, and control means for initially loading the register with, and storing as the feedback value, either N+Lh or N+Mv and for coupling either M or L respectively to the first input of the adder for successively incrementing the value loaded in the register pixel by pixel and means for transforming the ramp signal to another form, and means for modulating another signal representing an edge of a solid with the transformed ramp signal.
4. 4. A generator according to claim 3, wherein the register is arranged to continually cycle through the range of values which are stored therein as the stored value is successively incremented, whereby a repeated set of ramps is produced.
5. 5. A generator according to claim 1,2,3 or 4, wherein the modulating means comprises means for selectively combining the ramp signal with the other signal.
6. 6. A generator according to any preceding claim, wherein the transforming means comprises means for deriving a square wave from the said ramp signal.
7. 7 A generator according to any preceding claim, wherein the transforming means comprises means for deriving a triangular wave from the said ramp signal.
8. 8. A generator according to any preceding claim, wherein the transforming means comprises means for deriving a sine wave from the said ramp signal
9. 9. A generator according to any one of claims 1 to 8, wherein the transforming means is arrange to transform the ramp signal to any selectable one of a plurality of transformed signals and comprising means for selecting the one of the transformed signals to be applied to the modulating means.
10. 10. A generator according to any preceding claim, wherein the transforming means comprises means, including a look-up table, addressable by the ramp signal, the look-up table containing data which represents the said other form of signal.
11. 11. A generator according to any preceding claim, comprising means for selecting the values of L, M and N
12. 12. A signal generator substantially as hereinbefore described with reference to Figures 12 to 14 of the accompanying drawings.
13. 13. A solid generator comprising : a plurality of signal generators according to any preceding claim, a plurality of ramp generators for producing respective ramps representing edges of a solid, and coupled to respective combining means of the said signal generators to be modulated thereby, and means for combining the modulated ramps to form the said solid.
14. 14. A solid generator according to claim 13, wherein each ramp generator produces a video ramp signal Rr for each pixel of a predetermined set of pixels hr where hr=0 to n of each of a predetermined set of video lines vr where vr= 0 to m, wherein Rr=Ahr+Bvr+C where A, B, and C are coefficients each having a signed value.
15. 15. A solid generator according to claim 14, wherein each ramp generator comprises means for storing the coefficients A, B, and C and first and second accumulated values, adding means for incrementing the first accumulated value by A and the second accumulated value by B, and control means by which, for each of the said lines vr, the second accumulated value is incremented by the adding means by B to form C+Bvr which is stored as both the first and the second accumulated values, and for each pixel of the said set of pixels on each of the said lines the first accumulated value is incremented by the adding means to form C+Bvr+Ahr which is stored as the first accumulated value and is output as Rr.
16. 16. A solid generator according to claim 15, wherein the storing means of each ramp generator comprises coefficient registers for storing respective ones of A, B and C and feedback registers for storing the first and second accumulated values, and means for selectively coupling the registers to the adding means and for storing the output of the adding means in at least one of the feedback registers.
17. 17. A solid generator according to claim 16, wherein the control means of each ramp generator comprises selecting means for selectively coupling the registers to the adding means, and the output of the adding means is coupled to the feedback registers, the control means selectively enabling the registers to store the accumulated values.
18. 18. A solid generator according to claim 14 15 16, or 17, wherein the coefficients A, B and C are signed numbers and further comprising means for selectively inverting the sign of the coefficients before application to the adding means.
19. 19. A solid generator according to anyone of claims 14 to 18, comprising means for selectively limiting the value of the ramp signal Rr.
20. 20. A solid generator according to any one of claims 14 to 19, wherein the each ramp generator further comprises means for selecting the said set of lines vr and the said set of pixels hr within a picture.
21. 21. A solid generator according to any one of claims 14 to 20, further comprising means for selecting the values of the coefficients A, B and C.