GB2239113A - Power saving in conputer systems - Google Patents

Abstract

A comptuer system having a principal CPU chip and a separte memory chip, wherein the principal CPU chip is address line encoded, for example by Gray coding, so that in use the address codes on the address bus are changed sequentially so that at each access step only one address code is changed. Information on the data bus may be analogously encoded.

Description

Title: Improvements in Computer SYstems Field of the Invention This invention relates generally to computer systems and in particular to methods by which the principal CPU chip accesses other chips, more especially but not exclusively a separate or an external memory chip, within the system.

Background to the invention The majority of computers currently in use have a Harvard or Von Neumann architecture. Both these architectures consist, essentially, of a central processing unit with memory for data and instructions. During the execution of a program both instructions and data are fetched from memory, although instructions tend to be the more common fetch operation. Most programs will typically consist of a non branching sequence of instructions followed by a branch (eg add two numbers together and branch on the result).

Recently the architecture of integrated computer systems has split into several divisions based upon how the instructions for the computer are organised. The most important divisions are Complicated Instruction Set Computers (CISCs) and Reduced Instruction Set Computers (RISCs). Historically CISCS are older and their main characteristic is that their native instruction set is such that one instruction can perform several operations to achieve a complicated operation. This approach was satisfactory when machines were programmed at a fairly low level, but began to break down as compiler technology advanced. Under these circumstances it was noted that compilers hardly ever made use of the more complicated instructions and RISCs were introduced. RISC computers have a simple instruction set so that a compiler is able to make much better use of it.A consequence of the simpler instruction set is that more instructions are required for a given program than that required by a CISC program. This increases the rate at which instructions are fetched from memory and also increases the length of sequential instruction fetches between branches in the program.

In a highly integrated computer consisting of a CISC or RISC chip constituting the principal CPU chip and external memory, the power consumption of the whole system Is dictated by the rate at which memory is accessed and how wide the memory buses are (the number of data and address bits). It is well known that power can be reduced by integrating the computer and the memory onto the same chip. This is because power does not have to be expended changing the state of address or data bus lines. The integration of memory onto the same chip as the computer generally also means that the computer can operate faster.

The amount of memory that can be integrated onto a chip is limited and for all but the simplest applications it is necessary to store programs and data in memory that is not on the same chip as the computer (principal chip). Under these circumstances any reduction in the rate at which instructions or data are accessed in memory will reduce the power requirement. Similarly if the number of lines (wires) that have to change between different accesses is reduced then the power requirement will also be reduced.

The Invention According to one aspect of the invention, there is provided a method of accessing a separate chip from the principal CPU chip in a computer system, according to which the principal CPU chip is address line encoded so that, on the address bus and for at least one group of the address lines, the address codes are changed sequentially so that at each step only one address code is changed.

According to another aspect of the invention, there is provided a computer system having a principal CPU chip (computer) and at least one separate or external chip such as a memory chip, wherein, the principal CPU chip is address line encoded so that in use, on the address bus and for at least one group of the address lines, the address codes are changed sequentially so that at each step only one address code is changed.

In principle at least, the invention is also applicable to the accessing of data on the data bus, e.g., in a true Harvard architecture system.

Thus, in accordance with the invention, it is proposed to encode the information transmitted on the buses (collections of wires from the computer) so that the number of wires changing between accesses and the rate at which accesses are performed is reduced. The technique can be applied to both address (where the information is in memory) and data (what the information is) lines of memory. The encoding used for addresses will be different to the encoding used for data because the manner in which the lines are used is different. The technique can be applied to both standard processors and custom designed processors, in order to reduce power consumption.

Address line encoding for RISC/CISC processors is exemplified later using Gray coding, but the invention is not limited to Gray coding. Gray coding is efficient because for sequential accesses only one address line transitions between each address change.

Different encodings may be applied, and in the limit the entire range can be analysed and an optimum coding scheme for a particular program devised. In that case the coding would be highly specific and may not lead to power reduction for other programs. In general it is likely that Gray coding will give the best reduction in average power consumption.

It is important to note that the address lines of the processor are being encoded to access memory, which implies that the data must be stored in the memory at encoded addresses. If the information is put there by the processor then because Gray coding is invertible and unique it will be able to access it without modification.

However, if the program is externally supplied, by a floppy disc or card, the program must be encoded before being presented to the processor.

The invention thus also extends to the combination with the computer system of an input device and a floppy disc or other magnetic storage device bearing a program which enables the principal CPU chip to perform sequential accessing on the address or data bus as aforesaid.

It is to be noted that Gray coding is not directly possible for a standard, off the shelf, processor because unencoded address lines come from the chip. However, if the processor has some memory on chip (whether ROM, RAM or cache memory) a small program can be devised to perform the coding In this case the processor would run the instructions more slowly than the customised case.

Since programs are controlled by the programmer and are fixed, once a program has been written it can be analysed to devise a coding scheme to reduce the number of transitions in a common sequence of instructions. This form of coding will normally necessitate a small amount of on chip memory for the decoding program.

A more radical approach is to analyse a large number of programs and devise a coding scheme for the native instruction bit patterns of the processor itself, so as to reduce the number of transitions between instructions and thereby achieve the objective of the invention - ie power reduction.

As previously mentioned, data line coding could provide power reduction as well, although it requires more work than address line encoding since data is controlled by the user and therefore "random", A system in accordance with the invention is exemplified in the following further description, making reference to the accompanying drawings, in which: Figure 1 is a block diagram showing conventional computer architecture; and Figure 2 is a block diagram showing a revised architecture employing address line encoding for power saving; and Figure 3 is a block diagram showing a modification of the architecture of Figure 2.

Highly pipelined CPUs, RISC processors in particular, exhibit strong sequential (incrementing) address-line activity. Addresses are output binary coded conventionally and because the address-lines must be driven off-chip to all memory devices and some input/output peripherals (with fairly heavy capacitive loading normally), in systems where power or system noise is to be reduced, in accordance with the invention the addresses are coded to exploit the sequential characteristic in favour of reduced address line transitions over conventional binary coding.

Gray coding was devised in the late nineteenth century for use in telegraph systems. Gray coding in digital electronics design is synonymous with "reflected binary" counting. In a binary up-counter the count bit pattern is alternate O's and l's (010101010) whilst the Gray counter bit pattern has the 0 and 1 sequence then reflected the next two counts as 1 and 0 (01100110).

In this example of the invention, a fast coder is employed and a bit-reflecting Gray coding method is adopted whereby single XOR gate is used to gate every address line with the next higher address line (with the top address line left unmodified).

Example: 5-bit Address Coder A[4:0] - XA[4:0]

5-bit binary and bit-reversed Gray-coded address pattern For straight sequential address access a number is included in () brackets to indicate the number of capacitive loads that must be driven either high or low.

A net saving in loads driven is shown in [1 -brackets Binary Gray 11100 10010 11101 10011 11110 10001 11111 10000 0 0 0 0 0 (5) 0 0 0 0 0 (1) [-4] 0 0 0 0 1 (1) 0 0 0 0 1 (1) 0 0 0 1 0 (2) 0 0 0 1 1 (1) [-1] 0 0 0 1 1 (1) 0 0 0 1 0 (1) 0 0 1 0 0 (3) 0 0 1 1 0 (1) [-2] 0 0 1 0 0 (3) 0 0 1 1 0 (1) [-2] 0 0 1 0 1 (1) 0 0 1 1 1 (1) 0 0 1 1 0 (2) 0 0 1 0 1 (1) [-1] o 0 1 1 1 (1) 0 0 1 0 0 (1) 0 1 0 0 0 (4) 0 1 1 0 0 (1) [-3] 0 1 0 0 1 (1) 0 1 1 0 1 (1) 0 1 0 1 0 (2) 0 1 1 1 1 (1) [-1] o 1 0 1 1 (1) 0 1 1 1 0 (1) 0 1 1 0 0 (3) 0 1 0 1 0 (1) [-2] 0 1 1 0 1 (1) 0 1 0 1 1 (1) 0 1 1 1 0 (2) 0 1 0 0 1 (1) [-1] 0 1 1 1 1 (1) 0 1 0 0 0 (1) 1 0 0 0 0 (5) 1 1 0 0 0 (1) [-4] 1 0 0 0 1 (1) 1 1 0 0 1 (1) 1 0 0 1 0 (2) 1 1 0 1 1 (1) [-1] 1 0 0 1 1 (1) 1 1 0 1 0 (1) 1 0 1 0 0 (3) 1 1 1 1 0 (1) [-2] 1 0 1 0 1 (1) 1 1 1 1 1 (1) 1 0 1 1 0 (2) 1 1 1 0 1 (1) [-1] 1 0 1 1 1 (1) 1 1 1 0 0 (1) 1 1 0 0 0 (4) 1 0 1 0 0 (1) [-3] 1 1 0 0 1 (1) 1 0 1 0 1 (1) 1 1 0 1 0 (2) 1 0 1 1 1 (1) [-1] 1 1 0 1 1 (1) 1 0 1 1 0 (1) 1 1 1 0 0 (3) 1 0 0 1 0 (1) [-2] 1 1 1 0 1 (1) 1 0 0 1 1 (1) 1 1 1 1 0 (2) 1 0 0 0 1 (1) [-1] 1 1 1 1 1 (1) 1 0 0 0 0 (1) 0 0 0 0 0 ==== 0 0 0 0 0 ===== ===== 0 0 0 0 1 (62) 0 0 0 0 1 (=32) [=-30] 00010 00011 00011 00010 It is to be noted that in the event that sequential cycling over 32 addresses is performed the number of capacitive loads driven, is virtually half the number of straight binary accesses, with a consequent near 50% saving in address driver power.

A good application of such Gray coding of address lines is in a paged memory system. Such a system, with a page size of 256 bytes for example, benefits from the coding of the low 8 address lines before the addresses are broadcast to the memory system.

The fast Gray-coding hardware tends to generate spikes from a synchronous binary count, so in practice addresses are re-latched and driven off-chip only when a coded address is stable.

Load and Store Multiple instructions (LDM/STM) within pages, as well as executable code with sequential runs, can all benefit from a system such as that exemplified above, with the potential saving of up to one half of the address driver power.

Instructions that perform multiple accesses to sequential locations, eg the Load and Store Multiple instructions (LDM/STM) on the Acorn RISC machine (ARM), as well as executable code with sequential access runs, can all benefit from a system such as that exemplified above, with the potential saving of up to one half of the address driver power.

It is also to be noted that, as far as volatile memory such as RAM is concerned, the same addresses are always used to write and read locations, so to a program the coding scheme is transparent, but pre-programmed devices such as ROM's will require code and data to be interleaved with the same Gray coding of addresses.

Means may be provided for switching off the Gray coder on the low address bits for external I/O peripherals.

For completness, Figure 1 shows the architecture of a conventional computer system and Figure 2 shows the modified architecture of a system in accordance with the invention. Both figures are self-explanatory and will be clear without further description. It should be mentioned, however, that the system of Figure 2 will generally include a data code decoder on the data bus leading to the CPU.

Claims (12)

Claims

1. A method of accessing a separate chip from the principal CPU chip in a computer system, according to which the principal CPU chip is address line encoded so that, on the address bus and for at least one group of the address lines, the address codes are changd sequentially so that at each access step only one address code is changed.

2. A method according to claim 1, according to which the information transmitted on the data bus is also encoded so that, for at least one group of the data lines, the information codes are changed sequentially so that at each access step only one information code is changed.

3. A computer system having a principal CPU chip and at least one separate or external chip, wherein the principal CPU chip is address line encoded so that in use, on the address bus and for at least one group of the address lines, the address codes are changed sequentially so that at each access step only one address code is changed.

4. A computer system according to claim 3, wherein information transmitted on the data bus is also encoded so that, for at least one group of the information lines, the information codes are changed sequentially so that at each access step only one information code is changed.

5. A computer system according to claim 3 or claim 4, wherein the separate or external chip is a memory chip.

6. A computer system according to claim 3 or claim 4 or claim 5, in which the coding employed is Gray coding.

7. A computer system according to any of claims 3 to 6, in which the coding is optimised for a given program.

8. A computer system according to any of claims 3 to 6, in which the coding is optimised to suit the native instruction bit patterns of the processor.

9. A computer system according to any of claims 3 to 8, including an input device and a program storage device bearing a program which enables the principal CPU chip to perform sequential accessing on the address or data bus as aforesaid.

10. A computer system according to any of claims 3 to 9, in which the coding is performed by means of a coder on the address and/or data bus of the CPU chip.

11. A computer system according to any of claims 3 to 9, in which a program is entered into memory on the CPU chip to perform the coding.

12. A computer system substantially as hereinbefore described with reference to Figures 2 and 3 of the accompanying drawings.