GB2238192A

GB2238192A - An electronic switch arrangement

Info

Publication number: GB2238192A
Application number: GB8925633A
Authority: GB
Inventors: Richard John Walters
Original assignee: Individual
Current assignee: Individual
Priority date: 1989-11-13
Filing date: 1989-11-13
Publication date: 1991-05-22
Anticipated expiration: 2009-11-13
Also published as: GB8925633D0; GB2238192B

Abstract

An electronic switch arrangement including a signal input port 1, 2, a signal output port 10, a control port 17, 18 and a transmission network to which the ports are connected. The transmission network responds to the application of a switching signal to the control port by a gradual change in state which results in the transmission of a signal applied to the signal input port, with amplitude increasing gradually with time, from the signal input port to the signal output port. <IMAGE>

Description

An Electronic Switch Arranqement The present invention relates to an electronic switch arrangement especially suitable for audio signal switching.

In accordance with the invention, an electronic switch arrangement comprises a signal input port, a signal output port, a control port, and a transmission network to which the ports are connected, wherein the transmission network, in operation, responds to the application, to the control port, of a switching signal for actuating the switch arrangement, by a gradual change in state which results in the transmission of a signal applied to the signal input port, with amplitude increasing gradually with time, from the signal input port to the signal output port, the gradual change in the state of the transmission network covering a range with limits corresponding to no transmission of the signal and full transmission of the signal.

Preferably, the signal transmission network includes a switching unit connected to the signal input port, an amplifier network connected between the switching unit and the signal output port, and a control circuit connected between the control port of the switch arrangement and control terminals of the switching unit.

Preferably, the switching unit includes a first electrically controllable impedance interconnected with a second electrically controllable impedance and a plurality of resistors which, in operation, influence the current supplied to the electrically controllable impedances and the voltages developed across the electrically controllable impedances, the first electrically controllable impedance being connected, in effect in series with a terminal of the signal input port of the transmission network and the amplifier network and the second electrically controllable impedance being connected in effect, between the terminals of the signal input port of the transmission network, and the electrically controllable impedances having respective control electrodes which are the control terminals of the switch network.

Preferably, when the first electrically controllable impedance exhibits a substantially linear current-to-voltage relationship for a limited range of voltages present across itself the control circuit so operates as to restrict the operation of the first electrically controllable impedance to being within the substantially linear part of the current-tovoltage relationship.

Preferably, the control circuit so operates that when it is effecting a change in the impedance of the first controllable impedance, it maintains the first controllable impedance within the substantially linear part of its current-tc-voltage relationship by regulating the current supplied to the first controllable impedance, the current supplied to the first controllable impedance being regulated by varying the impedance of the second controllable impedance.

Preferably, when the second electrically controllable impedance exhibits a substantially linear current-to-voltage relationship for a limited range of voltages present across itself, and the control circuit so operates as to restrict operation of the second electrically controllable impedance to being within the substantially linear part of the current-tovoltage relationship.

Preferably, the first electrically controllable impedance is a junction field effect transistor, and, preferably, the second electrically controllable impedance is a junction field effect transistor.

Preferably, the control circuit generates steadily changing control voltages when a signal which includes an abrupt change is applied to the control port of the switch arrangement, and the steadily changing control voltages effect a gradual change in one electrically controllable impedance from a low to a high impedance state and a gradual change in the other electrically controllable impedance from a high to a low impedance state, the timing of the steadily changing control voltages being such that the electrically controllable impedance which is changing to its low impedance state reaching that state before the other impedance leaves its low impedance state.

Preferably, the amplifier network includes a first amplifying element connected to the switch network and a second amplifying element connected between the first amplifying element and the output port of the switch arrangement.

Preferably, the first amplifying element is such as to operate at or near its optimum signalto-noise ratio under the source conditions presented to it by the switch network, and the second amplifying network is such as to operate at or near its optimum signal-to-noise ratio under the source conditions presented to it by the first amplifying element Preferably, the amplifying elements include feedback for reducing the distortion introduced by the amplifier network into the signal transmitted by the transmission network.

Preferably, the amplifier network includes a third amplifying element connected to the second amplifying element and forming part of a d.c.

stabilising feedback network.

Preferably, the transmission network includes a control signal generator for generating a main control signal that changes gradually between an initial value and a final value in response to the application, to the control port, of a signal which includes an abrupt change, and a signal conditioning network providing, from the main control signal, a plurality of further control signals for effecting the gradual change in state of the signal transmission network.

Preferably, the signal conditioning network includes a first branch connected to a control electrode of the first electrically controllable impedance and a second branch connected to a control electrode of the second electrically controllable impedance, the signals provided by the first and second branches changing in opposite senses relative to each other to cause the electrically controllable impedances to change their impedances in opposite senses relative to each other between low and high impedance states, with the signals produced by the first and second branches being effective to cause a fall in the impedance of that electrically controllable impedance which is in the high-impedance state before there is a rise in the impedance of the electrically controllable impedance which is in the low-impedance state.

Preferably, the first electrically controll able impedance has a first control voltage threshold at which it ceases to be a high impedance, the second controllable impedance has a second control voltage threshold at which it ceases to be a high impedance, and the arrangement is such that the signals produced by the first and second branches of the signal conditioning network become equal to each other at a voltage lower in magnitude than either threshold voltage, in order to effect a change from a high to a low impedance in one of the electrically controllable impedances before there is a rise in the impedance of the other controllable impedance.

Preferably, the range of control of the signal by the transmission network has limits corresponding to an effective open-circuit condition and an effective short-circuit condition of the transmission network.

The electronic switch arrangement may include a plurality of signal input ports connected by way of a signal transmission network to respective signal output ports, and a control port connected to the signal transmission network, wherein the transmission network, in operation, responds to the application, to the control port, of a switching signal for actuating the switch arrangement, by transmitting each signal applied to a signal input port, increasingly, with time, from each signal input port to a respective signal output port, there being a gradual change from no transmission of the said signals to fill transmission of the said signals.

Preferably, the change from no transmission of the signal, or the signals, to full transmission of the signal, or the signals, occurs over a set time of at least several milliseconds, and, preferably, the set time lies within the range between several milliseconds and a few seconds.

The set time for the change from no transmission of the signal, or signals, to full transmission of the signal, or signals, may be chosen according to the required result. For example, a set time of a few milliseconds may be used where an apparently rapid change is required, whereas a set time of several seconds would be required where, for effect, a very gradual change in sound level is required.

An electronic switch arrangement, in accordance with the present invention, will now be described, by way of example only, wit reference to the accompanying drawings, in which: Fig. 1 is a circuit schematic representation of an electronic switch arrangement, in accorance with the invention, having a single signal channel.

Fig. 2 is a graphical representation of the variation, with time, of the signals applied to the control electrodes of the electrically contrcilable impedances, including the crossing points of the applied control signals, Fig. 3 is a graphical representation of the variation, with time, cf a sinusoidal signal as it is transmitted by the electronic switch arrangement of Fig. 1, including the form of the transmitted signal during twe switching phases of the electronic switch arrangement, Fig. 4 is a graphical representatIon cf are wave signals, as transmitted by the electronic switch arrangement when in the closed condition, the squarewave signals being at respective frequencies of approximately 50 KHz, 10 KHz and 1 KHz.

Referring to Fig. 1 of the accompanying drawings, the electronic switch arrangement includes a signal input port provided by terminals 1 and 2, a first Nchannel junction field effect transistor (JFET) 5 connected in series with the terminal 1, a second N-channel JFET 4 connected in shnt with the signal input port, a PNP bipolar transistor 7 having its base electrode connected to the outt port of the first JFET 4, a first amplifier 3 having an input terminal connected to the collector electrode o= the PNP transistor 7, ano a second amplifier 9 connected to the first amplifier 8.

Referring still to Fig. 1, the terminal 1 is connected to one terminal of a resistor 50, the other terminal of the resistor 50 is connected to the drain electrode of the first JFET 5, and the source electrode of the JFET is connected to the terminal 2 by way of a resistor 51. The second JFET 4 has its drain electrode connected to the drain electrode of the JFET 5 and its source electrode connected to the terminal 2. The source electrode of the JFET 5 is connected to one electrode of a capacitor 52 the other electrode of which is connected to the base electrode of the PNP transistor 7. A capacitor 53 and a resistor 54 are connected in parallel between the base electrode of the PNP transistor 7 and the terminal 2. The collector electrode of the PNP transistor 7 is connected through two resistors 47 and 48, in series, to a negative voltage supply.

A resistor 16 connects the base electrode of the transistor 7 to its collector electrode. The collector electrode of the PNP transistor 7 is connected also to an input terminal of the first amplifier 8 the output terminal of which is connected by way of a resistor 49 to an input terminal of the second amplifier 9, and the output terminal of the amplifier 9 is connected to a second input terminal of the first amplifier 8. The output terminal of the first amplifier 8 is connected also through two resistors 44 and 45 to the terminal 2 and the emitter electrode of the PNP transistor 7 is connected to the junction between the resistors 44 and 45. The amplifier 9 has a second input terminal which is connected to the terminal 2.

The input terminals of each of the amplifiers 8 and 9 are, respectively, inverting and non-inverting terminals, as found in differential-input amplifiers. The inverting input terminal of the amplifier 8 is connected to the collector electrode of the PNP transistor 7 and the inverting input terminal of the amplifier 9 is connected to the resistor 49. In addition, a capacitor 55 is connected between the inverting terminal and the output terminal of the amplifier 9, and a capacitor 56 is connected between the inverting input terminal and the output terminal of the amplifier 8. The output terminal of the amplifier 8 provides an output terminal 10 from the electronic switch arrangement.

Referring still to Fig. 1, the JFET transistors 4 and 5 are controlled through their respective gate electrodes by a control part of the electronic switch arrangement to which control part the gate electrodes of the JFETs 4 and 5 are connected by way of respective resistors 4 and 6. The control part of the electronic switch arrangement includes an input port provided by terminals 17 and 18, an N-channel enhancement-mode insulated gate field effect transistor 11 (IGFET) having its gate electrode connected to the terminal 17 by way of a resistor 19, a third amplifier 13 having an input terminal connected to the source electrode of the IGFET 11 by way of a resistor 22, a fourth amplifier 14 having an input terminal connected to the output terminal of the third amplifier 13 by way of a resistor 30, a fifth amplifier 15 having an input terminal connected to the output terminal of the third amplifier 13 by way of three diodes 28, and a sixth amplifier 16 having an input terminal connected to the output terminal of the fourth amplifier 14 by way of three diodes 35. The output terminal of the fifth amplifier 15 is connected by way of a resistor 43 to the resistor 6 which is the gate resistor of the JFET 5, and the output terminal of the sixth amplifier 16 is connected by way of a resistor 39 to the resistor 4 which is the gate resistor of the JFET 4.

Referring still to Fig. 1, and to the control part of the electronic switch arrangement, a resistor 21 and a capacitor 20 are connected in parallel between the gate electrode of te =GFET 11 and the terminal 13, and a capacitor 12 is connected between the source electrode of the IGFET 11 and the terminal 18. The third amplifier 13 has an inverting input terminal which is connected to the source electrode of the TGFET 11 by way of a resistor 22, and a reslstor 27 and a capacitor 26 are connected in parallel between the inverting input terminal and the output terminal of the third amplifier 13.The third amplifier 13 has a non-inverting input terminal which is connected to the junction of two series connected resistors 23 and 25, the resistors 23 and 25 being connected in series between a reduced positive supply voltage and the terminal 18, and the resistor 25 having a capacitor 24 connected in parallel with it. The output terminal of the third amplifier 13 is connected to the noninverting input terminal of the fifth amplifier 15 by way of a string of three diodes 23 so connected as to allow current flow from the non-inverting input terminal of the fifth amplifier 15 to towards the output terminal of the third amplifier 13. The noninverting input terminal of the fifth amplifier 15 is connected to the terminal 18 by way of a resistor 29 and is connected to the positive supply voltage by way of a resistor 40.The fifth amplifier 15 has an inverting input terminal which is connected to the terminal 18 by way of a resistor 41 and has a resistor 42 connected between its inverting input terminal and its output terminal which output terminal is connected to the gate electrode of the JFET 5 by way of a resistor 43 and the resistor 6.

Referring still to the control part of the electronic switch arrangement o Fig. 1, the output terminal of the third amplifier 13 is connected also to the inverting input terminal of the fourth amplifier 1 by way of a resistor 30 and the Inverting input terminal of the fourth amplifier 14 is connected to its output terminal by way of a resistor 34. The fourth amplifier 14 has a non-inverting terminal which is connected to the junction of two series connected resistors 31 and 33 which are connected in series between the reduced positive supply voltage and a reduced negative supply voltage, there being a capacitor 32 connected in parallel with the resistor 33.The output terminal of the fourth amplifier 14 is connected to the noninverting input terminal of the fifth amplifier 16 by way of a further string of three diodes 35 which are so connected as to allow current flow from the non-inverting input terminal of the fifth amplifier 16 towards the output terminal of the fourth amplifier 14. The non-inverting input terminal of the fifth amplifier 16 is connected also to the junction of two series connected resistors 36 and 58 which are connected in series between the reduced positive supply voltage and the terminal 18. The fifth amplifier 16 has an inverting input terminal connected by way of a resistor 38 to the terminal 18 and connected by way of a resistor 37 to its output terminal, which output terminal is connected by way of a resistor 39 and the resistor 4 to the gate electrode of the JFET 3.

Referring still to Fig. 1 of the accom.?any-na drawings, the electronic switch arrangement is provided with a positive supply voltage which is applied directly to the positive voltage supply terminals of the first, second, fifth and sixth amplifiers 15 and 16, a negative supply voltage which is applied directly to the negative voltage supply terminals of the first, second, fifth, and sixth amplifiers 15 and 16, and a reference voltage mid-way between the positive and negative supply voltages to which reference voltage the terminals 2 and 18 are connected.The positive and negative voltage supply terminals of the third amplifier 13 are connected, respectively, to the reduced positive and reduced negative supply voltages, and the positive and negative voltage supply terminals of the fourth amplifier 14 are connected, respectively,to the reduced positive and reduced negative supply voltages.

The switch arrangement represented by Fig. 1 operates as follows: The input terminals 1 and 2 are connected to a signal source that is to be controlled by the switch arrangement, the terminal 1 being connected to the "live" terminal of the signal source and the terminai 2 connected to the "ear" terminal of the signal source.

When the switch arrangement is off, the transistor 3 in its conductive state and the transistor 5 is in its non-condu=ive state, and the signal source connected ro the terminals 1 and 2 is unable tG influence the signal appearing at the output terminal 10. At the time that the transistor 3 is conductive, the signal source connected to the terminals 1 and 2 will have the resistor 50 as its load.

When the switch arrangement is on, the transistor 3 is in its non-conductive state and the transistor 5 is in its conductive state, and the signal source connected to the terminals 1 and 2 then controls the signal appearing at the output terminal 10.

When the switch arrangement s on, signals passed on by the transistors 5 are amplified by the PNP transistor 7 and the amplifier 8, the output terminal of the amplifier 8 being the output terminal 10 for the switch arrangement. The source electrode of the transistor 5, being connected to the terminal 2 by way of the resistor 51, is provided with the voltage level of the terminal 2 as its reference voltage. The signal passed on by the transistor 5 is coupled by the capacitor 52 to the base electrode of the PNP transistor 7, the resistor 54 and the capacitor 53 acting to limit the bandwidth of the signal transmitted to the PNP transistor 7.The PNP transistor 7 has an emitter load resistor 44 and collector load resistors 47 and 48, the junction of which collector load resistors is decoupled by a capacitor. The PNP transistor is provided It a collector to base feedback resistor 45, and, therefore, = gain of the amplifying stage provided by the PNP transistor 7 is set by the values of the resistors 4 & and 46. The output signal from the PNP transistor 7 is taken from its collector electrode and applied to the inverting input terminal of the differential amplifier 8, and the inverting input terminal of the differential amplifier 8 has applied to it a fed-back signal obtained from the output terminal 10 and returned by way of the resistor 49 and the differential amplifier 9. The output signal from the terminal 10 is fed back also to the emitter electrode of the PNP transistor 7 bv way of the resistor 45 having the capacitor 57 connected in parallel with it.

The differential amplifier 9 is provided with a reference voltage by virtue of having its noninverting input terminal connected to the terminal 2. The differential amplifiers 8 and 9 are provided with respective bandwidth-limiting capacitors 56 and 55.

The transistors 3 and 5 are switched on and off through control of their respective gate electrodes by the amplifiers 16 and 15, respectively, by way of the resistors 39 and 4 in the case of the transistor 3, and by way of the resistors 43 and 6 in the case of the transistor 5.

Referring still te Fig. 1, the differential amplifier 15 operates with a gain that is set partly by the resistors 1 and 42 connected to its inverting input terminal, and with an output d.c. bias that is set by the resistors 29 and 40 connected to its noninverting input terminal. An input signal for the non-inverting input terminal of the amplifier 15 is provided by the amplifier 13. The group of three diodes 28 is used to compensate for the difference in d.c. levels required between the output terminal of the amplifier 13 and the non-inverting input terminal of the amplifier 15.The amplifier 13 is a differential amplifier that operates with a gain that is set by the resistors 22 and 27 connected to its inverting input terminal with some bandwidth limiting provided by the capacitor 25. The amplifier 13 operates with an output d.c. bias set by an input d.c. bias applied, by the resistors 23 and 25, to its non-inverting input terminal.

The signal applied to the inverting terminal of the amplifier 13 is developed across the capacitor 12, that signal being controlled by the enhancement mode IGFET 11 and, ultimately, a switch such as the switch S which is a mechanical switch for switching an audio signal on and off in a piece of equipment.

Referring still to Fig. 1, the gate electrode of the enhancement mcde IGFET 11 is held at the voltage level of the terminal 18, when the switch S is open, because of the resistor 21, an the gate electrode of the IGFET is eld at some elevated voltage relative te the voltage at the terminal 15, when the switch S is ciosed, because the resistor 19 is then connected to the reduced positive supply voltage.When the switch S is closed, the IGFET 11 is switched on, and the capacitor 12 is charged to a positive voltage through the IGFET 11, the result being that the inverting input terminal of the amplifier 13 is supplied with a voltage level in excess of that supplied to its non-inverting input terminal, and the amplifier 13 therefore produces a large negative output voltage. The large negative output voltage from the amplifier 13 is passed, by the diodes 28, to the non-inverting input terminal of the amplifier 15 which produces a large negative output voltage also, the output voltage of the amplifier being effective to hold the transistor 5 in its nonconductive state.The negative output signal from the amplifier 13 is applied also to the Inverting input terminal of the amplifier 14, which has an arrangement of feedback resistors 30 and 34 generally similarly arranged to the resistors 22 and 27 connected to the amplifier 13, and biassing resistors 31 and 33 generally similarly arranged to the resistors 23 and 25 connected to the amplifier 13, that is, the overall configuration of the amplifier 14 is generally the same as the configuration of the amplifier 13. The output signal from the amplifier 14 is a positive signal which is blocked by the diodes 35 with the result that a small positive d.c. bias voltage provided by the resistors 58 and 36 to the non-inverting input terminal of the amplifier 16 drives the output of that amplifier to a set positive voltage, switching on the transistor 3.

The overall configuration of the amplifier 16 is substantially the same as that of the amplifier 15 as regards the connection of biassing and feedback resistors.

Referring still to Fig. 1, when the switch S is closed, therefore, the transistor 3 is conductive and the transistor 5 is non-conductive, the result being that a signal applied to the terminals 1 and 2 does not propagate to the terminal 10 of the switch arrangement.

When, however, the switch S is opened, the IGFET 11 ceases to conduct and the capacitor 12 discharges at a controlled rate through the resistors 22 and 27 into the output terminal of the amplifier 13.

The discharge of the capacitor 12 is communicated to the transistor 3 as a fall in its in gate voltage and the discharge of the capacitor 12 is communicated to the transistor 5 as a rise in its gate voltage, the result being that the transistor 3 ceases to conduct when its gate voltage falls below the threshold value for conduction, and the transistor 5 begins to conduct when its gate voltage rises above the threshold value for conduction. In fact, the feedback and bias resistor values for the amplifiers 13 to 16 are so chosen that the transistor 5 begins to conduct shortly before the transistor 3 ceases to conduct.

Referring still to Fig. 1, the resistor 49 has a high-value, as does the capacitor 55, which results in the combination of the resistor 49, the capacitor 55, and the amplifier 9 to ignore substantially all a.c. signals and makes it respond, in effect, only to the d.c. level at the output port 10 Because the non-inverting input terminal of the amplifier 9 is held at zero volts, the closed-loop connection of the output terminal of the amplifier 9 to the non-inverting input terminal of the amplifier 8 which, in turn, has its output terminal connected to the inverting input terminal of the amplifier 9 has the effect of driving the d.c. voltage level at the output terminal of the amplifier 8 towards zero-volts.The d.c. voltage level at the output terminal of the amplifier 8 can never be quite zero volts because the amplifier 9 is required to provide a non-zero output voltage (to match that at the collector electrode of the transistor 7).

However, the large differential gain of the amplifier 9 results in the voltage level at the output terminal of the amplifier 8 needing to be only a few millivolts to provide the required nonzero output voltage from the amplifier 9. It may be expected that the bias conditions of the transistor 7 will change with time and with temperature, resulting in changes in the d.c. voltage level at the inverting input terminal of the amplifier 8, but the resulting change in the d.c. level at the output terminal of the amplifier will be minimal because of the action of the amplifier 9. The overall effect of the amplifier 9 is to maintain the d.c. level at the output terminal of the amplifier 8 at within a few millivolts of zero volts, thereby ensuring that the outout a.c, signal is always centred on substantially zero volts d.c.

Referring still to Fig. 1, the transistor 7 is the active device of an amplifier, and the d.c.

operating conditions of the transistor 7 are established by the resistors 46, 47, 48 and 54.

The resistors 44 and 45 provide negative feedback between the output terminal 10 of the amplifier 8 and the transistor 7, the resistor 44 having a value of only a few ohms and providing mainly a.c. feedback. The resistor 46 provides localised negative feedback for the transistor 7, which feedback stabilises the gain of the amplifier for which the transistor 7 is the active device, and the resistor 46 also stabilises the d.c. bias setting of the transistor 7.

Referring still to Fig. 1, the capacitors 53, 56 and 57 are selected to provide a satisfactory square-wave response for the switch arrangement in the audio band and to define the high-frequency roll-off of that response.

Referring still to Fig. 1, the operating conditions provided for the JFET 3, the JFET 5 and the transistor 7 are such as to minimise the distortion and noise introduced, by the switch arrangement, to an audio signal that is being controlled by the switch arrangement. More specifically, the JFET 3 and the JFET 5 are operated in a manner that ensures that the JFET 5 always operates within its linear resistance state when it is passing the audio signal that is being controlled by the switch arrangement, and, also, the input network and the d.c. operating conditions for the transistor 7 are selected to minimise the noise generated by the amplifier for which the transistor 7 is the active device.

Referring still to Fig. 1, in respect of the operating conditions of the JFET 3 and the JFET 5, when the JFET 5 is fully conductive (the JFET 3 is then non-conductive), the current drawn from the audio signal source is determined by the network consisting of the resistors 50, 51 and 54, the capacitor 52, and, of course, the resistance of the signal source itself, and the values of the network components 50, 51, 54 and 52 are selected to ensure that the voltage developed across the JFET 5 by the audio current which is passing through it lies within the linear resistance range of the JFET 5.The selection of a gate voltage of 0.5. volts for holding the JFET 5 in its conductive condition ensures that it is operating well into its linear resistance region and, at the same time, its gate-source junction is not forward biassed, so no charge is being injected from the JFET gate electrode into its channel.

Referring still to Fig. 1, in respect of the operating conditions of the JFET 3 and the JFET 5, when the JFET 5 is non-conductive and the JFET 3 is fully conductive, the JFET 3 provides a very low resistance to the audio signal current drawn through the resistor 50 and, as a result, the audio signal voltage present at the drain electrode of the JFET 5 is extremely small, with the effect that substantially none of the audio signal is available for transmission by the JFET 5 which, although in a high-impedance state is not a perfect open-circuit.The gate electrode of the JFET 3 is maintained at 0.5 volts, while it is fully conductive, in order to meet the requirements that the JFET 3 should be in a highly conductive state but that there should be no charges injected from its gate electrode into its channel electrode, so as to ensure that there will be a smooth transistion to its non-conductive state, when that transistion is required.

Referring still to Fig. 1, in respect of the operating conditions of the JFET 3 and the JFET 5 when the JFET 3 is being returned to its non-conductive state and the JFET 5 is being placed in its conductive state, an effect of ensuring that the JFET 3 remains conductive but with a steadily increasing resistance), during the time before the JFET 5 becomes fully conductive, is that the audio signal current being rejected by the JFET 3, and being accepted by the JFET 5, is being transferred at a rate which does not take the JFET 5 outside its linear resistance region.In a similar manner, when the JFET 5 is being returned to its non-conductive state and the JFET 3 is being placed in its conductive state, the current being progressively rejected by the JFET 5 is being accepted by the JFET 3 at a rate which keeps the drain-source voltage of the JFET 5 within the linearresistance region of the device characteristic.

Therefore, the switch arrangement maintains minimumdistortion conditions for the JFET 5 during the switching phase of the operation.

Referring still to Fig. 1, the noise contribution of the transistor 7 to the overall system noise depends on the source resistance presented to the transistor, during its operation, in relation to its parameters. The source resistance presented to the transistor 7 changes with the operational states of the JFETS 3 and 5, having its lowest value during the switching phase when the JFETS are both partly conductive and its highest value when the JFET 5 is non-conductive, that value being substanially equal to the effective resistance of the resistors 51 and 54 connected in parallel with each other (the impedance of the capacitor 52 being treated as negligible over the relevant frequency range).The source resistance presented to the transistor 7 when the JFET 5 is fully conductive is an intermediate value and amounts to the effective resistance of the resistors 51 and 54 connected in parallel with each other and having the resistor 50 and the audio signal source resistance as a further parallel limb of a source resistance network. It is known that a transistor contributes least noise when presented with a source resistance Rsopt determined by the the equation Rs,opt = + 2 rb where gm and rb are the conventional hybrid-pi parameter symbols and hf is the d.c. current gain for the transistor being used.For low-noise operation of the transistor 7 the values of the resistors 50, 51 and 54 are chosen to make their effective resistance when connected together, in parallel, about the same as R5,opt for the transistor 7, but, of course, final adjustments may be made on test. In addition, it is known that transistor low-noise operation is collector-current dependent O25(hf) according to the equation Ic,opt = Rs where Rs is the effective source resistance presented to the transistor, and the operating point of the transistor 7 is selected to make Ic as near Ic,opt as is possible.

Referring still to Fig. 1, a further aspect of the switch arrangement is that the Inverting input terminal of the amplifier 8, by virtue of its connection to the collector electrode of the transistor 7, is presented with a substantially constant source resistance despite the variations in the effective source resistance presented to the transistor 7.

The shielding, or buffering effect of the transistor 7 on the amplifier 8 ensures that the amplifier 8 is not presented with a source resistance which would result in its contributing significantly to the overall system noise. A condition where, in the absence of the transistor 7, the amplifier 8 would be expected to make a significant noise constribution is that of the JFETS 3 and 5 both being in their intermediate-resistance states during the switching phase of the operation of the switch arrangement.

The switch arrangement is best realised by the use of high-accuracy resistors (2%, for example) and provides substantially unity gain, to an audio signal, from input to output. In practice, gain of the order of 40dB is required from the active devices to compensate for the attenuation suffered by the signal in the input network of the switch arrangements.

The absence of feedback components connected between the drain and gate electrodes of the JFETS 3 and 5 should be noted.

The performance of the switch arrangement may be summarised as follows: Available headroom on +15 0 -15 volts supply s +21dBu Freq Response flat from 10Hz to 85Khz In ( OdBu ) -3dB &commat; 300Khz =(+ 20dBu) -3dB &commat; @ 150Xhz 150Khz Square Wave response (see Fig4) Distortion In - OdBu - + 20dBu

30 Hz { lKhz | 20Khz 30 Hz 1 1Khz 20Khz 0.004 % 0.003 % 1 0.001 8 0.006 % I 0.002 % 0.002 % Noise Performance (measured Audio B/W) = -90 dBu Extraneous Noises (including glitches from switch operation) measured at -90dBu level with 30Khz L.P filter in only.

meter rectifier set P.P.M. - none.

Isolation Performance measured with 80Khz L.P filter in.

In - OdBu

1Khz 20Khz 1 50Khz -90 dBu ss -9OdBu -80dBu Timing Cap range 22uF = -omS equal exponential rise 100uF = 25mS and fall 470uF = 125mS Circuit non-inverts Input impedance = 5.6 Kohm Output load not to be less than SKohm The specifications for a stereo and a balanced version are similar in most respects.

Referring to Fig. 2 of the accompanying drawings, showing the variation, with time, of the gate voltages of the transistors 3 and 5, the curve A represents the variation of the gate voltage of the transistor 5 as its gate voltage rises from below cut-off to above cut-off, and the curve B represents the variation of the gate voltage of the transistor 3 as its gate voltage falls from above cut-off to below cut-off, using a first value of the capacitor 12 in the circuit represented by Fig. 1. If it is assumed that the cut-off voltages of the transistors are the aame, at about -4 volts, the transistor 5 will begin to conduct at the time corresponding to the point A1 while the transistor 3 will cease to conduct at the time B1.If the value of the capacitor 12 is reduced, the curves C and D are obtained for the gate voltage variation of the transistors 5 and 3, respectively, but it is still noted that the transistor 5 conducts from the time corresponding to the point C1, and the transistor 3 ceases conduction at the time corresponding to the point D1. Also, it is to be noted that the cross-over point E remains uneffected by the value of the capacitor 12, that point being determined by the biassing and feedback resistors values selected for the amplifiers 13 to 16.In general, the cut-off voltages for the transistors 3 and 5 may not be the same, but so long as the voltage at the point E is selected to lie above the highest cut-off voltage likely to be encountered among the transistors selected (the least negative being regarded as the highest and the most negative as the lowest) then the transistor 5 can be caused to conduct before the transisor 3 ceases conduction.

Referring still to Fig. 2 of the accompanying drawings, it will be noted that the limits of the voltages applied to the gate electrodes of the transistors 3 and 5 are about 0.5 volts positive and about 13 volts negative. A voltage of 0.5 volts positive applied to the gate electrode of the transistor 3, or the transistor 5 (of Fig. 1), will, of course, cause the transistor to be driven well into conduction, while a gate voltage of 13 volts negative ensures that the transistors are truly non-conductive. The limits of the voltages applied to the gate electrodes of the transistors 3 and 5 are, of course, set by the amplifiers 15 and 16, of Fig. 1.

Referring to Fig. 3 of the accompanying drawings, the build-up of the audio signal is gradual and there are no discernible "thumps" or "clicks" normally associated with the switching-on of an audio signal. The switching-off is also gradual and, again, "thumps" and "clicks are not generated.

Referring to Fig. 4 of the accompanying drawings, output signals at 50 KHz(REF 1), 10 KHz (REF 2), and 1 KHz(REF 3) obtained at the terminal 10 of the circuit represented by Fig. 1 are shown, for input square wave signals at 50 KHz, 10 KHz, and 1 KHz, respectively. It will be noted, from the output signals shown, that the switch arrangement does not introduce any significant distortion of the input signal.

Returning to the circuit represented by Fig. 1, distortion of the signal is minimised by performing the switching operation at low level, that is, with no amplification of the signal applied to the terminals 1 and 2 prior to performing the switching operation by the transistors 3 and 5. Further, the transistor 7 has localised feedback provided by the resistor 46, and the transistor 7 and the amplifier 8 are included in a feedback loop because of the resistor 45, thereby minimising any distortion produced by the transistor 7 and the amplifier 8. In addition, the amplifier 9 and the capacitor 55 provide additional feedback at high frequencies that is effective to block audio frequency signals.

Referring again to Fig. 1 of the accompanying drawings, the electronic switch assembly may include additional signal channels, each requiring an additional set of components corresponding to the active elements 3,5,7,8, and 9, and their associated passive elements, connected to respective signal input and signal output ports, but controlled by the same control signals as those applied to the active elements 3 and 5.

Electronic switch arrangements, in accordance with the invention, may be used in domestic audio equipment for the purpose of avoiding unpleasant or undesirable effects caused by mechanical switch operation, which is abrupt, but may be used also in professional audio equipment not only to avoid switching transients, but, also, to provide preset rates of increase and decrease, of sound level in particular situations.

Referring again to Fig. 1, subjective listening tests resulted in the value of the resistor 51 being selected as 51 ohms. Other component values, also arrived at following subjective listening tests, are as follows: Component reference numeral Value 4,6 10 M ohms 44 3.3 ohms 46 51 K ohms 47 2.2 K ohms 48 680 ohms 50 5.1 K ohms 54 10 K ohms 52 47AF 53 10*F

Claims

CLAIMS: 1. An electronic switch arrangement comprising a signal input port, a signal output port, a control port, and a transmission network to which the ports are connected, wherein the transmission network, in operation, responds to the application, to the control port, of a switching signal for actuating the switch arrangement, by a gradual change in state which results in the transmission of a signal applied to the signal input port, with amplitude increasing gradually, with time, from the signal input port to the signal output port, the gradual change in the state of the transmission network covering a range with limits corresponding to no transmission of the signal and full transmission of the signal.
2. An electronic switch arrangement as claimed in claim 1, wherein the signal transmission network includes a switching unit connected to the signal input port, an amplifier network connected between the switching unit and the signal output port, and a control circuit connected between the control port of the switch arrangement and control terminals of the switching unit.
3. An electronic switch arrangement as claimed in claim 2, wherein the switching unit includes a first electrically controllable impedance interconnected with a second electrically controllable impedance and a plurality of resistors which, in operation, influence the currents supplied to the electrically controllable impedances and the voltages developed across the electrically controllable impedances, the first electrically controllable impedance being connected in effect in series with a terminal of the signal input port of the transmission network and the amplifier network and the second electrically controllable impedance being connected, in effect between the terminals of the signal input port of the transmission network, and the electrically controllable impedances having respective control electrodes which are the control terminals of the switch network.
4. An electronic switch arrangement as claimed in claim 3, wherein the first electrically controllable impedance exhibits a substantially linear current-tovoltage relationship for a limited range of voltages present across itself and the control circuit so operates as to restrict the operation of the first electrically controllable impedance to being within the substantially linear part of the current-tovoltage relationship.
5. An electronic switch arrangement as claimed in claim 4, wherein the control circuit so operates that when it is effecting a change in the impedance of the first controllable impedance, it maintains the first controllable impedance within the substantially linear part of its current-to-voltage relationship by regulating the current supplied to the first controllable impedance, the current supplied to the first controllable impedance being regulated by varying the impedance of the second controllable impendance.
6. An electronic switch arrangement as claimed in any one of claims 3 to 5, wherein the second electrically controllable impedance exhibits a substantially linear current-to-voltage relationship for limited range of voltages present across itself and the control circuit so operates as to restrict operation of the second electrically controllable impedance to being within the substantially linear part of the current-to-voltage relationship.
7. An electronic switch arrangement as claimed in any one of claims 3 to 6, wherein the first electrically controllable impedance is a junction field effect transistor.
8. An electronic switch arrangement as claimed in any one of claims 3 to 7, wherein the second electrically controllable impedance is a junction field effect transistor.
9. An electronic switch arrangement as claimed in any one of claims 2 to 8, wherein the control circuit generates steadily changing control voltages when a signal which includes an abrupt change is applied to the control port of the switch arrangement, and the steadily changing control voltages effect a gradual change in one electrically controllable impedance from a low to a high impedance state and a gradual change in the other electrically controllable impedance from a high to a low impedance state,the timing of the steadily changing control voltages being such that the electrically controllable impedance which is changing to its low impedance state reaching that state before the other impedance leaves its low impedance state.
10. An electronic switch arrangement as claimed in any one of claims 2 to 9 wherein the amplifier network includes a first amplifying element connected to the switch network and a second amplifying element connected between the first amplifying element and the output port of the switch arrangement.
11. An electronic switch arrangement as claimed in claim 10, wherein the first amplifying element is such as to operate at or near its optimum signal-tonoise ratio under the source conditions presented to it by the switch network, and the second amplifying network is such as to operate at or near its optimum signal-to-noise ratio under the source conditions presented to it by the first amplifying elements.
12. An electronic switch arrangement as claimed in claim 10 or 11, wherein the amplifying elements include feedback for reducing the distortion introduced by the amplifier network into the signal transmitted by the transmission network.
13. An electronic switch arrangement as claimed in any one of claims 10 to 12, wherein the amplifier network includes a third amplifying element connected to the second amplifying element and forming part of a d.c. stabilising feedback network.
14. An electronic switch arrangement as claimed in any one of claims 1 to 13, wherein the transmission network includes control signal generator for generating a main control signal that changes gradually between an initial value and a final value in response to the application, to the control port, of a signal which includes an abrupt change, and a signal conditioning network providing, from the main control signal, a plurality of further control signals for effecting the gradual change in state of the signal transmission network.
15. An electronic switch arrangement as claimed in claim 14, when dependent on any one of claims 3 to 11, wherein the signal conditioning network includes a first branch connected to a control electrode of the first electrically controllable impedance and a second branch connected to a control electrode of the second electrically controllable impedance, the signals provided by the first and second branches changing in opposite senses relative to each other to cause the electrically controllable impedances to change their impedances in opposite senses relative to each other between low and high impedance states, with the signals produced by the first and second branches being effective to cause a fall in the impedance of that electrically controllable impedance which is in the high-impedance state before there is a rise in the impedance of the electrically controllable impedance which is in the low-impedance state.
16. An electronic switch as claimed in claim 15, wherein the first electrically controllable impedance has a first control voltage threshold at which it ceases to be a high impedance, the second controllable impedance has a second control voltage threshold at which it ceases to be a high impedance, and the arrangement is such that the signals produced by the first and second branches of the signal conditioning network become equal to each other at a voltage lower in magnitude than either threshold voltage, in order to effect a change from a high to a low impedance in one of the electrically controllable impedances before there is a rise in the impedance of the other controllable impedance.
17. An electronic switch arrangement as claimed in any one of claims 1 to 6, wherein the range of control of the signal by the transmission network has limits corresponding to an effective open-circuit condition and an effective short-circuit condition of the transmission network.
18. An electronic switch arrangement substantially as herein described with reference to, and as illustrated by, Fig. 1 of the accompanying drawings.
19. An electronic switch arrangement including a plurality of signal input ports connected by way of a signal transmission network to respective signal output ports, and a control port connected to the signal transmission network, wherein the transmission network, in operation, responds to the application,to the control port, of a switching signal for actuating the switch arrangement, by transmitting each signal applied to a signal input port, increasingly, with time, from each signal input port to a respective signal output port, there being a gradual change from no transmission of the said signals to full transmission of the said signals.
20. An electronic switch arrangement as claimed in any one of claims 1 to 19, wherein the change from no transmission of the signal, or the signals, to full tranmission of the signal, or the signals, occurs over a set time of at least several milliseconds.
21. An electronic switch arrangement as claimed in claim 20, wherein the set time lies within the range between several milliseconds and a few seconds.