GB2238189A - P W M inverter - Google Patents

Abstract

Control is provided for prevention of a short circuit between controllable elements used as switching elements in a pulse-width modulation (PWM) inverter 20 which outputs a variable a.c. voltage or an a.c. indicative of a variable frequency. A reference signal generator 40a, associated with zero level current detected by an output current detector 90, supplies a sinewave to a PWM generator 60a which controls the inverter 20. A selecting means (80, Figs 14 and 15) selects an output within a period during which the result of detection by the current detector 90, falls within a region of substantially zero level and also selects only a signal corresponding to each switching element which effectively acts on the generation of the output current, cut of signals generated by a PWM signal generator 60 during a period other than the above-described period, thereby to output the same as a drive signal for the switching element. The current detector 90 is used to determine the polarity of the output and the control ensures that only the switching elements providing the correct polarity output are allowed to be driven. <IMAGE>

Description

PULSE-WIDTH MODULATION TYPE INVERTER APPARATUS The present invention relates to a pulse-width modulation type inverter apparatus for outputting a variable a.c. voltage or variable a.c. frequency, and particularly to ar, improvement in the control for prevention of a short circuit between controllable elements used as switching elements.

2) Description of the Related Art: Ff0. 16 Is a block diagram shewing the ccnstruction of a conventional pulse-width modulation type inverter apratus (hereinafer called "PWM type inverter"). In the sare drawing, designated at numeral 10 is a d.c. rower supply and numeral 20 indicates a power inverter composed of controllable elements as switching ee.-ents and diodes connected to each other in antiparallel form, said inverter being adapted to covert a d.c. voltage fed fre the d.c. power supply 10 into a variable a.c. voltage or variable a.c. frequency (for the brevity of description, electrical symbols representative of only a single phase are shown here). Numeral 30 indicates an electric motor which is to be driven by the PWM type inverter.

DesIgnated at numeral 40 is a reference voltage gener ator corresponding to a reference signal generating means for outputting waveforms indicative of reference voltages, i.e., reference-voltage waveforms as references of output frequencies or output voltages.

Numeral 50 indicates a carrier generator for generating a carrier waveform indicative of a frequency fc with waveforms indicative of triangular waves or the like so as to output the same therefrom. Numeral 60 indicates a PWM circuit for generating each striking signal (PhE signal) for each controllable element provided in the power inverter 2G based on signals from the reference voltage generator 40 and the carrier generator 50.Designated at numeral 65 is a processing means for generatIng each PWM signal by which a short-prevention period Td is established, based on each signal from the PY circuit 60 with a view toward preventing a short circuit between under and lower controllable efts corresponding to each phase designated by the power inverter 20. Numeral 70 indicates a drive circuit for driving each ccntrollable element provided in the power inverter in response to each signal from the processing means 65.

A description will now be made on the operation of the abcve apparatus. FIG. 18 is a graphic representation of the shapes of waves that typically indicate a PWM operation of this type of PW' type inverter, e.g., FIG. 18 is waveforms for describing the operation of a single U phase employed in the PWM type inverter, out of three phases of U, V and W. As shown in FIG. 17, the reference voltage as a reference of an output voltage or output frequency from the inverter is compared with a signal for modulating the same, e.g., a signal indicative of a carrier waveform as a triangular wave.A period during which the reference voltage is larger than a voltage indicative of the carrer wavefroit is brought into an on state, while a period during which the referee voltage is smaller than the voltage indicative of the carrier waveform is brought into an off state, thereby making it possible to obtain time result, as a p signal UpO for the upper-side controllable element corresponding to the U phase.A PWM signal UNO for the lower-side controllable element, which corresponds to the U phase, is determined as an invert signal indicative of the PWN signal Up. In order to prevent the upper-side and lower-sIde controllable elements from being short c.rca.ted, each controllable element is actually driver by a short-prevention processed PWM signals Up, UN for delaying on-timing by a time interval corresponding to the short-prevention period Td. As a result, an output voltage corresponding to the U phase is pulse-width modulated in the form of a sine wave, thereby obtaining an output voltage waveform shown in FIG. 18(d).Incidentally, each of output voltages corresponding to V and W phases can be obtained in the above-described manner. A potential shown in FIG.

18(d) represents one corresponding to an imaginary neutral point on a d.c. side.

The above-described reference voltage waveform and carrier waveform are shown in FIG. 18(a). The PhE signals UpO and UNO are depicted in FIG. 18(b) and the output voltage is illustrated in FIG. 18(d). Referring to FIG. 16, the reference voltage generator 40 serves to output a reference voltage waveform shown in FIG. 18(a). The carrier generator 50 serves to generate a carrier waveform in the form of a triangular wave depicted in FIG. 18(a) and the PWM circuit 60 serves to generate a P signal illustrated in FIG.

18(b). n addition, the processing means 65 serves to generate a short-prevention processed PWM signal depicted in FIG. 18(c) and the drive circuit 70 ac titles controllable elements provided in the power inverter 2C using a Prm.r signal subsequent to a shortprevention processing b the processing means 65. The Pw inverter can bring about a variable a.c. voltage or variable a.c. frequency in the above-described manner.

Meanwhile, the influence of the short-prevention period Td on the output voltage will occur as shown in FIGS. 19 and 20. Its influence differs depending on polarity of the output current. When the polarity of the output current is positive, the output voltage is outputted at a value lower than the reference voltage during the short-prevention period Td. When the polarity of the output current is negative on the other hand, the output voltage is outputted at a value higher than the reference voltage. Thus, the output voltage is affected by the polarity period of the output current, thereby causing distortion represented by VUN in FIG. 20 owing to an ideal sine wave obtained by the referent PWY signal.In addition, the manner of occurrence of distortion in the output voltage is also shown in FIG. 18(e) as distortion (error) which appears in association with the current polarity. Here, VU-01 0-0 0 each represent a potential in the case where an iraglnary neutral point on the d.c. side is considered as a reference.

In other words, an error will occur in a reference voltage sIgnal by the short-prevention period Td. This error is undesIrable because of the distortion of the output voltage, the reduction in the output voltage and an increase in torque ripples.

A description will next be made on the PWM type inverter which has been proposed for the purpose of solution of such incovenience.

FIG. 21 is a block diagram showing the construction of the conventional PM type inverter which has been disclosed in Japanese Patent Laid-Open No. 60 207494. In the same drawing, designated at numeral 55 is a potential detector for detecting the level of each logic output voltage corresponding to each phase.

Numeral 60a indicates a PhE circuit as a Pew'A signal generating means for generating each striking signal (PWM signal) for each controllable element provided in a power inverter 20, based on signals from a refeference voltage generator 40 and a carrier generator 50 and a signal from the potential detector 55.

Incidentally, in the sane drawing, the same elements of structure as those shown in FIG. 16 are identified by like reference numerals and its description will therefore be omitted. A description will hereinafter be made on the operation of correction of the 1n- fluence of the short-prevention period Td on the output voltage. In the conventional example shown in FIG. 21, the potential detector 55 for detecting the level of the logic output voltage corresponding to each phase is provided in order tc solve the above described inconvenience as shown in FIG. 21.Then, the output signal from the potential detector 55 is compared with the reference PeM signal [e.g., UpO, UNO shown in FIG. 18(b)) prior to the short-prevention processing, so that the difference between the voltages corresponding to the signals referred to above is corrected successively.

FIG. 22 is a circuit diagram showing the poten tial detector in detail, and shows an output unit of the PEE. type inverter, corresponding to the U phase.

A resistor 15 and a photocoupler 16 are interposed between a U phase output terrinal and a d.c. bus N.

When the potential corresponding to the U phase is applied to a d.c. bus P, i.e., the potential is brought into P level, the photocoupler 16 is made conductive, so that a detection signal PC is brought into H level.

On the other hand, when the potential corresponding to the U phase is in the level of the d.c. bus N, the pbotocoupler 15 is .aqe nonconductive, so that the detection siganl PC is brought into L level. In the above-described nanner, the logic level of the actual output voltage is detected, thereby to output the result of detection to time r;Cz circuit 60a. Inciden tally, the operations of V and h phases are also the sare as that in the above-described embodiment and their cescriptlon will therefore be omitted.

A description will next be made on the operation of the potential detector in cotbination with FIG. 23.

For exarple, a reference singal representative of a UpO is compared with a detection signal PC indicative of a potential corresponding to the U phase from the potential detector 55 and errors corresponding to time delays of the change timing from, e.g., L level to H level are accumulated by a counter or the like. When a tie delay is made by the time corresponding to the above-accunulated errors during a period of the next change timing from H level to L level and a command is given by the reference signal v-pO, the time interval indicative of H level is secured only during the same period (the time interval indicative of L level is also secured similarly to the time interval indicative of H level), whereby the error correction is performed so as to obtain a given output voltage.As shown in FIG. 23, the graphic representation of the shapes of waves that indicate the operational characteristics about the error correction includes only a shortprevention period Td and a time delay Ts representative of an off state of a main circuit element, and other delay elements are not included therein. In the drawing, a UDLY corresponds te a Phw signal subsequent to the correction of the signal UpO, and a PC corresponds to a signal obtained by detecting the result of operation cf elements by the short-prevention processed F ,' signal Up from the signal IDLY. In addition, CU represents the result of integration or counting of errors in signal between the reference signal and the detection signal.

In the drawing, it is practiced to correct, for example, a time delay indicative of the change timing from L level to H level, which has been stored as data about the time interval between t2 and tl, by delaying the next change timing from H level to L level by a time of transition from t3 to t4.

6a and 6b represent the state of striking of arc (H level) and extinction of arc (L level) of the upper- and lower-side controllable elements corresponding to the U phase, which are shown in FIG. 22, respectively.

As an alternative to the above-described method, there has been propcsed a PhE type inverter for controlling the influence of the short-prevention period Td on the output voltage.

FIG. 24 is a block diagram showing the construction of the conventional another PM, type inverter.

In the drawing, designated at numeral 90 is a current detector for detecting output current from the inverter. Numeral lOG indicates a polarity doscri"inat- ing means which is responsive to an ouput signal from the current detector 9G for jugging wimether or not the polarity of output current corresponding te each phase erployed in the inverter is positive or negative.

Designated at numeral 40c is a reference voltage generator for outputting each reference voltage wavefcrm as a criterion of an output frequency or output voltage, and is responsive to an output signal from the polarity discriminating means 100 so as to output each reference voltage waveform for correcting each waveform of signals corresponding to preestimated errors such that the output voltage from the inverter becomes the reference voltage. Numeral 60 indicates a PWM circuit for generating each striking signal (PWM signal) for each controllable element provided in a power inverter 20, based on output signals from the reference voltage generator 40c and a carrier generator 50.

Incidentally, in the same drawing, the sa..,e elements of structure as those shown in FIG. 21 are identified by lie reference numerals and their description will therefore be omitted.

A description will next be made on the operation of the inverter referred to above. In this PhE type inverter, as shown in FIG. 24, the current detector 90 and the polarity dssscri."inating reans 100 are provided in place of the potential detector 55. It is practiced in this unit to judge whether or not the polarity of output current corresponding to each phase is positive or negative and correct each reference voltage waveform according to the polarity of the output current in the direction in which output current affected by the short-prevention period Td is cancelled.

FIG. 25 is waveforms for describing the operation for the correction of each reference voltage waveform according to the polarity of the output current. FIG. 25 depicts each waveform for describing the operation of correction of the reference voltage waveform corresponding to a U phase alone out of three phases, in an illustrative example representing the case where three-arz, control of a type wherein the three phases are always subjected to switching during each cycle period of each of the carrier waveforms shown in FIGS. 18, 1 and 20, is performed.

FIG. 25(a) shows a reference voltage waveform and FIG. 25(b) depicts an output current waveform.

FIG. 25(c) is a waveform obtained by replacing the level of a voltage AV corresponding to distortion of an output voltage waveform affected by the shortprevent ion period Td by the level of the reference voitage waveform. FIG. 25(d) is a waveform representing a polarity dis~rininating signal S2 as output current and FIG. 25(e) is a waveform representing the level of a voltage for correcting the reference voltage waveform in the direction in which the level of the voltage AV corresponding to the distortion of the output voltage waveforn. In addition, FIG. 25(f) depicts a phase voltage waveform corresponding to the U phase, having distortion corpcnents caused by the influence of the short-prevention period Td on the output voltage and indicated by the solid line, with respect to a target voltage indicated by the broken line (in practice, FIG. 25(f) shows a PWM waveform, which is in turn represented by analog values for the brevity of description).

As has been described in the article entitled "Short-Prevention Period Regarding Upper and Lower Arms Employed In FE Inverter" published at the meet- ing of the Association of Tokai Branch sponsored by the Institute of Electrical Engineering, in 1982 (Showa 57 nendo Denki Gakkai Tokaishibu Rengotaikai), the voltage AV corresponding to the distortion of the output voltage waveform is established by the following expression: # V#fc . Td where fc = carrier frequency Td = short-prevention period Let's now assume that such output current IU as shown in FIG. 25(b) flows in a state In which an electric motor 30 has been driven by the inverter.At this time, the current detector 90 serves to detect the above-descrIed output current ',Q, and the polarity discririnating means 100 supplies a polarity discriminating signal S2 shown in FIG. 25(d) to the reference voltage generator 4Ce based cn the signal detected by the current detector 90.Then, the reference voltage generator 40c is responsive to the polarity discriminating signal S2 for generating a correction signal in the direction in which the influence of the short-prevention period Td on the output voltage, i.e., the voltage AV corresponding to the distortion of the output voltage waveform shown in FIG. 25(c) is cancelled, and for adding the generated signal to the reference voltage waveform depicted in FIG. 25(a) so as to supply the result of addition to the PeE circuit 60. In the above-described manner, the reference voltage waveform is corrected and PWMcalculated in such a way that the influence of the short-prevention period Td is cancelled in advance according to the polarity of the output current for obtanning an output voltage.Thus, such distortion as indicated by the solid line in FIG. 25(f) is controlled, thereby obtaining such an output voltage waveform as indicated by the broken line.

The conventional pu'se-width rodulation type inverter apparatus is constructed as described above.

ere the short-prevention period Td is established by the processing earns 65 so as to avoid a short circuit between the controllable elements, the short prevention period Td exert a bad influence upon the output voltage. In addition, where the potential detector 55 detects a voltage at each of junction points between the controllable elements of the arms and the influence of the short-prevention period Td on the output voltage is corrected by the PWM circuit 60 based on the detected voltage, the logic level of the output voltage to be generated by the potential detector 55 is not established in a region in which the output current is rendered minimum. It is thus im possible to correct the influence of the shortprevent ion period Td caused by the logic correction.

Furthermore, where a judbesl.ent is made by the polarity discriminating means 100 as to whether or not the polarity of the output current detected by the current detector 90 is positive or negative and a correction signal corresponding to the discriminating signal S2 is generated by the reference signal generator 40c, and the voltage corresponding to the correction signal is added to the reference voltage, thereby correcting the influence of the short-prevention period Td on the output voltage, a limitation is imposed on the accuracy in disorirination of the polarity discriminat- ing rears 100 in zero level region of output current, in which the polarity of the output current is changed from positive to negative or vice versa, thereby causing difficulty In discrimination of the polarity with high accuracy. The influence of the short-prevention period Td on the output voltage appears remarkably in the vicinity of changeover in the polarity of the ouptut current and hence the period during which the output current is stayed in the vicinity of the zero level is rendered long. As a result, a period representative of the result of the polarity discrimination of positive or negative is rendered unbalanced in correlation with the limitation of accuracy in the polarity discrimination.In addition, detection er rors occur in each point at which the above polarity is to be changed, and hence the influence of the short-prevention period Td on the output voltage cannot be corrected, thereby causing a problem to be solved by the invention, that the distortion in the output voltage, the reduction in the output voltage, the torque ripples, the irregularity in rotation, etc.

is produced.

With the foregoing problems in view, it is therefore an object of this invention to provide a pulse-^id'h modulation type inverter apparatus which can control the Influence on output current by short prevention processIng between switching elents and also sufficiently correct each output voltage waveform even within a region in which the output current is rendered mini.uz, thereby causing no distortion in voltage, reduction in voltage, tcrque ripples, irregularity in rotation, etc., an bringing about high stability.

According to a first embodiment of this invention, there is provided a pulse-width modulation type inverter apparatus, which comprises an inverter unit composed of arms connected in the form of three-phase bridge, the arms including a pair of switching elements which are connected in series and on/off con trolled in a complementary form, a current detector for detecting output current from the inverter unit, phE signal generating means for generating each of pulse-width modulation signals for controlling each of the switching elements, processing means for subjecting each signal generated by the PhE signal generating means to processing for preventing a short circuit between the pair of switching elements, and means for selecting each signal generated by the processing mean within a period during which current detected by the current detector falls within substantially zero level and for selecting only a signal corresponding to each switching element which effectIvely acts on the generratio of the output current, out of signals generated by the r;X3.' signal generating means, thereby to output the same as a drive signal for each switching element.

According to a second ebssiiment of this invention, there is provided a pulse-width modulation type inverter apparatus, which comorises an inverter unit composed of arms connected in the form of three-phase bridge, the ars including a pair of switching elements which are connected in series and on/off controlled in a coitplementary form, a current detector for detecting output current from the inverter unit, PWM signal generating means for generating each of pulse-width modulation signals for controlling each of the switching elements, processing means for subject ing each signal generated by the PWM signal generating means to processing for preventing a short circuit between the pair of switching elements, and reference signal generating means for saturating a region corresponding to r/3(rad) at the maximum during a half cycle of each output voltage waveform corresponding to a desired phase, in association with a region of substantially zero level of current detected by the the current detector thereby to perform two-arm modulation of the remaining phases and for generating each reference signal for outputting each output voltage in the form of a substantially sine wave thereby to supply the same to the P6 signal generating means.

According to a third embodiment of this invention, there is provided a pulse-width modulation type inverter apparatus, which comprises an inverter unit cor rosed of arms connected in the form of three-phase bridge, time ars including a pair of switching elerents whIch are connected in series and on/off con trclled In a cotrplementary form, a current detector for detecting output current from the inverter unit, pnv signal generating means for generating each of pulse-width modulation signals for controlling each of the switching elements, reference signal generating means for saturating a region corresponding to o/3(rad) at the maximum during a half cycle of each output voltage waveform corresponding to a desired phase, in association with a region of substantially zero level of current detected by the current detector, thereby to perform two-arm modulation of the retaining phases and for generating each reference signal for outputting each output voltage in the form of a substantially sine wave, thereby to supply the same to the P'nM signal generating means, and means for selecting, based each output signal from the current detector, only a signal corresponding to each switching element which effectIvely acts on the generation of the output current, out of signals generated by the PWY signal generating means, thereby to output the same as a drive signal for each switching element.

According to a fourth embodiment of this invention, there is provIded a pulse-width modulation type inverter apparatus, which comprises an inverter unit ocr osed of arms connected in the form of three-phase bridge, the arms including a pair of switching elerents which are connected in series and onjoif con- trolled in a complementary form, a current detector for detecting output current from the inverter unit, ShE signal generating means for generating each of pulse-width modulation signals for controlling each of the switching elements, processing means for subjecting each signal generated by the PWE signal generating means to processing for preventing a short circuit between the pair of switching elements, reference signal generating means for saturating a region corresponding to #/3(rad) at the maximum during a half cycle of each output voltage waveform corresponding to a desired phase, in associaticn with a region of substantially zero level of current detected by the current detector, thereby to perform two-arm modulation of the remaining phases and for generating each reference signal for outputting each output voltage in the form of a substantially sine wave, thereby to supply the same to the PhE signal generating means, means for selecting each signal generated by time processing mean within a period during which current detected by the current detector falls with In substantially zero level and for selecting only a signal ccrrespcnAing to each switching element which effe:tlvely aets on the generat ion of the output current, out of signals generated by the p;s, signal generating ncns, thereby to output the s3m.e as a drove signal for each switching element.

The above and other objectes, features and advantages of the present invention will become apparent from the following description and the appended claims, taken in conjunction with the accompanying drawings in which preferred embodiments of the present invention are shown by way of illustrative example.

FIG. 1 is a block diagram showing the construc tion of a pulse-width modulation type inverter apparatus according to a first emtodi:nent of this invention; FIG. 2 is a circuit diagram for describing the operation of each of switching elements; FIG. 3 is a block diagram depicting the construction of a pulse-width modulation type inverter apparatus according to a second embodiment of this invent ion; FIGS. 4 trough 6 are waveforms for describing the operation of the second embodiment of this invention; FIG. 7 is a circuit diagram showing a referencevoltage generator according to the second embodiment of this invention; FIG. 8 is a format for illustrating the contents of data stored in a ROM;; FIG. 9 is a graphIc rerresentation of the shapes of waves that indicate the operation of the referencevoltage generator according to the second embodiment of this invention; FIG. 10 is a flow chart for describing the cper- at ion of the second embodiment of this invention; FIG. 11 is a block diagram showing the construciton of a pulse-width modulation inverter apparatus according td a modification of the second embodiment of this invention; FIG. 12 is a circuit diagram depicting a reference-voltage generator according to a modification of the second embodiment of this invention;; FIG. 13 is a graphic representation of the shapes of waves that indicate the operation of the reference-voltage generator according to the modification of the second embodiment of this invention; FIG. 14 is a block diagram illustrating the construction of a pulse-width modulation type inverter arats according to a third embodiment of this invent ion; FIG. i5 is a block diagram depicting the construction of a pulse-width modulation type inverter apparatus according to a fourth embodiment of this in vent ion; FIG. 15 is a block diagram showing the conven tonal puse-width modulation type inverter apparatus; Flu. 1 is a circuit diagram for generating a PWX control signal;; FIG. IS is waveforms for describing the cperation of the conventional pulse-width modulation type inverter apparatus; FIGS. 19 and 20 are waveforms for describing waveform distortion which appears at the waveform of an output volatge produced during a short-prevention period Td; FIG. 21 is a block diagram showing the construction of another conventional pulse-width modulation type inverter apparatus; FIG. 22 is a circuit diagram of a potential detector employed in the conventIonal pulse-width modulation type inverter apparatus of FIG. 21;; FIG. 23 is wavefors for decribing the manner of correction of waveform distortion which appears at the waveform of an output voltage produced during the short-prevention period Td in the conventional pulsewidth modulation type inverter apparatus of FIG. 21; FIG. 24 is a block dIagram illustrating the construction of a further conventional pulse-width modulation type inverter apparatus; and FIG. 25 is waveforms for describing the manner of correction of wavefcrm distortion which appears at the waveform of an output voltage produced during the short-prevention period Td in the conventional pulsewidth modulation type Inverter apparatus of FIG. 24.

A first embodiment of this invention will hereinafter be described with reference to the accompanying drawings. Referring now to FIG. 1, designated at numeral 80 is a selecting means which is adapted to receive a PWM signal to which shortprevention processing has been made by a processing means 65 and a PWM signal from a PWM circuit 60, to which no short-prevention processing is made and to judge whether or not output current falls within substantially zero level region and it is positive or negative, based on a signal from a current detector 90 for selecting a switching signal which effectively acts on each of controllable elements with respect to individual phases, from the result of the above judgement so as to supply the same to a drive circuit 70.

Incidentally, in the same drawing, the same elements of structure as those in a conventional example shown in FIG. 16 or 24 are identified by like reference numerals and their description will therefore he omitted herein.

A descriFti3r, will next he made on the operation of time first erWodlnent. FIG. 2 is a circuit diagram of an inverter output unit which operates under a U phase, in which FIG. 2(a) shows a circuit diagram of the output unit in time case where cutout current IU is positive (I > Oj and FITS. 2(b, depicts a circuit diagram of the output unit in the case where output current IU is negative (Iu < o).

Let' now assume that an upper-side transistor TRUp as a controllable element as shown in FIG. 2(a) is in an ON state and the output current IU flows through the cirucit in the form of a positive polarity. In this case, needless to say, a lower-side transistor TRUN as a controllable element is in a OFF state. At this time, the potential corresponding to the U phase at an output terminal U becomes equal to E/2 because the output terminal is electrically connected to a d.c. bus owing to turn-on of the transistor TRUp.

When the transistor TRUp is next brought into an OFF state, the output current IU will continue to flow in the same direction, so that it flows by way of a lower-side diode DN. At this time, the potential at the output terminal U becomes -E/2 because it is connected to a d.c. bus N owing to conduction of the diode DUN.

Then, after the short-prevention period Td has elapsed, the transistor TRUN is turned on. Howerver, the output current I. continues to flow by way of the diode DUN in spite of turn-on of the transistor TRUN.

Therefore, the potential at the output terminal U still te-e-,.s -E/2. Then, even when the transistor TRUN is brought into an OFF state, the potential at the output terminal U remains unchanged. When the transistor Trump is turned on after the shortprevent ion period Td has elapsed, the output current IU flows into the transistor TRUp, so that the potential at the output terminal U is brought into E/2.

Similarly, the dbove-described operations are applied to those executed at V and W phases.

Let's next assume that as shown in FIG. 2(b), the transistor TRUN is in an ON state and output crrent IU flows in the circuit in the form of negative polarity. In this case, needless to say, the trasistor TRUP is in an OFF state. At this time, the potential under an U phase at an output terminal U is esaul to -E/2 because the output terminal is electrically connected to a d.c. bus N owing to turn-on of the transistor TRUN.

Then, when the transistor TRUN is turned on, the output current IU will continue to flow in the same direction, so that it flows in the circuit by way of an uppper-side diode Dp. At this time, the potential at the c'fltput terminal U becomes E/2 because the output terminal U is electrically connected to a d.c. bus owing tc conduction of the diode Dup.

Then, the transistor TPp is turned on after the short-prevention period Td has elapsed. However, the output current IU continues to flow through the diode Dup in spite of turn-on of the transistor Trump, so that the potential at the output terminal U remains Ej2. Then, the potential at the output terminal U remains unchanged in spite of turn-off of the transistor TRUG.

When the transistor TRUN is then turned on after the short-prevention period Td has elapsed, the output current IU flows into the transistor TRUN, so that the potential at the output terminal U is changed to -E/2.

Similarly, the operation referred to above is applied to that at each of the V and W phases.

In other words, the output current is controlled at the timing of switching of the upper-side controllable element regardless of the timing of switching of the lower-side controllable element as long as the output current is kept in a positive-polarity state.

In addition, the output current is governed at the timing of switching of the lower-side controllable element regardless of the timing of switching of the upper-side controllable element as long as the output current is kept in a negative-polarity state.

Thus, if the polarity of the output current has already been established, .e., where the polarity of the output current 15 positive, it is only necessary to make a switching operation ith respect to the upper-side controllable element alcne, i.e., turn on and off the u > er-side controllable element alone. On the other hand, where the po arnti of the output current is negative, it is only necessary to turn on and off the lower-side controllable element alone. Where the level of the output current is small and its polarity changes during switching operation, or in regions where the level of the output current is small and its polarity cannot be specified, it is only necessary to complementarily turn on and off the upper-side and lower-side controllable elements.

In othere words, in a region where the polarity of the output current has assuredly been established, it is practiced to drive its associated controllable element with the PWM signal prior to the shortprevention processing. In a region other than said region, it is practiced to drive the upper-side and lower-side controllable elements with the PhE signal subsequent to the short-prevention processing.

The above-described operation will next be de scribe in detail with reference to FIG. 1. When a reference voltage having such a waveform as shown in FIG. 18(a) is outputted from a reference voltage generator 4C and a carrier having such a waveform as depicted in FIG. 18(a) is generated by a carrier generator 5C, PWM signals Up0,U'0 depicted in FIG. 18(b) are generated bused on the reference voltage and the carrier by time PeM circuit 60.In addition, the short-v-evelion Frosessed ph. signals Up,UN shown in FIG. 18(c) are produced by the processing means 65 based on the PWM signals U PO,UNO.

Assuming now that the output current IU flows in such a state as illustrated in FIG. 18(a), the current detector 90 serves to detect this current for supplying the result of detection to the selecting means 80.

Then, the selecting means 80 executes the following operations in response to the signal thus detected.

In other words, let's now assume that the output current IU is sufficiently large and assumes negative polarity. In such a region, the output current IU falls under the control of switching operation of the lower-side controllable element. Thus, the PM signal UNO prior to the short-prevention processing is seXecte but the P'eM signal UpO at the upper-side controllable element is not chosen, so that this signal is brought into an off state.

Then, when the output current IU approaches a value in the vicinity of zero level to be intersected therewith and then becomes substantially zero level, the short-prevention Frocessed PhE signals Up,UN are selected. Where the output current IU is next increased and changed from the negative polarity to the positive polarity for assuredly establishing the state of the output current, the output current IU falls uner the ctrol of switching operation of the upperside controllable element in such a region. Thus, the r '. signal UpO prior to the short-prevention processing is selected tut the PWM signal UNO at the power side controllable element is not chosen, so that this signal is rendered off.Even if the conditions of a loard or the like changes and the output current IU varies correspondingly, the same selection operation is made. Incidentally, the operation similar to that described above is executed even with respect to V and W phases.

Then, the drive circuit 70 performs a switching operation of the upper and lower controllable elements in response to the signal from the selecting means 80, thereby to drive an electric motor 30 at the variable speed. Thus, an output voltage corresponding to the reference voltage waveform can be obtained without being affected by the short-prevention period Td within a period during which the polarity of an output current has been established. The electric motor 30 is driven by a P;;8t signal subsequent to the shortprevention processing within a period during which the output current falls within substantially zero level.

Therefore, the output current is affected by the shor-p.evenaion period Td. This period is ex'remely short compared ;=h the period during which the polarity of the output current has been established.

In addition, the period during which time output current falls within the substantIally zero level can further he corpressec if carrier frequencies are high, the ripple of current is small and the output current is in the form of a smoother sine wave. Thus, the output current is hardly affected by the shortprevention period, considered as a whole. Accordingly, the distortion of the output voltage, reduction in the output voltage, torque ripples, irregularity in rotation, etc. do not occur and high stability can be achieved.

A description will next be made on the second embodiment of this invention with reference to FIG. 3.

In FIG. 3, numeral 90 indicates a current detector for detecting the level of output current from an inverter and numeral 40a indicates a reference voltage generator, as a reference signal generating means, for outputting a waveform that indicates a reference voltage as a reference of an output frequency or output voltage. This waveform is one for making maximum a period corresponding to r/3(rad) during a half cycle so as to saturate time same to be positive or negative, thereby controlling the remaining two phases (so-called twoarm modulation control).Thus, this reference voltage generator serves to control such that the region within the saturated period during the half cycle corresponds substantially to t period indicative of zero level of the output current in response to each output from the current detector 90.

Incidentally, in time so drawing, the same elements of structure as those in a c~nve..tsonal example shown in FIG. 21 are identified by like reference numerals and their description will therefore be omitted herein.

A description will next be made on the operation of the second embodiment. First of all, a method of production of each waveform indicative of the reference voltage employed in the two-arm modulation mode with reference to FIG. 4. FIG. 4(a) is a graphic representation of the shape of a wave that indicates a voltage VU,V between U and V, out of waves indicative of line voltages to be outputted. The solid line represents an example in which the voltage control rate is equal to 1 (k=l) and the broken line also shows an example in which the rate is equal to 0.5 (k=0.5).This voltage VUU is expressed by k.E.sin #, where E represents a d.c. bus line voltage and a Uphase reference voltage U(6) for generating the voltage VU-V between U and V phases is expressed by the equation depicted by FIG. 4(f).

V(#) and '(4) can be obtained by shifting U( & 2#/3 by 2r,3 in radians.

The phase at #=0(rad) will next be defined as shown in FIG. 4(a). In this case, FIGS. 4(c), 4(d) and 4e, are representative of phases at w=O(rad) by way of an illustrative example. FIGS. 4(c), 4(d) and 4 (e, show waveshapes at the reference volatges U(6), V(#) and W(#) respectively. FIG. 4(b) shows an exam- ple representative of a waveshape at the reference voltage u(f) when ç = #/6(rad).

This # may be in the range from 0 to r/3(rad) as is understood from the relationship between FIGS. 5(a) and 5(b). The relational expressions shown in FIG.

4(f) are each given as the general formula by fixing # out of 6' = 6+s to each of O to #/3(rad).

As undestood from FIG. 5(a), for example, a period in which a voltage corresponding to the U phase represents the maximum with respect to other V and W phases corresponds to 2/3(rad), while its minimal period also corresponds to 2n/3(rad). In order to ob tain the above maximal and minimal periods, it is only necessary to saturate the U phase to be positive or negative and then determine other two phases [saturation: they may be fixed to E/2 or -E/2 in this case.

The switiching operation of a controllable element is stopped by turning on or off a PWM signal within those periods because the crest value of a wave of a carrier frequency falls between E/2 and -E/2 as shown in FIG.

(f).]. However, each of the period in which the U phase is to be saturated so as to be positive or nega- tive becomes n/3(rad) at the maximum because three phases are detemIne.d in the above-described manner each period becomes 7r/3 at the maximum because of division of the periods to be saturated with the three phases for each half cycle, i.e., r (rad). Thus, ç is in the range of O to r/3(rad).

Incidentally, the way of obtaining a variable voltage and a variable frequency as an output is the same as the two-arm modulation control method. Namely, it is only necessary to control the voltage control rate k in the case of voltage control and to control the phase-angle velocity in the case of frequency control.

FIGS. 5 is a graphic representation of the shapes of each wave at the reference voltages under the two-arm modulation control, similarly to FIG. 4.

In FIG. 5, FIG. 5(a) shows each phase voltage and the range within which each of the phases is saturable into a positive or negative state. FIG.

5(b) is the same as FIG. 4(a). FIGS. 5(c), 5(d) and 5(e) are waveforms cf reference voltages U(S), V(6) and W(#) corresponding to the U, V and W phases in the case where ç = #/6(rad). FIG. 5(f) is a waveform of the reference voltage U() in the case where ç = /3(rad), and FIG. 5(gj is a waveform of the reference voltage U() in the case where +^ = C(ra5) . FIG. 5(h) is a graphic representation of the shapes of a wave that indicates a carrier frequency by way of example and depicts a case where six ~-.efcrrs are included within one cycle out of each output from the inverter for the brevity of description.

The waveforms at the reference voltages with respect to the respective phases employed in the twoarm modulation control method can be determined in the above-described manner. It has here been clear that the period of tp can have the degree of freedom taken among # = O to 7r/3(rad) even in the case of use of the same two-arm control.

The operation of the present embodiment will hereinafter be described with reference to FIGS. 3 and 6.

FIGS. 6(a) and 6(b) are the same as FIGS. 5(a) and 5(b). FIG. 6(c) is a waveform of a reference voltage U(s) at the time when ç = r/3(rad). FIG. 6(d) is a waveform of the reference voltage U() at the time when ç = r/6(rad) and FIG. 6(e) is a waveform of the reference voltage U(6) at the time when ç = 0(rad). FIGS. 6(f), 6(g) and 6(h) are graphic representation of the shapes of waves that indicate current corresponding to the U phase and each show the state of different power factor.

Let's now assume that a PWM signal is generated under the condition of a certain frequency and voltage so as to drive the electric motor 30. At this time, let's further assume that the load is relatively small and the U-phase output current flows as shown in FIG.

6 (g). Then, the current detector 90 detects this state. Thereafter, the preference voltage generator 4Oa serves to receive the signal from the current detector 90 for generating the waveform indicative of the reference voltage illustrated in FIG. 6(d) in such a way that the reference voltage is saturated within the region of substantially zero level of the output current, thereby to output the result to the PhE circuit 60. As a consequence, the PhE control is achieved based on an output from the PM circuit 60.

Assuming next that the load is rendered high thereby to make the power factor greater and the output current corresponding to the U phase flows as shown in FIG. 6(f). In this case, the reference voltage generator 4Ca generates a waveform representative of a reference voltage, which is shown in FIG. 6(c), in response to the output from the current detector 90, thereby to supply the result to the P,E circuit 60.

Thus, the PWM circuit 60 generates a pwE signal based on the waveform indicative of the reference voltage, which has been produced in the above aescr bed manner, an output from the carrier generator 50 and an output from a potential detector 55. Each of the waveforms indicative of the reference voltages is crerated such that a tire interval during which the output current is substantially zero level is sturated as descrIbed above. Thus, the switching operation of a controllable element is brought into a stop state between a tie interval during which the logic level of the output voltage is uncertain. It is unnecessary to correct the influence of the shortprevent ion period.Similarly to the conventional example, it is practiced to correct the influence of the short-prevention period Td in response to an output from the potential detector 55 with respect to a time interval during which the logic level of the output voltage is established. It is thus possible to always correct the influence of the short-prevention period Td even at any state of applied loads or any state of the power factor. Thus, an ideal operation of the electric motor can be realized without any detectable formation of the reduction in voltage, distortion in voltage, torque ripples, irreqularity of rotation, etc.

FIG. 7 shows one example in which the reference voltage generator 40a having the above-described functions is constructed by a digital circuit. For the brevity of description, FIG. 7 depicts one example of the reference voltage generator 40a in the case where a single 3se is used.Designated at nureral 41 is a zero level elector for detecting a period of substantially zero level in response to an output from a current detector 90 so as to supply the detected signal S1 to a coincidence detector 42. Numeral 44 indicates a counter for counting a clock of an output frequency co.-rand (which is to be given as a ciock) from the inverter to generate an inverter output phase command therefrom, thereby to supply the same to a POM 45, and for generating singals S41, S42 and S43 for reference waveform period, corresponding to the time interval during which output current is the substantially zero level, so as to supply them to the coincidence detector 42, where S41 is a correspondece signal for selecting a waveform indicative of the reference voltage at the time of ç=r/3(rad), S42 is a correspondece signal for selecting a waveform indicative of the reference voltage at the time of ç=ff/6(rad), S43 is a cor respondence signal for selecting a waveform indicative of the reference voltage at the time of s=0(rad).

Thus, the coincidence detector 42 serves to determine which signal out of the signals S41, S42 and S43 corresponds to a time interval during which the present output current falls within substantially zero level, in response to the outputs from the zero level detector and the counter 44, thereby to output one of the sir.gels. Numeral 43 indicates a selector for selecting each address in the ROM 45, in which data about the waveforms indicative of the reference voltages at the time of f=r/3 (rad), ç=r/6(rad) and *=C(rad) has been stored, in response to each output from the coincidence detector 42.For example, when the time interval representing the sustantially zero level corresponds to the signal S41, the selector selects the address (An,An-l)=(0,0). Likewise, when the time interval corresponds to the signal S42, it selects the address (An,An-l)=(0,1) and when the time interval corresponds to the signal S43, it selects the address (An,An-1)=(1,0). Designated at numeral 45 is a ROM in which data about the waveforms representing the reference voltages have been stored therein, which in turn stores, in a 8-bit binary form, the data about the waveforms representative of the reference voltages, which correspond to addresses reprentative of information (An,An-l) about the time interval of the substantially zero level of the output current from the selector 43, an inverter output voltage com- mand (An-2 - An-x) and of an output phase comjnand (Anx-l - A0). FIG. 8 shows one example of a format including the above data.

FIG. 9 is a graphic representation of the shapes of waves that indicate the operation of the reference voltage generator. In this case, the signal Sl corresponding to the time interval during which the detected output current falls within the substantialy zero level coincides with the signal S42 out of the signals S41, S42 ad S43. At this time, the selector 43 outputs the address (Ah,Ah-1)=(0,1). Then, the ROM 5 selects the waveform representative of the reference voltage at the time that ç=r/6(rad) to supply the se to the Pew'A circuit 60. Similarly, the same operation as described above is also performed with respect to the other phases. The flow chart of operation of the present embodiment with respect to the other phases will be shown in FIG. 10.

A description will next be made on a modification of the second embodiment according to this invention with referecne to the drawing. Referring to FIG.

11, numeral 40b indicates a reference voltage genera tor, as a reference signal generating means, for outputting a waveform that indicates a reference voltage as a reference of an output frequency or output voltage. This waveform is one for making maximum each period corresponding to rj3(radj during a half cycle so as to saturate the same to be positive or negative, thereby controlling the remaining two phases (socalled two-arm modulation control).Thus, this reference voltage generator serves to control such that each region within the saturated period during the half cycle corresponds substantially to the period indicative of zero level of the output current in response to each output from the current detector 90, and to correct the waveform representative of the reference voltage se as to counteract the influence of the short-prevention period Td on the output voltage.

Incidentally, in the same drawing, the same elements of structure as those in a conventional example shown in FIG. 24 are identified by lirze reference numerals and their description will therefore be omitted herein.

A description will next be made on the operation of the modification of the second embodiment. Incidentally, the method of generating a reference voltage waveform in the two-arm modulation mode has already been described by the above-described embodiment and its description will therefore be omitted herein.

The elements of structure dissimilar to those in the above-described embodiments will be described with reference to FIGS. 11 and 6.

Let's now assume that a PWM signal is generated under the condition of a certain frequency or voltage so as to drive the electric motor 30. At this time, let's further assume that the load'is relatively small and the U-phase output current flows as shown in FIG.

6 (g). Then, the current detector 90 detects this state. Thereafter, the reference voltage generator 40b serves to receive the signal from the current detector 90 for generating the waveform indicative of the reference voltage illustrated in FIG. 6(d) in such a way that the reference voltage is saturated within the region of substantially zero level of the output current.Then, the reference voltage generator 4Gb serves to receive an output from a polarity discriminating means 100 for correcting the waveform representative of the reference voltage so as to counteract the influence of the shor'-pre.ention period Td on the output voltage (the correction method is the same as the conventional example and its description will therefore be omitted), thereby to supply the result to a PE circuit 60. The U phase is hereinafter PuM-controlled based on the inputted signal. Incidentally, the V and W phases are also PWE- control led in the same manner.

Assuming next that the load is rendered high thereby to make the power factor greater and the output current corresponding to the U phase flows as shown in FIG. 6(f). In this case, the reference voltage generator 40b generates a waveform representative of a reference voltage, which is shown in FIG. 6(c), in response to the output from the current detector 90. Letìs also assume that the load is in a regenerative mode and an output current corresponding to the U phase flows as shown in FIG. 6(h). At this time, the referee voltage generator 40b is responsive to the output from the current detector 90 for generating the waveform indicative of the reference voltage il- lustrated in FIG. 6(e). The subsequent operation is executed in the same manner as described above.The F45 circuit 6G serves to generate a PhE signal based on the wwveform indicative of the reference voltage and the waveform Indicative of the carrier frequency, which have been generated in the above-decribed man- ner. Thus, the waveform indicative of the reference voltage is formed such that the time interval during which the output current falls within the substantially zero level as described above, so that the saturated region is brought into a switching stop mode, thereby causing no influence of the shortprevention period Td on the output voltage.It is thus unnecessary to correct the influence of the short-prevention period Td on the output voltage within the period during which the output current falls within the substantially zero level even in the case where the accuracy of the polarity discriminating means 100 is insufficient, thereby causing no problems.

The region other than the above saturated region is also brought into a switching mode. It is thus necessary te correct the influence of the shortprevention period Td on the output voltage because the switching operation is performed. However, the output current is sufficiently large in this region and the polarity 3iscriminating means 100 can function with high as~,racry. it 15 thus possible te correct the influence of the short-prevention period Td in response te the output from the current detector 90.

Acccrdingly, it is possible to always correct the in fluence of the short-prevention period Td even at any state of applied loads cr ary state of the power factor. Therefore, an ideal operation of the electric motor can be realized without any detectable formation of the reduction in voltage, the distortion in voltage, the torque ripples, the irreqularity of rotation, etc.

FIG. 12 shows one example in which the reference voltage generator 40b having the above-described functions is constructed by a digital circuit. For the brevity of descripition, FIG. 12 depicts one example of the reference voltage generator 40b in the case where only a single phase is used. Incidentally, in the same drawing, the same elements of structure as those shown in FIG. 7 are identified by like reference numerals and their description will therefore be omitted herein.In FIG. 12, designated at numeral 46 is a means for correcting, in response to an output signal S2 from the polarity discriminating means 100, a distortion component AV in a direction in which the influence of the short-prevention period Td cn the output voltage is counteracted, with respect to the non-saturated region of the waveform indicative of the reference voltage, thereby te supply the corrected signal to the ptE circuit 60.

FIG. 13 is a graphic representation of the shapes of waves that indicate the operation of the circuit shown in FIG. 12. At this time, the signal S1 detected within the period during which the output current falls within the substantially zero level coincides with the signal S42 out of the signals S41, S42 and S43, and at the sane time, the selector 43 outputs data (An,An-1)=(0,1) and the ROM 45 selects a waveform indicative of the reference voltage to supply the same to the correcting means 46.The correcting means 46 is responsive to this signal representing the reference voltage waveform for correcting the distor tion component #V in the direction in which the influence of the short-prevention period Td on the output voltage is counteracted or cancelled, with respect to the non-saturated region of the selected reference voltage waveform, thereby to supply the result of correction to the PhE circuit 60. The same operation as described above is also performed with respect to other phases by the circuit similar to that employed in the above embodiment. The flow chart of operation of the present embodiment with respect to the other phases is similar to that in FIG. 10.

A description will next be made on a third embodiment of this invention with reference to FIG. 14.

In FIG. 14, the same elements of structure as those shown in FIG. 1 or 3 are idemtified by like reference numerals and their description will therefore be omitted herein.

A description will next be made on the operation of the third embodIment. When a signal having such a reference voltage waveform as shewn in FIG. 18 (a) is supplied from a reference voltage generator 40a to a PWM circuit and a signal having a waveform indicative of a carrier frequency is fed from a carrier generator 50 to the P-nE circuit, the P'e'M circuit 60 generates PWM signals UPO,UNO shown in FIG. 18(b) based on both signals therefrom.

Let's now assume that output current IU flows in the form of a waveform shown in FIG. 18(a). At this time, the current detector 90 serves to detect this current for supplying the result to a selecting means 80, which is in turn responsive to the output signal from the current detector 90 so as to perform such an operation as described below.

In other words, let's now assume that the output current Iu is sufficiently large and assumes negative polarity. In such a region, the output current IU falls under the control of switching operation of the lower-side controllable element as expressed in the abcve-described embodiment. Thus, the PWM signal UUN is sleeted but the FM signal Up0 is not chosen, so that this s',ral is brought into an off state.

Then, en the output current U apprcaches a value in the vicinity of the zero level to be intersected therewith and then becomes substantially zero level, each period corresponding to o/3(rad) during the half cycle in the reference voltage waveform cor respon I ng to the U phase is rendered maximum, there rb to saturate the same so as to be positive or negative, and the remaining phases are then subjected to the two-arm modulation control at the reference voltage generator 4Ga, as in the above-decribed embodiment.

When the output current IU is next increased and changed from the negative polarity to the positive polarity so as to be free of the region of the substantially zero level for assuredly establishing the polarity of the output current, the output current IU falls under the control of switching operation of the upper-side controllable element in such a region as in the above-described embodiment. Thus, the selecting means 80 selects the PWM signal UpO but does not select the F signal UNO at the lower-side controllable element, thereby rendering this signal off.Even when the conditions of a load or the like changes and the output current IU varies correspondingly, the same selection operation is made. Incidentally, the operation similar to that described above is also executed with respect to V an Phases.

Then, the drive circuit ^ performs a switching control operation of the upper and lower controllable elements in response to the sigma 1 from the selecting means 80, thereby to drive an electric rotor 30 at the variable speed. Thus, an output voltage corresponding to the reference voltage avefcrm can be obtained even within a period during which the polarity of output current has been established and even in the region of the substantially zero level within which its polarity is not determined. It is thus unnecessary to establish the short-prevention period Td. In addition, the distortion of the output voltage, reduction in the output voltage, torque ripple, irregularity in rota tion, etc. does not appear and the high stability can be achieved.

The fourth embodiment of this invention will next be described with reference to FIG. 15. In FIG.

15, the same elements of structure as those shown in FIG. 1 or FIG. 14 are identified by like reference numerals and their description will therefore be omitted.

A description will next be made on the operation of the fourth embodiment. When a reference voltage having such a aefor as shown in FIG. 18(a) is now outputted from a reference voltage generator 40a and a carrier having such a waveform as depicted in FIG.

18(a) is generated by a carrier generator 50, PWM signals UPO,UNO depicted in FIG. 18(b) are generated based on the reference voltage and the carrier by the Pem circuit 60. In addition, the short-prevetion processed PWW signals Up,U; shown in FIG. 18(c) are produced by the Processing means 65 based on the PWM signals UPO,UNO.

Assuming now that the output current IU flows in such a state as illustrated in FIG. 18(a), the current detector 90 serves to detect this current for supplying the result of detection to the selecting means 80.

Then, the selecting means 80 executes the following operations in response to the signal from the current detector 90.

In other words, let's now assume that the output current IU is sufficiently large and assumes negative polarity. In such a region, the output current IU falls under the control of switching operation of the lower-side controllable element as stated in the above-described embodiment. Thus, the selecting means 80 selects the PWM signal UNO prior to the shortprevention processing but does not select the PhE signal C'pO at t upper-side controllable element, so that this signal is brought into an off state.

Then, when the output current IU approaches a value in the vicinity of the zero level to be inter sect: therewith and then becomes the substantially zero level, each period corresponding to r/3(rad) dur ini the half cycle in the reference voltage waveform corresponding to the U phase is rendered maximum, thereby to saturate the same so as to be positive or necatlve, and te remaining phases are then subjected the the arm modulation control at the reference voltage generator 4Ga, as in the above-decribed em embodiment. For example, when a change in load is extremely large and the correction of the output voltage waveform falls within a range out of coverage by the above saturation operation, the reference voltage generator 40a serves to output such a reference voltage as shown in FIG. 18(a) as usual.

When the output current IU is next increased and changed from the negative polarity to the positive polarity so as to be free of the region of the substantially zero level for assuredly establishing the polarity of the output current, the output current falls under the control of switching operation of the upper-side controllable element in such a region as in the above-described embodiment. Thus, the selecting means 80 selects the PhE signal Upo prior to the short-prevention processing but does not select the F;wE signal UNO at the lower-side controllable element, thereby rendering this signal off.Even when the conditions of a load or the like changes and the output current IU varies correspondingly, the same selection operation is made. incidentally, the operation similar to that described above is also executed with respect to V and W phases.

Then, the drive circuit 70 performs switching control of the upper and lower controllable elements in response to the signal from the selecting means 80, thereby to drive an electric motor 30 at the variable speed. Thus, an output voltage corresponding to the reference voltage waveform can be obtained without being affected by the short-prevention period Td even within a period during which the polarity of output current has been established and even in the region of the substantially zero level within which its polarity is not fixed.Even when the change in load is ex tremely large and the correction of the output voltage waveform at the region of the substantially zero level of the output current becomes incomplete by the saturation operation of each phase, the output voltage waveform is little affected by the short-prevention period Td, considering it as a whole because the short-prevention processing operation is executed by the processing means 65. Accordingly, the distortion of the output voltage, reduction in the output voltage, torque ripples, irregularity in rotation, etc. do not appear and high stability can be achieved.

In each of the above-described embodiments, an illustrative example of the RGM in which data corresponding to each of ç=r/3(radV, t^=r/6 (rafflj and s=O(rad) have been stored ss value, has been shown by FIG. 7 or FIG. 12. As an alternative, the logic processing of the data referred to above may be ex ecuted using a ricroco ter, or the data 2 may be arithmetically operated for calcinaiion in place of storage of the data into the ROM 45.

The saturation period of the reference voltage waveform is represented by r/3(rad) for each half cycle by way of example in each of the above-described embodiment. It may be less than r/3(rad) in priciple.

Even in the case where at least output current which falls within the substantially zero level is saturated only during a period to make the logic level of an output voltage uncertain or during a period to change the output current from the positive to negative polorality or vice versa, the same advantageous effects as those in the above-described embodiments can be effected.

In the above-described embodiment, after the level of the output current has been detected by the current detector 90, each of the reference voltage generators 40a, 40b have controlled such that the period during which this output current falls within the substantially zero level coincides substantially with the saturation period of the reference voltage aveform. However, if the characteristic of a load is distinct in advance and the relationship between in formation about the current level (for example, peakvalue information or information about the effective value) and in formation about the period of the substantially zero level can be determined by p, the reference voltace waveform which has been determined in advance (or has been stored in advance) may be selected depending upon the information about the current level.

For example, in the case where the change in load is small or where it is clear in advance that a region within which deterioration in the drive characteristic of the electric motor gives rise to trouble can be covered by the saturation period r/3(rad) of the PWM signal, the same advantageous effects as those in each of the above-described embodiments can be effected even when ç is fixed and set to a desired value.

It has also been explained for the brevity of description that the cause of the voltage distortion is developed by the influence of the short-prevention period Td on the output voltage. However, needless to say, a time delay or the like at each unit is also included in practice because it has influence on the output voltage.

According to the present invent ion, as has been described tare, the output from the processing means is selected by the selecting means within the period during which the result of detection by te current detector falls within the substantially zero level.

n aMiditicn, the selecting means serves to select only the sisal corresponding to each switching element which effectively acts on the generation of the output current, out of the signals generated by the FM signal generating means, during the period other than that referred to above, for outputting the selected signal as the drive signal of the switching element.

Thus, the present invention can bring about an advantageous effect that the output voltage waveform can be corrected while controlling the influence of the short-prevention processing so as to be minimal, thereby making it possible to obtain output current with high stability.

Further, according to the present invention, the reference voltage generating means serves to make maximum the region corresponding to r/3(rad) during the half cycle of the output voltage waveform corresponding to the phase under which the output current is detected, for saturating the region, in association with the region of the substantially zero level of the output current from the inverter unit, which is detected by the current detector, and to generate the reference signal for performing the two-arm modulation control of the remaining phases so as to supply the generated signal to the pE signal generating means.

Thus, the present invention can bring about an advantageous effect that the correction of the output voltage waveform is assuredly performed even in the region where the output current IS rendered minimum, thereby making it possible to obtain the output current with high stability.

Furthermore, according to the present invention, the reference signal generating means serves to make maximum the region corresponding to w/3(rad) during the half cylce of the output voltage waveform corresponding to the phase under which the output current is detected, for saturating the region, in association with the region of the substantially zero level of the output current detected by the current detector, and to generate the reference signal for performing the two-arm modulation control of the remaining phases so as to supply the same to the P'E signal generating means.In addition, when the result of detection by the current detector falls within the period other than that corresponding to the region of the substantially zero level, the selecting means serves to select only the signal corresponding to each switching element which effectively acts on the generation of the above output current, out of the signals generated by the PwE signal generating means, for outputting the selected signal as the drive signal of the switching element.Thus, the present invention can bring about an advantageous effect that the output voltage waveform can assuredly be ccrrected even in the mini mal region of the output current and in the region other than the minimal region, thereby making it possible to obtain the output current with high stability.

Still further, according to the present invention, the reference signal generating means serves to make maximum the region corresponding to r/3(rad) during the half cycle of the outptu voltage waveform corresponding to the phase under which the output current is detected, for saturating the region, in association with the region of the substantially zero level of the output current detected by the current detector, and to generate the reference signal for peforming the two-arm modulation control of the remaining phases so as to supply the same to the Pie signal generating means.In addition, the selecting means serves to select the signal generated by the processing means during the period of the substantially zero level of the current detected by the current detector, and to select only the signal corresponding to each switching element which effectively acts on the generation of the output current, out of the signals generated by the pt signal generating means, for outputting the selected signal as the drive signal of each switching element Thus, the present invention can bring about an advantageous effect that the correction of the otuput voltage waveform can assuredly be performed even in the region at which the output current is rendered minimum and in the region other than the min final region and the output current with high stability, which can meet any state of the load.

Having now fully described the invent ion, it will be apparent to those skilled in the art that many changes and modifications can be made without departing from the spirit or scope of the invention as set forth herein.

Claims (7)

1 . A pulse-width modulation type inverter apparatus, comprising: an inverter unit composed of ars connected in the form of three-phase bridge said arms including a pair of switching elements which are connected in series and on/off controlled in a complementary form; a current detector for detecting output current from said inverter unit; PWM signal generating means for generating each of pulse-width modulation signals for controlling each of said switching elements;; process no means for subjecting each signal generated by said P'. signal generating means to Frocessing for preventing a shirt circuit between said pair of swltchfnc elements: and reference signal generating means for saturating a region corresponding to r/3(rad) at the maximum during a half cycle of each output voltage waveform corresponding to an desired phase, in association with a region of substantially zero level of the current detected by said current detector, thereby to perform two-arm modulation of the remaining phases and for generating each reference signal for outputting each output voltage in the form of a substantially sine wave thereby to supply the same to said PhE signal generating means.

A A pu'se-width modu'lation type inverter appa- ratus according to Claim ffl, wherein said processing means serves to delay on-timing of each signal as an output venerated by said row signal generating means by a time interval corresponding to a short-prevention period.

3. A pulse-wiith modulation type inverter apparatus according to Claim , wherein said reference voltage generating means serves to output each reference voltage which corresponds to a certain phase and is set so as to be a saturated voltage within a period during which output current falls within a time interval of zero level when said current detector detects that the output current corresponding to the certain phase and outputted from said inverter unit falls within the time interval of the zero level.

4. A pulse-width modulation type inverter apparatus according to Claim , wherein said pulse-width modulation signals are each free from being turned to an on or off state upon saturation of the reference voltage.

A A pulse-width modulation type inverter appa- ratus according to Claim , wherein said reference voltage generating means includes a zero level detector for detecting a time interval correspcnding to zero level, a counter for chanting each of clock sig nals for spe-,ffi output frequencies at said inperter unit so as to output three kinks of phase dis criri::,aring ssg..als, a ROY. adapted to store each of reference voltage waveforms therein, a coincIdence detector for ,udFing to which phase discriminating signal the tie interval of the zero level detected by said zero level detector corresponds, so as to output each one of said phase discriminating signals, which corresponds to the time interval of the zero level, and a selector for outputting each of addresses which designate an area in said ROM, in which data about said each reference voltage waveform associated with each phase discriminating signal outputted by said coincidence detector has been stored.

A A pulse-width modulation type inverter appa- ratus according to Claim , wherein said ROM includes data about each reference voltage waveform corresponding to each of r/3(rad), #/6(rad) and 0(rad).

7. A pulse-width modulation type inverter apparatus according to Claim 3, further comprising means for discriminating the polarity of output current from said inverter unit and wherein said reference signal generating means further serves to correct each reference voltage in accordance with the polarity decn e~ by each one of polarity discriminating signals which are te be outputted by said polarity dis crImlnatlng mars an order to reduce distortion com- ponents which appear at each output voltage from said inverter unit during the short-prevention period.

A A pulse-width modulation type inverter appara- tus according to Claim ~, wherein said reference voltage generating means includes a zero level detector for detecting a time interval corresponding to zero level, a counter for counting each of clock signals for specifying output frequencies at said inverter unit so as to output three kinds of phase discriminating signals, a ROM adapted to store each of reference voltage waveforms therein, a coincidence detector for judging to which phase discriminating signal the time interval of the zero level detected by said zero level detector corresponds, so as to output one of said phase discriminating signals, which corresponds to the time interval of the zero level, a selector for outputting each of addresses which designate an area in said ROM, in which data about said reference voltage waveform associated with each phase discriminating signal outputted by said coincidence detector has been stored, and means for correcting each output data from said ROM in accordance with the polarity designated by each one of polarity discriminating signals which are to be outputted b said polarity discriminating means.

A A pu'se-*idth modulation type Inverter appara- tus according to Claim , wherein said ROM includes data about each reference voltage waveform corresponding to each of n/3(rad), #/6(rad) and 0trad).