GB2237481A - Detecting communication path errors - Google Patents

Abstract

In order to detect errors in a communication path, the level of an input digital signal (INPUT) is sampled several times per bit, for instance by an up/down counter (1) (Fig. 1 not shown) or a SIPO shift register (20) and summer (21). The number of samples per bit having the same value is compared in a comparator (2) with upper and lower limits and, it the number is between these limits, an error signal (FAULT) is given. The apparatus is immune to narrow voltage spikes or transients, affecting only one of the seven samples of each bit, but errors affecting two or more samples are indicated as faults. <IMAGE>

Description

APPARATUS FOR DETECTING COMMUNICATION PATH ERRORS.

The invention relates to apparatuses for detecting communication path errors. Such apparatuses may be used between a digital communication path and receiving apparatus in order to detect errors caused by electromagnetic interference or by various short-circuit fault modes.

When digital signals are transmitted along a communication path such that first and second voltage levels represent binary "0" and "1" digits, respectively, the voltage levels are detected at the receiving end of the path and converted in an interface circuit into the corresponding digital voltage levels used by digital circuitry in the receiving apparatus. Such interface conversion is necessary, even when the digital voltage levels of the receiving apparatus nominally correspond to those of the transmitter supplying the digital signals to the communication path, because the transmission properties of the path and interfering signals picked up by the path can degrade the signals beyond the tolerances of the receiving apparatus.The interface circuit provides resistance to, for instance, voltage spikes or transients induced in conductors of the path and performs voltage comparison in order to detect the binary digits of the signal from the path.

However, certain forms of interference and certain types of fault condition cause the signals in the communications path to be corrupted to such an extent that known types of interface circuits make erroneous voltage level detections. This in turn causes the receiving apparatus to receive corrupted signals without being aware that an error has occurred. For instance, in digital control systems used in aircraft where digital signals are transmitted from one part of the aircraft to another along a communication path, a "hot short" can occur such that a conductor of the communication path is short-circuited to a power supply voltage. This can cause the receiving apparatus to receive incorrect data or control signals, with potentially very serious results.

According to the invention, there is provided an apparatus for detecting a communication path error, comprising sampling means for sampling an input signal at a plurality of sampling times during each bit period and for supplying an output signal representing the level of the input signal at each of the sampling times, and fault indicating means for providing a fault indicating signal when the sampling means output signal represents a number of input signal samples of the same level which number is between a first predetermined number and a second predetermined number.

Preferably the sampling means is arranged to detect when each sampled value of the input signal lies in a predetermined voltage range, for instance in a voltage range greater than a predetermined value. In such a case where the predetermined voltage range corresponds to binary or logic level "1", the fault indicating means provides the fault indicating signal when too many of the sampled levels are at the level "1" for the received bit to represent "0" with confidence, but too few of the sampled levels are at the level "1" for the received bit to represent "1" with confidence.However, by not requiring that all of the sampled levels are at the level "1" for the received bit to represent "1", or that all the sampled levels are "less than 1" for the received bit to represent "0", the apparatus has immunity to interference such as narrow voltage transients or spikes and can be used to provide detection of bits representing "O" and "1" with a high degree of confidence.

The apparatus itself may be used as an interface between a communication path and a receiving apparatus and may convert between the input signals from the path and digital output signals generated according to whether the sampling output signal represents a number of input signal samples of the same level greater than or equal to the first predetermined number (e.g. representing "1") or less than or equal to the second predetermined number (e.g. representing "0"). Where the apparatus includes means for generating digital output signals, the problem may arise as to what sort of output signal to supply when an error is detected. In order to deal with this problem, the apparatus may include means for repeating a previous digital signal when the fault indicating signal is produced.Thus, a signal whose level cannot be detected with confidence can be replaced by a previous correctly detected signal.

Alternatively, separate means may be provided for converting the input signals to output digital signals, and suitable processing means arranged to receive the output digital signals and the fault indicating signal may be used to take appropriate action when an error is detected.

In one embodiment, the sampling means may comprise an up/down counter having an up/down control input for receiving the input signal, a clock input for receiving a clock signal whose frequency is greater than the bit rate of the input signal, and means for preventing underflow and overflow of the counter. In another embodiment, the sampling means may comprise a serial-in/parallel-out shift register having a data input for receiving the input signal and a clock input for receiving a clock signal whose frequency is greater than the bit rate of the input signal, and a summer for summing the outputs of the shift register. In both embodiments, the clock frequency may be nominally equal to a multiple of the bit rate, and the fault indicating means may comprise one or more digital comparators.

The invention will be further described, by way of example, with reference to the accompanying drawings, in which: Figure 1 is a circuit diagram of an apparatus for detecting a communication path error constituting a first embodiment of the invention; and Figure 2 is a circuit diagram of an apparatus for detecting a communication path error constituting a second embodiment of the invention.

The apparatuses shown in the accompanying drawings may be used to detect errors in signals received from any digital communication path in which the binary digits are received serially and are represented by standard logic voltage levels. One application of circuits of this type is for the detection of hot shorts occurring on communication paths, for instance to fuel control systems in aero engines. Several such circuits may be provided as parts of interfaces between several communication paths and further circuitry, such as data processors, and interfaces including several circuits of the type shown in the accompanying drawings may be provided on, for instance, an application specific integrated circuit (ASIC).

The apparatus shown in Figure 1 comprises a three bit up/down counter 1 having an up/down control input connected to receive an input signal INPUT from a communication path such that, when the signal INPUT has a logic high value, the counter 1 is set to count up whereas, when the signal INPUT has a logic low level, the counter 1 is set to count down. The counter 1 has a clock input connected to receive clock pulses CLK, and also includes means for preventing the counter from overflowing and underflowing i.e. means for preventing the contents of the counter from going below zero and above seven. In the embodiment shown in Figure 1, the bit rate of digital signals received from the communication path is nominally 400 bits per second and the clock rate of the clock signals CLK is 2.8 kHz.

Thus, the counter 1 effectively samples the signal INPUT seven times during each bit period.

The outputs QA, QB and QC of the counter 3 are connected to a digital comparator 2 which has a first output producing an output signal when the contents of the cdunter 1 exceed five and a second output signal when the contents of the counter 1 are less than two. The comparator 2 has first and second outputs 3 and 4 for the first and second output signals, respectively.

The first and second outputs 3 and 4 of the comparator 2 are connected to first and second complementing or inverting inputs of an AND gate 5, whose output is connected to a datainput of a D-type flip-flop 6. The flip-flop 6 has a Q output for supplying a fault indicating signal FAULT when an error or fault is detected and a clock input connected to the output of an inverter 7 whose input receives the clock pulses CLK.

The apparatus shown in Figure 1 further includes means for providing a digital output signal OUTPUT representing the detected logic level of the input signal INPUT, and for repeating a previous output signal when a fault is detected. These means comprise two D-type flip-flops 8 and 9, a two input NAND gate 10, a two input OR gate 11 having complementing or inverting inputs, and an inverter 12. The clock inputs of the flip-flops 8 and 9 are connected to receive the clock pulses CLK and the inverted clock pulses from the inverter 7, respectively.

The data input of the flip-flop 8 is connected to the Q output of the flip-flop 9, whose data input is connected to the output of the gate 11. A first inverting input of the gate 11 is connected to the output of the inverter 12 whose input is connected to the first output 3 of the comparator 2. The second inverting input of the gate 11 is connected to the output of the gate 10, whose first input is connected to the Q output of the flip-flop 8 and whose second input is connected to the output of the gate 5.

During normal operation when valid bits of the input signal are received, a transient fault signal is produced each time the input signal changes between logic high and logic low levels. However, such transient fault signals can be rejected, for instance by sampling the fault signal in synchronism with the incoming bits of the input signal or by integrating the fault signal so as to recognise only persistent faults.

In operation, the counter 1 samples the voltage level of each bit of the input signal at seven points. The comparator 2 determines whether the sampled values correspond to more than five logic high levels or less than two logic low levels. Thus, if the sampled bit of the input signal is at the logic high level for six or seven of the samples, this is taken to indicate that the bit represents logic high or "1" in positive logic.

Conversely, if the input bit is at logic high level for no or one sample, the input bit is detected as being at logic low level, representing logic 0 in positive logic.

In either case, the gate 5 supplies a low logic level to the gate 10, thus preventing the passage of signals from the flip-flop 8. Also, the flip-flop 6 is set to zero so that the fault signal is cleared. The flip-flop 9 is set to the logic level of the first output 3 of the comparator, and this is supplied as the output signal of the circuit.

By arranging the comparator 2 to compare the number of samples at the high logic level with two and five, the circuit is made immune to certain errors, such as narrow voltage spikes or transients which might affect one of the seven samples of each bit. However, in the event of larger errors or communication path faults, such as a hot short, the number of samples of the input signal at logic level 1 will be greater than or equal to two and less than or equal to five. In this case, the first and second outputs 3 and 4 of the comparator 2 will be at logic low level so that the output of the gate 5 will be at logic high level. The output of the flip-flop 6 will thus be set, indicating that a fault or error has been detected.Also, the output of the gate 5 opens the gate10, thus causing the previous output level of the flipflop 9, which has previously been clocked into the flipflop 8 to be clocked back into the flip-flop 9. Thus, whenever a fault condition is detected, the digital output of the circuit is maintained at the previous fault-free detected value.

The embodiment shown in Figure 2 differs from that shown in Figure 1 in that the counter 1 is replaced by a shift register 20 and a summer 21. The remaining components shown in Figure 2 are referred to by the same reference numerals as those used in Figure 1 for corresponding parts and will not be described further.

The shift register 20 is of the serial-in/parallel-out type and has a data input which receives the input signal INPUT and a clock input which receives the clock pulses CLK. The shift register has seven stages whose outputs QA to QG are connected to respective inputs of a summer 21. The summer 21 has a three bit parallel output which represents in binary form the sum of the logic high level signals supplied by the outputs of the shift register 20.

Thus, the binary three bit output of the summer 21 represents the number of samples at logic high level in the sampled bit of the input signal.

The remaining operation of the circuit shown in Figure 2 is the same as that shown in Figure 1, and will not be described further.

Claims (8)

CLAIMS.

1. An apparatus for detecting a communication path error, comprising sampling means for sampling an input signal at a plurality of sampling times during each bit period of the input signal and for supplying an output representing the level of the input signal at each of the sampling times, and fault indicating means for providing a fault indicating signal when the sampling means output signal represents a number of input signal samples of the same level which number is between a first predetermined number and a second predetermined number.

2. An apparatus as claimed in Claim 1, in which the sampling means is arranged to detect when each sampled value of the input signal lies in a predetermined voltage range.

3. An apparatus as claimed in Claim 2, in which the sampling means is arranged to detect when each sampled value of the input signal is greater than a predetermined value.

4. An apparatus as claimed in any one of the preceding claims, including means for supplying an output signal having a first value when the number of input signal samples of the same value is less than the first predetermined number and a second value when the number of input signal samples of the same value is greater than the second predetermined number, the second predetermined number being greater than the first predetermined number.

5. An apparatus as claimed in Claim 4, including means for repeating a previous output signal when the fault indicating signal is produced.

6. An apparatus as claimed in any one of the preceding claims, in which the sampling means comprises an up/down counter having an up/down control input for receiving the input signal, a clock input for receiving a clock signal whose frequency is greater than the bit rate of the input signal, and means for preventing underflow and overflow of the counter.

7. An apparatus as claimed in any one of Claims 1 to 5, in which the sampling means comprises a serialin/parallel-out shift register having a data input -for receiving the input signal and a clock input for receiving a clock signal whose frequency is greater than the bit rate of the input signal, and a summer for summing the outputs of the shift register.

8. An apparatus as claimed in Claim 6 or 7, in which the fault indicating means comprises a digital comparator.