GB2234871A - Power delivery circuit with over current detection - Google Patents

Abstract

A current switch S1' is connected on the high potential side of a load 14' and an over-current detection circuit 24' cooperates with the current switch S1' to turn the switch off on detection of an overcurrent. The switch comprises a multi-cellular device such as an FET or bipolar transistor, having a main current terminal (18, Figs 2A and 6) connected to a source of high potential, a main current terminal (16) connecting a majority of device cells to the load (14), a first auxiliary terminal (40) connected at one end to a minority of device cells so as to provide a current proportional to the main device current, and a second auxiliary terminal (42) connected at one end to a majority of device cells. The over-current detection circuit 24' comprises one branch connected between the first auxiliary terminal (40) and ground and including, in serial circuit, a current-to-voltage converting resistor (48 Fig 2A) providing a voltage at one end proportional to the main device current and a transimpedance device (44) such as a bipolar transistor coupling the first auxiliary terminal (40) to this resistor (48), and another branch connected between the second auxiliary terminal (42) and ground and providing a bias signal for the transimpedance device (44). The protection circuit can be used on the high potential sides of a H bridge circuit (Fig 1) with a motor load (14). <IMAGE>

Description

:,-- _e_-_ -171- 5 7:1 f - 1 POWER DELIVERY CIRCUIT WITH OVER-CURRENT

DETECTION The present invention relates to a power delivery circuit for supplying load current to a load, and more particularly to such a circuit including means to detect an over-current condition.

Power delivery circuits first for supplying load current to a load and including over-current detection means are known. See, for example, U.S. Pat- to ents 4,705,997 and 4,654,586. Such circuits typically include a current switch between a load and ground so that the switch is placed on the low potential side of the load. An over-current detection means is then responsive to the current level in the low potential side s switch. Such circuits typically require a dualpolarity voltage supply to provide a negative bias to an over-current detection device typically incorporating operational amplifier circuitry.

In environments where typically only single- polarity voltage supplies are provided, such as in automobiles, the above- described prior art circuitry requiring dual-polarity voltage supply cannot be used. It is also known to use current-sensing MOSFETs in the high side of a power switch. However, these devices z5 employ more complex control circuitry which is achieved by integrating the sense circuitry on an IC.

2 - It is, accordingly, an object of the invention to provide a power delivery circuit having a switch located on a high potential side of the load and including simple, discrete and reliable circuit means to detect an over-current condition in the load. The power delivery circuit preferably includes means to turn off the current through the switch upon detection of an over-current condition to prevent-destruction of the switch or of the load. The foregoing type of cir- cuit is particularly suitable for use with a singlepolarity voltage supply, such as typically provided in automobiles.

A further object of the invention is to provide a power delivery circuit with over-current protection that functions accurately and reliably despite large changes in ambient temperature, such as is typically encountered in an automobile.

Another object of the invention is to provide a power delivery circuit with over-current protec- tion that can be inexpensively manufactured with the use of readily- available discrete components.

In accordance with a preferred form of the invention, the power delivery circuit for supplying load current to a load is provided. The circuit includes a power node for connection to a source of electrical power, a load node for connection to a load, and a high potential current path for supplying electrical current from the power node to the load node. The high potential current path includes a current switch whose switching state is controlled by a control signal on an associated control terminal. The power delivery cir- 1 0 cuit further includes a single, highly reliable overcurrent detection circuit responsive to an electrical condition of the high potential current path. The over-current detection circuit is for detecting when the current in the high potential current path exceeds a predetermined level. The power delivery circuit, preferably, further includes current turn-oft means for disabling current flow to the load when an over- current condition is detected.

In a particularly preferred embodiment of the invention for providing accurate and reliable overcurrent detection, the curr ent switch in the high potential current path comprises a multi- cellular device with a plurality of terminals including a first main current terminal connected to the power means, a second main current terminal connecting a majority of device cells to the electrical load, a first auxiliary terminal connected at one end to a minority of device cells so as to provide a current generally proportional to the main device current, and a second auxiliary terminal connected at one end to the majority of device cells. The over-current detection circuit in this embodiment preferably comprises one branch connected between the first auxiliary terminal and a ground and in- cluding, in serial circuit, a bias-controlled transimpedance device such as a transistor and a resistor placed between the transimpedance device and the ground and providing a voltage at one end approximately proportional to the main device currentr and another branch connected between the second auxiliary terminal and the ground means and providing a bias current for the transimpedance device in the first branch.

t 1 The transimpedance device in the foregoing over-current detection circuit beneficially couples the currents from the high-potential-side first auxiliary node to the resistor that is at low potential. This permits such resistor to have a desirably low value such as specified below.

The above objects as well as other objects of this invention shall become readily apparent after reading the following description of the accompanying le) drawings, in which:

Fig. 1 is a schematic illustration partially in block diagram form providing an overview of the present invention as used in a so-called "H"bridge circuit.

is Fig. 2A is a schematic circuit diagram par- tially in block form of current switch S 1 and over-current detector 24 of Fig. 1.

Fig. 2B is a schematic illustration of an alternative current-sensing circuit that can be used in the over-current detector of Fig. 2A.

Fig. 3 is a simplified schematic of a multicellular current switch preferably used to implement switch S 1 in Fig. 1.

Fig. 4 is a block diagram of sub-circuits contained within gate override circuit 26 of Fig. 1-.

Fig. 5 is a schematic illustration partially in block form of a generalized form of the invention.

Fig. 6 is a schematic circuit diagram of another embodiment of the invention.

to In the drawingst, like reference numerals refer to like parts unless otherwise noted.

Figure 1 shows a general overview of the power delivery circuit of the invention as used in conjunction with an exemplary "H"-bridge circuit 10. The power delivery circuit of Fig. 1 additionally includes control circuitry 12 associated with H-bridge circuit 10.

Considering first H-bridge circuit 10, a load leg LO extends horizontally and contains a load 14, such as an electrical motor. Vertical leg Ll extends between left end node 16 of load leg L 0 and an upper node 18, which typically is at a 12-volt potential for automotive applications. Load leg L 2 extends is between node 16 and a node 20, typically at ground potential. Connected between a right end node 22 of load leg L 0 and an upper node 181 is load leg L3. Load leg L4 is connected between end node 22 and ground node 201.

The reference to "vertical" and "horizontal" orientations of the various legs of H-bridge circuit 10 are, of course, merely for descriptive purposes and may or may not accurately describe the layout of an actual Hbridge circuit.

As indicated by the phantom lines high potential nodes 18 and 181 are typically interconnected, and ground nodes 20 and 201 similarly are also interconnected.

Contained within load legs Ll to L 41 respectively, are current switches S, to S41 respectively.

t These switches are controlled by respective signals on their gates G 1 to G V As used herein, the term "gatew broadly encompasses any form of control lead for changing the switching state of a current switch. As such, 5 the term "gate" is intended to be synonymous with the "base" of a bipolar transistor, for example.

In order to direct current through load 14 in the direction shown by a curved arrow 25, appropriate signals are placed on gates G 1 and G 4 of switches S 1 and S 41 respectively, to turn such switches on, while appropriate signals are placed on the gates G 2 and G 3 of switches S 2 and S 31 respectively, to keep these switches off during this time. Conversely, to direct current through load 14 in the direction shown by curved arrow 27, switches S 2 and S 3 are made to conduct by appropriate control of their gates, while the other switches S 1 and S 4 are kept off during this time.

In order to prevent an over-current condition from destroying the load 14 or the switches S 1 and S 3 located in the high potential legs of Hbridge circuit 10 ("high side switches"), over-current detectors 24 and 30, shown as part of control circuitry 12, respond to electrical conditions in high potential legs L 1 and L 31 respectively. In a preferred arrangement, over-current detector 24 is responsive to electrical conditions within switch Sl, described below in connection with Figs. 2A and 3. - Continuing with Fig. 1, if an over-current condition is detected by detector 24, a gate override circuit 26 overrides a conventional gate control function 28 to assure that switches Sl and S4 remain off.

Similarly, upon detection of an over-current condition in switch S 3 by detector 30, a gate override circuit 32 prevents conventional gate control function 34 from turning on switches S 2 and S 3 Switch Si and over-current detector 24 are described in greater detail in Fig. 2A. Switch S 3 and over-current detector 30 are suitably of corresponding construction to switch S, and detector 24. Turning to Fig. 2A, switch Si is represented by a symbol for a MOSFET device, such as that sold by the present assignee under the trademark "HEXSense". The main load terminals of HEXSense device S 1 are illustrated as terminals 16 and 18. Terminal 16 is the main source terminal of switch S,, and terminal 18 is the sole drain terminal of the switch. Gate G 1 corresponds to gate G, of current switch S 1 of Fig. 1.

HEXSense device S, includes two auxiliary, further terminals 40 and 42. The interrelation of auxiliary terminals 40 and 42 to the main terminals 16 and 18 of switch S 1 is explained in connection with the schematic representation of switch S 1 in Fig. 3. Cells c 1 through C n' shown in Fig. 3, represent individual cells of HEXSense device S,, Common gate G, provides a common gate signal for the individual gates of cells c 1-Cn. Drain electrode 18 serves as a common drain electrode for all the cells C 1-Cn Source terminal 16 serves as a common source for a majority of the cells of switch S,, namely cells C 3-CnI while terminal 42 serves as an auxiliary source electrode connected in common with source electrode 16 except for minor metallization resistance (not shown). Auxiliary terminal 40 serves as a source electrode for only a minority of the cells of switch Sl, namely cells Cl_C2 In an actual device having several thousands or more cells, the auxiliary terminal 40 would serve as a source for perhaps several hundreds of cells.

HEXSense device S, is formed as one integrated circuit with each of its cells having similar characteristics to its other cells. For this reason, a current which flows from drain 18 to auxiliary source 40 is approximately proportional to the current that flows from drain 18 to main source 16, where such proportion is determined by the ratio of the minority number of cells connected to terminal 40 to the majority number of cells connected to terminal 16.

Further details of HEXSense device S, are contained in Power MOSFET Application Notes, No. AN-959, published by the present assignee in 1986, and incorporated herein by reference.

In view of the above description of the multi-cellular construction of switch Sl, it will be apparent to those skilled in the art that other types of multi-cellular switching devices could be used herein instead of a HEXSense device. By way of example, a multi-cellular thyristor device would comprise a suit- able replacement.

Returning to Fig. 2A, auxiliary terminals 40 and 42 are shown connected to a current-sensing circuit 43 comprising PNP bipolar transistors 44 and 46 and resistors 48 and 50. Current from switch S that flows t, J.

through auxiliary terminal 40 is conducted through a bias-signal controlled transistor 44 to cause a voltage p 1 11 drop across resistor 48. Neglecting the base current in transistor 44, the voltage drop across resistor 48 is proportional to the current flowing through termi nal 40 and, hence, to the load current flowing through terminal 16. The voltage at node 52 is thus propor tional to the load current. Transistor 44 functions as a transimpedance device to couple the current from the high potential side auxiliary node 40 to the low poten tial side resistor 48. This permits resistor 48 to have a desirably low value such as specified below.

Transistor 46 of circuit 43, having a short across its base and collector so as to function as a P-N diode, provides a bias current for the mirror cir cuit. Transistors 44 and 46 are preferably formed of matched silicon so as to have equal emitter-to-base turn-on thresholds.

Resistors 48 and 50 of the current-sensing circuit 43 are preferably, but not necessarily, select ed to result in equal currents through them when an over-current condition occurs in the load (at the over current trip point). A circuit designer can select resistors 48 and 50 so that the voltage at node 52 varies linearly with the load current according to the ratio of the number of cells in HEXSense switch S, connected to auxiliary terminal 40 to the number of cells in such switch connected to load 14. A circuit designer can, however, select resistors 48 and 50 so that the voltage at node 52 varies linearly with load current but according to a ratio differing from the foregoing ratio. Thus, a circuit designer can select resistors 48 and 50 to alter the relative change of - voltage at node 52 to the change of level of current in load 14.

Where the line voltage on node 18 (Fig. 2M is nominally 12 volts, PNP transistors 44 and 46 typi- cally each have a beta value of 200 and a breakdown voltage of 60 volts, and resistors 48 and 50 typically have values of 487 and 9.1K ohms, respectively. Additionally, a 0.001 or 0.01 microfarad capacitor 49 (shown in phantom) is preferably placed across resistor 48 to filter any potential current spikes during turnon. The voltage on node 52 of current-sensing circuit 43 is applied to input node 60 of a comparator 62, whose other input is a reference voltage level 64 selected to determine the over-current level. The output of comparator 62 is then processed by a 12-volt-to5-volt level shifter 66 so that further processing can conveniently occur with standard S-volt logic circuitry. When the voltage at node 60 exceeds that of reference level voltage 64, the comparator 62 provides an output, processed by voltage level shifter 66, which is applied to gate override circuit 26 described in connection with Pigs. 1 and 4. Current-sensing circuit 43 can be replaced by other types of circuits that provide a voltage at node 60 of comparator 62 that is approximately proportional to load current. A preferred alternative current-sensing circuit is illustrated in Fig. 2B as circuit 70. Like 30 circuit 43 of Fig. 2A, circuit 70 of Fig. 2B preferably includes two PNP bipolar transistors 44' and 461 and resistors 481 and SO'. Transistor 441 and resistor 48' of circuit 70 function in the same manner as the likenumbered elements of circuit 43 of Fig. 2A. An additional PNP bipolar transistor 72, however, is provided in association with transistor 461. The addition of transistor 72 causes circuit 70 to operate consistently regardless of wide variations in ambient temperature, and to somewhat improve consistency of operation when the supply voltage varies.

With the possible exception of matched-silicon transistors 44 and 46, both current-sensing circuits 43 and 70 (Figs. 2A and 2B) may be advantageously formed of inexpensive, discrete elements.

In current-sensing circuit 70, PNP transistors 4V, 46' and 72 preferably each have a typical beta value of 200 and a typical breakdown voltage of 60 volts, and resistors 481 and SO' preferably have values of 240 and 6. 5K ohms, respectively. Additionally, a shunting capacitor 49' (shown in phantom) across resis- tor 48' is preferably used to filter any potential current spikes during turn-on. Typical values are 0.001 or 0.01 microfarads.

In Fig. 4, gate override circuit 26, described above in connection with Fig. 1, is shown in more detail. Considering Fig. 4, an over-current signal from over-current detector 24, typically at a 5-volt level, may be provided to the reset terminal of a reset/set latch 80, which may be conventionally formed by tWo CMOS NAND gates (not shown). A signal applied to the reset terminal of latch 80 will override any signal from gate control function 28 which is sup- i 12 - plied to the set input of the reset/set latch 80 and which typically is a 5-volt signal from a microprocessor. The output of the reset/set latch 80 is then processed by a pre-driver circuit 82 to provide appropri- ate biasing signals for gates G 1 and G4 of switches S, and S 4 (Fig. 1), respectively.

The high potential side gates G 1 and G 3 are preferably provided with a biasing voltage of about 12 volts above the supply voltage, which may be generated with a conventional voltage-doubling circuit (not shown). This is in contrast to the low potential side gates G 2 and G4 which are preferably provided with a biasing voltage at the supply voltage level, typically 12 volts. Pre-driver circuit 82 cooperates with a counterpart pre-driver circuit (not shown) of gate override circuit 32 (Fig.;). to provide the foregoing biasing voltages. The foregoing pre- driver circuits can be designed as illustrated to have one logic input from latch 80 control switches S 2 and S 3 and the other logic input (not shown) control the other two switches. Alternatively, the pre-driver circuits can be designed to have one logic input toggle switches Sl, S21 or vice-versa; and to have the other logic input likewise toggle S 3 and S 4' Pre-driver circuit 82 and its counterpart (not shown) for switches S 2 and S3 can, further be designed to provide delay times to the control signals on gates Gl-G4 to insure that current is fully off in one direction through the load before causing current flow in the other direction. Alternativelyl gate control functions 28 and 34 (Fig. 1), typically implemented by a microprocessor, may provide such delay times.

Fig. 5 shows a more generalized form of the invention in which a single current switch S11 is placed on the high potential side of a load 141. The over-current detector.241, gate override circuit 26', and gate control function 281 correspond to the likenumbered parts shown in connection with the above-described power delivery circuit of the H- bridge type.

Fig. 6 shows still another embodiment of the invention in which all components similar to those of Fig. 2A have like identifying numerals. Fig. 6 differs from Fig. 2A in that resistor 90 is tied between the bases of transistors 44 and 46 and ground and the collector of transistor 46 goes directly to ground. The circuit of Fig. 6 has been found to experience varia- tions in current ratio with changes in voltage, current and transistor beta due to temperature change. These problems are largely avoided in the circuit of Fig. 2A. However, the circuit of Fig. 6 demonstrates the principle of operation of the circuits of Figs. 2A and 2B and is satisfactory for some applications. In the circuit of Fig. 6, resistor 48 may have a resistance of 1000 ohms and resistor 90 a resistance from 50K to 100 Kohms.

The foregoing describes a power delivery circuit for supplying load current to a load. The power delivery circuit includes an over-current detection circuit for detecting an over-current condition in -the load. The power delivery circuit of the invention may comprise the form of an Hbridge circuit for supplying current of selectable polarity to a load. Additionally described are accurate and reliable over-current detection circuits employing so-called current mirror concepts. The power delivery circuit of the invention can employ inexpensive and readily- available discrete components.

Although the present invention has been described in connection with a preferred embodiment thereof, many other variations and modifications will now become apparent to those skilled in the art. It is preferred, therefore, that the present invention be limited not by the specific disclosure herein, but only by the appended claims.

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Claims (10)

CLAIMS:

1. A power delivery circuit for supplying load current ' to a load, comprising:

a power node for connection to a source of electrical power; a load node for connection to a load; a high potential current path for supplying electrical current from the power node to the load node and including a current switch whose switching state is controlled by a control signal on an associated control terminal; a current detection circuit responsive to an electrical condition of the high potential current path and being for detecting the current level in the high potential current path; the current detection circuit comprising one branch connected between the first auxiliary terminal and a ground and including, in serial circuit, a resistor providing a voltage at one end approximately proportional to the main device current and a bias signal-controlled transimpedance device, and another branch connected between the second auxiliary terminal and the ground and providing a bias signal for the transimpedance device in the first branch.

2. The power delivery circuit of claim-1, further comprising current turnoff means for turning off the current switch in the high potential current path when the current detection circuit detects current in excess of a predetermined level in the high potential current path.

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3. The power delivery circuit of claim 1, wherein the current switch in the high potential current path comprises a multi-cellular device with a plurality of terminals, including a first main current terminal connected to the power means, a second main current terminal connecting a majority of device cells to a respective end node of the load leg, a first auxiliary terminal connected at one end to a minority of device cells so as to provide a current generally proportional to the main device current, and a second auxiliary terminal connected at one end to the majority of device cells; and wherein the current detection circuit is responsive to electrical conditions of the first and second auxiliary terminals.

4. The power delivery circuit of claim 1, which further includes a second transimpedance device in said other branch and coupled between said load node and said ground; said second transimpedance means pro- ducing a bias signal which is coupled to said bias signal-controlled transimpedance device.

5. A power delivery circuit of the H-bridge type including:

a load leg having two end nodes and means to connect to a load; power means for connection to a source of electrical power for supplying current to the load; ground means for providing a path for returning load current to the source of electrical power; 1 J 1 a first current path for supplying load cur- rent through the load in a first direction comprising a first high potential leg connected between the power means an a first end node of the load leg, and a first low potential leg connected between a second end node of the load leg and the ground means; and a second current path for supplying load cur rent through the load in a second direction comprising a second high potential leg connected between the power means and the second end node of the load leg, and a second low potential leg connected between the first end node of the load leg and the ground means; the high and low potential legs each includ ing a respective current switch whose switching state is controlled by a control signal on an associated con trol terminal; the power delivery circuit further comprising first and second current detection circuits responsive to electrical conditions in the first and second high potential legs, respectively. for detecting the current level in either of such legs; each current detection circuit comprising one branch connected between the first auxiliary terminal and the ground means and including in serial circuit, a resistor providing a voltage at one end approximate ly proportional to the main device current and a bias signal-controlled transimpedance device, and another branch connected between the second auxiliary terminal and the ground means and providing a bias signal for the transimpedance device in the first branch.

6. The power delivery circuit of claim 5, further comprising current turnoff means for turning off at least the current switch in the first or second high potential leg when the respective, associated current detection circuit detects current in excess of the predetermined level in such high potential leg.

7. The power delivery circuit of claim 5, wherein each current switch in the first and second high potential legs comprises a multi-cellular device with a plurality of terminals, including a first main current terminal connected to the power means, a second main current terminal connecting a majority of device cells to a respective end node of the load leg, a first auxiliary terminal connected at one end to a minority of device cells so as to provide a current generally proportional to the main device current, and a second auxiliary terminal connected at one end to the majority of device cells; and wherein each current detection circuit is responsive to electrical conditions of the first and second auxiliary terminals.

8. The power delivery circuit of claim 5, which further includes a second transimpedance device in said other branch and coupled between said load node and said ground; said second transimpedance means pro- ducing a bias signal which is coupled to said bias signal-controlled transimpedance device.

9. The power delivery circuit of claim 4, wherein said first and second transimpedance devices 1 ow 4 - 19 both comprise first and second bipolar transistors respectively, and which further includes a third bipolar transistor having its emitter and collector electrodes coupled between said common base connection and ground and having its base electrode connected to the node between the bipolar transistor and resistor in said second branch.

10. The power delivery circuit of claim 8, wherein said first and second transimpedance devices both comprise first and second bipolar transistors respectively, and which further includes a third bipolar transistor having its emitter and collector electrodes coupled between said common base connection and ground and having its base electrode connected to the node between the bipolar transistor and resistor in said second branch.

A power delivery circuit substantially as hereinbefore described with refernece to and as illustrated in figures 1-4, 5 or6.