GB2230670A - Extracting carriers - Google Patents

Abstract

In a method of extracting the two carriers of two A.M signals forming a composite input signal with only one tuning operation, one sinusoidal carrier is first extracted at 1 and mixed with the composite signal at 3 to generate a signal sin OMEGA beta t at the difference frequency between the two carriers which is then squared in a hard limiter 5 and further processed e.g. at 16, to derive a sinusoidal signal at the difference frequency which is combined at 7 (SSB generator) with the first carrier to derive the other carrier. The processing circuit may be a low-pass filter if the amount of residual modulation is acceptable or a multiple phase lock loop including a VCO 15, frequency discriminators 13, 24 and a controllable phase shifter 19 when residual AM modulation and time variant phase modulation are to be removed. The arrangement 16 enables the output of VCO 15 to be phase locked to output of limiter over a wide range of phase variations. Phase shifts within generator 7 may be compensated by a controlled phase shifter following mixer 23. One of the carriers is a strong signal and the other a weak signal. Alternative arrangements for the circuit 16 and the controlled phase shifter are disclosed. <IMAGE>

Description

Carrier extraction This invention relates to carrier extraction methods and circuits; it also provides a novel form of voltagecontrolled oscillator (VCO) circuit whose output frequency is determined by an input frequency from an external source, a novel form of phase-lock loop (PU) whose output phase is always fixed relative to that source irrespective of frequency, and a novel form of carrier extraction circuit using this PLL.

In our copenjing GB Appln No. 8705428 (Publn No.

2,187,907A), arrangements are described for suppressing interference between two amplitude-modulated signals. These involve the use of either one or two circuits for extracting the signal carrier frequencies, and a preferred form of extraction circuit, incorporating a VCO in a phase-lock loop, is described with reference to Fig 4 of that Application. Where only one such current is used no difficulty arises because tuning the VCO to approximately the required RF or IF frequency is reasonably convenient.

Where two such circuits are used it is still convenient to tune one to the signal of interest, but more difficult to tune the other to the unwanted signal. In effect, two receiver-tuning operations must be performed, instead of the usual single operation. This may present little difficulty to a skilled professional operator, but is more of a problem for the general user. In principle the second tuning operation can be made automatic once the first tuning is achieved, but in practice such an arrangement is complex and expensive. The present invention provides an extraction method and circuit which requires only one tuning operation but delivers both carrier frequencies simultaneously.

According to the present invention a method of simultaneously extracting the two carriers of two amplitudemodulated signals forming a composite input signal, comprises: extracting the sinusoidal carrier of one of said signals; mixing the extracted carrier with the composite input signal to generate a signal at a beat frequency equal to the frequency difference between the two carriers; hard-limiting said beat frequency signal to convert it to a square wave; processing said square wave to derive a sinusoidal waveform at said beat frequency; and combining said sinusoidal waveform with said extracted carrier by single-sideband generation to derive the carrier of the other of said signals.

The said processing of said square wave may comprise substantially only low-pass filtering.

Alternatively said processing of said square wave may comprise: applying said square wave to a phase-lock loop (PLL) which includes a voltage-controlled oscillator (VCO); and utilising said VCO output to provide said sinusoidal waveform for combination with said extracted carrier by said single-sideband generation.

Said square wave may be applied to said VCO via frequency-discriminator means arranged to deliver a zero control voltage to said VCO when the VCO output is at least approximately at said beat frequency.

The invention also provides a carrier extraction circuit arranged to extract the two carriers of two amplitude-modulated signals forming a composite input signal by a method as aforesaid, and also forms of VCO and PLL circuits suitable for use in a method as aforesaid.

The invention will now be described, by way of example, with reference to the accompanying drawings wherein: Fig 1 is a block-schematic circuit diagram of an embodiment of the invention; Fig 2 is a graph showing the frequency-discriminator characteristic obtained in the circuit of Fig 1; Fig 3 is a similar circuit diagram of a form of frequency discriminator suitable for use in the circuit of Fig 1; Fig 4 is a similar diagram of a phase-shift compensating circuit for use in the circuit of Fig 1; Fig 5 is a similar diagram of a phase-detector circuit for use in the circuit of Fig 4; Fig 6 is a similar diagram of an alternative form of phase-lock loop for use in the circuit of Fig 1; Fig 7 is a partially block-schematic diagram of a form of the circuit of Fig 6; Fig 8 is a circuit diagram of a trigger etc circuit for use in the circuit of Fig 7;; Fig 9 shows waveforms in the circuit of Pig 8; Fig 10 is a block-schematic diagram of a carrierextract ion circuit incorporating the circuits of Pigs 7 and 8; Fig 11 is a similar diagram of a version of Pig 1 substituting the circuits of Figs 7, 8 and 9 for parts thereof.

In Pig 1 a composite-input signal (RF or IF) is represented by b = a+=c (1) where a = a single = a (1 + kmcosQmt)sinDlt c = c sinQ2t ~ c (1 + kncosDnt)sinQ2t 1t and Q2t are the RF (radio frequency) or IF (intermediate frequency) phase angles of the stronger and weaker signals respectively Qmt and Qnt are the modulation phase angles of the stronger and weaker signals respectively km and k are the AM modulation indices of the stronger n and weaker signals respectively a and c are amplitudes of the stronger and weaker signals respectively.

This composite input signal is applied to a carrier extraction circuit 1, suitably of the kind disclosed in the aforesaid Fig 4, tuned to deliver single. The latter is fed via a 90O phase-shifter 2 to deliver cos#1t to a balanced mixer 3 which also receives the signal (1). After filtering in a low-pass filter 4, the product can be shown to be c(l+kncos#nt)sin#sst .....(2) where #ss = #2 - #1.

The signal (2) is an AM wave in which the beat frequency Qss replaces the original carrier Q2 of the weaker signal. Where the two original signals are in adjacent channels (no sideband overlap) as in the aforesaid Application, even the maximum possible value of fins viz as as defined by the spacing of the two channels, will be very different from Qss;; where they are co-channel (over lapping sidebands), the value of 9 can be comparable with n The The signal (2) is passed to an amplitude-limiter 5 of a type which converts the carrier to a square wave having zeros defined largely by Qss and removes most of the amplitude modulation Qn. . Such a "hard" limiter may be provided by a known circuit comprising a resistor in series with two oppositely-poled, parallel-connected diodes (not shown), which may be reverse-biased; the output is taken across the two diodes.Any residual amplitude-modulation, plus any time-variant phase-modulation caused by noiseproduced jitter in the zeros of Dss, are removed in the remainder of Fig 1, which also removes harmonics of the square wave produced by limiter 5.

Provided the amount of such residual modulations in the output of limiter 5 is acceptable, for use in the aforesaid Application its output can be fed to a low-pass filter 6 to remove the harmonics, and the filter output, sinQsst, fed direct to a single-sideband generator 7 where it is combined with single from extraction circuit 1 to deliver the required output sinQ2t. This is because in the adjacentchannel case Qss is sufficiently restricted in its possible range of values to allow filter 6 to be of simple low-pass, fixed-band design. For co-channel use, the larger range of values will generally disallow the use of such a design.

However, the arrangement shown in the remainder of Pig 1 is preferred, even for the adjacent-channel case, where the possible range of Qss values is fairly small.

The generator 7 referred to above can be of a known type, that shown comprising two multipliers 8 and 9 which respectively receive direct versions of sinQsst and single, and quadrature versions thereof obtained via 90" phaseshifters 10 and 11. The multiplier outputs are fed to either an addition or a subtraction circuit 12 depending on the connections of the direct and quadrature versions to the multipliers, as most easily determined in a known manner by experiment and/or calculation.

In the remainder of Pig 1, the output of limiter 5 is fed, not to filter 6, but to a frequency discriminator 13 which can operate over a range of Qss values from about 1/10 (max) to about Qss (max) as defined earlier. The DC output of discriminator 13 is connected to one input of a differential amplifier 14 whose output is connected via an addition circuit 40 to the control input of the VC0 15 of a carrier extraction circuit 16. Circuit 16 is of the kind described in the aforesaid Fig 4, but its components are designed to operate at the beat frequency Qss instead of at the carrier frequencies no Q1 or Q2. In addition to VCO 15, it comprises a balanced mixer 17 and a low-pass filter 18 connected therewith in a conventional phase-lock loop.The VCO output is fed to a voltage-controlled phase-shifter 19 controlled by the DC error signal from filter 18, and its output is fed to a balanced mixer 21 via a 900 phase-shifter 20. The second input to mixer 21 is taken from filter 4, and the output of mixer 21 is fed to a balanced mixer 23 via a low-pass filter 22. The second input to mixer 23 is obtained from phase-shifter 20, and the output of mixer 23 is sinQsst which is fed to single-sideband generator 7. The output of VC0 15 is also fed to a frequency discriminator 24 whose DC output forms the other input to amplifier 14. The DC outputs of filter 18 and amplifier 14 are added to form the control voltage for VCO 15.

The operation of circuit 16 itself is fully described in the aforesaid Application and will not be repeated here; the fact that the inputs to mixers 17 and 21 are now separated by filter 4 (for a reason to be explained) does not affect the operation. The discriminators 13 and 24 each have an approximately linear response as shown in Pig 2 at (i), for which graph the horizontal axis represents the input frequency to either discriminator. After subtraction in amplifier 14, their nett response is shown in Fig 2 at (ii), for which graph (parallel to (i)) the horizontal axis now represents the input frequency to discriminator 24 relative to a fixed input frequency to discriminator 13 represented by the origin (iii). It is seen that the nett output to VCO 15 is zero when the two discriminator inputs are of approximately the same frequency.

The above twin frequency-discriminator arrangement approximately aligns the output frequency of VCO 15 with the input frequency from limiter 5, in the face of a possible wide potential variation in Qss values, in order to facilitate more precise phase-locking of the VCO output by means of the fedback phase-lock loop in circuit 16. The time-responses of the detectors incorporated, as normal, in discriminators 13 and 24 are made fairly long, eg about 0.1 sec, whereas the time-responses within the circuit 16 are made shorter than this, eg by a factor 0.5 or less, so that the final phase-control of the sinQsst output from mixer 23 is by the circuit 16 and not by the discriminators. A preferred form of frequency discriminator will be described later.

If the difference between the free-running VCO frequency prior to locking and that of the signal from limiter 5 is always within the pull-in range of the phase-lock loop, the above twin frequency-discriminator arrangement, ie circuits 13, 14, 24 and 40, may be omitted.

The output sinQ2t of generator 7 is sensibly in phase with the original c term of equation (1) because the circuit 16 maintains the VCO 15 output in phase with the beat frequency from limiter 5 as stated above. However, a small phase-shift can be applied to the circuit 16 output, by means of a variable phase-shifter (not shown in Fig 1) connected between mixer 23 and the input to generator 7, to compensate for phase shifts within generator 7 itself, as described later in more detail.

In the interference-suppress ion arrangements of the aforesaid Application, an advantageous feature is that failure to extract the carrier still allows normal linear detection to take place. This is inherent in the RF or IF version of extraction circuit 16 as shown in Pig 4 of that Application (eg as for the present circuit 1), which does not produce any VCO output in the absence of an input to the extraction circuit. In the present invention this advantage is retained by feeding mixer 21 with the non-limited Qss from filter 4, instead of with the same input as mixer 17 as in the aforesaid Fig 4. If mixer 21 were also fed from limiter 5, then in the absence of a Qss signal the limiter would produce relatively high levels of noise which would tend to produce an unwanted output from VCO 15.

As regards the discriminators 13 and 24, any known form can be used. However, because of the low frequency, involved, and the desirability of using digital circuitry as far as possible, a preferred form is shown in Fig 3. The input signal Qss is fed to a squarer 25, suitably incorporating a pair of opposite-poled diodes; as discriminator 13 is already fed from limiter 5, a squarer 25 need only be included in discriminator 24. The resulting square waveform, of semi-period s/Qss, is differentiated in circuit 26 and has the resultant negative-going pulses removed by a unipolar clipping circuit 27. The positive-going pulses form one input to a binary counting stage 28. These pulses are also fed to a monostable flip-flop 29 which delivers a positive output pulse of fixed duration.The latter is inverted in circuit 30, differentiated in circuit 31 and has the resultant negative-going pulses removed by a clipping circuit 32 similar to circuit 27, whose output forms another input to stage 28. The binary stage output is thus a pulse, shown negative-going, whose duration is that of the output from flip-flop 29 and whose period is 2n/n,, ie inversely proportional to Qss. In effect the output from clipper 32 is delayed relative to that of clipper 27 by the period of flip-flop 29, thus providing the time-delay required to realise a frequency discriminator.The output of stage 28 is applied to a capacitor C1 and resistor R1 in series to establish a zero DC level as shown, and the positive-going amplitude h of the resultant waveform is measured by a peak voltmeter comprising diode D1, resistor R2 and capacitor C2.

The time-constant C2.R2 is made sufficiently long to prevent the detected DC voltage falling too far between input pulses to the peak voltmeter, eg about 0.1 sec as already mentioned. However, a time-constant sufficiently long to eliminate this "ripple" may be too long for satisfactory performance otherwise in Fig 1. Fortunately a substantial degree of ripple from each discriminator can be tolerated, since the two ripples are in phase and are effectively subtracted from one another in amplifier 14 to give nominally zero ripple at the zero-frequency point (iii) in Fig 2. R1 is made R2 so that C2 charges rapidly at the end of each negative-going pulse from stage 28. Thus as increases, the DC output across R2 (=h) also increases, as shown in line (i) of Fig 2.

A suitable circuit for VCO 15, capable of producing a sinusoidal output over a wide band, is the controllable Wien Bridge oscillator described in IEE Letters, 5 Jan 1989, page 19. If a VCO circuit producing a square or pulse output waveform is used, which is not preferred, a squarer need not be incorporated in discriminator 24.

The Fig 1 arrangement, as described, is more suitable for adjacent-channel use, because the value of Qss can then be reasonably well defined. This allows the filter 6, and the phase shifters 20 and 10, to be of fixed design. In principle, if Qss is known and fixed, circuit 15 could be replaced by a simple PLL, expecially if some form of automatic compensation were applied to compensate for errors in the phases of the beat-frequency and the RF or IF signals fed to circuit 7. In that case, even a less precise carrier extraction circuit than that described in the aforesaid Application could be used. Such an automatic compensation circuit will now be described, giving enhanced results mainly, but not exclusively, in adjacent-channel operation, and particularly where simpler forms of carrier and beatfrequency extraction circuits are used.

Such a compensation circuit has already been mentioned briefly, viz connecting a phase-shifter between mixer 23 and generator 7 to compensate for phase shifts within generator 7 itself. These can be caused by changes in the value of (= Q1-Q2) over the tuning range of Q1' relative to the design frequency of phase-shifter 10. This variable phaseshifter is shown at 33 in Fig 4. It can be controlled manually, but preferably is voltage-controlled automati cally, like phase-shifter 19 in circuit 16, the DC control voltage being obtained from the output of discriminator 13 as shown by the interrupted-line input connection in Fig 4.

For small tuning ranges of Q1' the latter may not change by a sufficient factor relative to the design frequency of phase-shifter 11 to require compensation. For larger ranges, simultaneous compensation for changes in both Q and Qss can be provided by the remainder of the Fig 4 circuit. In this, the sinQ2t output of generator 7 is mixed with single from extractor 1 in Fig 1 in a balanced mixer 34, whose output, via low-pass filter 35, is cos Qsst. The latter forms one input to a phase-detector 36 whose other input is sinQsst from mixer 23, and the DC output of detector 36 is connected to control phase-shifter 33 instead of the DC output of discriminator 13.When D1 is an IF frequency, and therefore fixed, this difficulty does not arise and it suffices to correct for changes in Qss as described in the preceding paragraph.

Fig 5 shows a suitable circuit for the phasedetector 36 in Fig 4, and is similar in operation to the frequency-discriminator circuit of Fig 3. One input, sinQsst in Fig 5, is applied to circuits 251, 261 and 271 in series, corresponding to circuits 25, 26 and 27 in Fig 3, the output of clipper 271 forming one input to a binary counting stage 281 (not shown) as in Fig 3. The other input, cosQsst in Fig 5, is applied to circuits 37, 38 and 39 corresponding in function to circuits 251, 261 and 271 respectively, and the unipolar pulses from clipper 39 are fed to stage 281. Thus the phase-detector 36 is similar to the frequencydiscriminator of Fig 3, minus the flip-flop 29 etc which provides the time-delay therein.The output of binary stage 281 is processed as in Fig 3, and the final DC output varies with the phase difference between the two inputs. This DC output controls phase-shifter 33 in Fig 4.

As stated, this more complex and expensive arrangement, requiring in particular the additional mixer 34, is only required where Qss can vary over a large tuning range. An alternative form of carrier extraction circuit, incorporating an alternative form of PLL, which can remove the need for such automatic phase-correction, is described with reference to Fig 6 et seq.

In the above description it is the RF carrier of the stronger signal to which the receiver is tuned, and which is extracted first, as RF or IP, by circuit 1, the remainder of Fig 1 being used to extract the carrier of the weaker signal automatically. Although this will usually be the easier tuning operation, occasions may arise when it is preferred to tune the receiver to the RF carrier of the weaker signal, and Fig 1 will function satisfactorily if the weaker signal is extracted first by circuit 1 instead.

It will be seen that the above-described embodiment of the present carrier-extraction invention uses a VCO circuit comprising a frequency-discriminator arrangement which delivers a zero control voltage to the VCO when the VCO output frequency is at least approximately equal to an external reference frequency applied to the discriminator arrangement. In the present embodiment this arrangement comprises the discriminators 13 and 24, the difference amplifier 14, and the VCO 15 connected as shown, the reference frequency being applied to discriminator 13 and the arrangement operating as described.This novel arrangement is preferred, but other frequency-discriminator/ VCO arrangements delivering a zero control voltage to the VCO at a given input frequency and VCO output frequency may be substituted, eg the quadricorrelator described by D Ruchman in Proc IRE, vol 42, pp 288-299, Jan 1954, and on page 87 of "Phase-Lock Techniques" 2nd Edition, by F M Gardner (John Wiley, 1979).

A disadvantage of the carrier extraction circuit 16 in Fig 1, as described, is that the phase-shifters 19 and 20 may sometimes need to operate over a wide frequency range.

This was not so in Appln No. 8705428, as operation there was at IF or, at most, over a limited RF range. In the present case, however, operation may be required over a beatfrequency range, in the co-channel case, of 10:1. For this reason the present invention also provides a novel form of carrier extraction circuit, utilising novel forms of phaselock loop. Some of these forms are applicable to any frequency range, ie IF, RF or beat, provided suitable components are available.

Fig 6 shows a form of PLL, usable at any frequency for which a VCO is available, which enables phase-shifter 19 to be omitted. In this loop, mixer 41 and VCO 42 correspond to mixer 17 and VCO 15, but LP filter 18 is replaced by LP filters 43 and 44 which both receive the output of mixer 41.

Filter 43 has a low-pass cut-off frequency no higher than 1/10 that of filter 44, and is followed by a phase inverter 45 whose output is added to that of filter 44 in adder 46.

The DC output of adder 46 provides the control input to VCO 42.

The inverted output from filter 43 would cause the loop to become unstable, but for the faster response of the output from filter 44. Phase-locking occurs through the mechanism of this faster response, but the stability point of locking is at zero input to VCO 42 because of the cancellation of the two filter outputs in adder 46. Hence the phase of the VCO output is always at 900 relative to the input to mixer 41 irrespective of the input frequency, ie variable phase-shifter 19 is no longer needed. This modification of the PLL circuit shown in Fig 4 of the aforesaid Application is preferred for all purposes, as cheaper and more effective, and can replace the PLL in extraction circuit 1.

There still remains the difficulty over phase-shifter 20. Fig 7 shows a form of Fig 6 for overcoming this difficulty, but is at present applicable only to relatively low, eg beat, frequencies because it uses digital circuitry which is difficult to realise at IF or EF.

In Fig 7 the input frequency is applied to a circuit 47 in which the input waveform (shown sinusoidal for the purposes of explanation) is squared, differentiated and unipolar clipped, as already described in relation to Figs 3 and 5.

The resulting pulses are fed to a binary counting stage 48 (cf circuit 28 in Fig 3). The other input to stage 48 is derived from VCO 421 via a squarer 50 and a differentiating and unipolar clipping circuit 51, omitting for the present the trigger etc circuit 52. The output of stage 48 is fed to two detector circuits comprising diode D3, resistor R3 and capacitor C3, and diode D4, resistor R4 and capacitor C4 respectively, arranged as shown.The time-constant R3.C3 (corresponding to filter 43) is much longer than the maximum beat period 2r/a,. The time-constant R4.C4 (corresponding to filter 44) provides a higher cut-off frequency, sufficient to reduce the ripple effect from the detection by D4, ie R3.C3 R4.C4. The inversion provided by circuit 45 is now obtained by the differential amplifier 49 which receives the two detector circuit outputs.

The operation of Fig 7 is seen to be similar to Fig 6, with the VCO output phase again at 900 relative to that of the input to circuit 47. However, by connecting circuit 52 between circuits 50 and 51, a phase-shift of 90" in the output of the VCO is obtained.

Details of circuit 52 are shown in Fig 8. Assuming that the square wave from circuit 50 goes between positive voltages v and E as shown in Fig 9(i), it is first applied to a differential amplifier 55 where the voltage v is subtracted so that its output goes positive from zero volts to E-v volts. If the output of circuit 50 already starts from zero volts, amplifier 55 is omitted. This zero-based square wave is applied to a diode D5 connected to a resistor R5 which is taken to a relatively high positive source, and to a capacitor C5 connected to earth. D5 is cut off when the square wave rises above zero, and C5 charges substantially linearly, from the source voltage ( > E-v) via R5, as shown in Fig 9(ii).The charging terminates, and C5 is discharged, when the square wave returns to zero. A steady DC voltage equal to e/4 is thereby obtained across a capacitor C6 connected in series with a resistor R6 across C5, where e is the peak amplitude of the ramp waveform in Fig 9(ii).

This DC voltage is multiplied by 2 in an amplifier 53 to provide the triggering level e/2 for a Schmitt trigger circuit 54 (ie one which produces an output pulse whose duration equals the time for which the triggering input exceeds the triggering level). The ramp waveform across C5 is applied as the triggering input to circuit 54. The resulting output is shown in Fig 9(iii) whose leading edge is halfway between the leading and trailing edges of the Fig 9(i) waveform, ie an effective 900 phase-shift has been obtained. (Incidentally, other phase-shifts can be obtained with the Fig 8 circuit by varying the gain (or the attenuation) of amplifier 53 appropriately.) This edgeshifted waveform is fed to circuit 51 to produce the second input to circuit 48 as before.The final result is a PLL in which (for the 90" shift described) the VCO output phase relative to the PLL input is 0 , instead of 90" as in a conventional PLL or in the PLL of circuit 16. Since the duration of the Fig 9(iii) pulse is not critical, a monostable flip-flop can alternatively be used for circuit 54.

Hence, for beat-type frequencies as in the present case, the circuit 16 of Fig 1 is preferably replaced by the circuit of Fig 7 incorporating the circuit of Fig 8, as shown at 161 in Fig 10. Since the input from limiter 5 in Fig 1 is already square, the circuit 47 in Fig 7 need only differentiate and clip in this case.

It will be seen that the combination of Figs 7 and 8 per se acts as a frequency-independent phase-shifter; however it cannot change its operating frequency quickly, since such rate of change is limited by the slower of the two time-constants, R3.C3, in the PLL.

The use of a Fig 7 circuit to produce a desired phase is shown in Fig 11, in which the upper part includes a circuit 161 (Fig 10) which replaces the circuit 16 in Fig 1 and the lower part replaces the 900 phase-shifter 10 in Fig 1; the latter is subject to the same frequency-range difficulty as phase-shifter 20. In Fig 11 the other upper components have the same reference numerals as in Fig 1 and detailed description is required; likewise as regards circuit 71 In the lower part of Fig 11 the Fig 7 circuit 1611 receives the same input from limiter 5 as the circuit 161.

The control voltage to the lower VCO 421 is obtained from an addition circuit 401 which receives the output of a differential amplifier 141. The inputs to the latter are from the (upper) frequency discriminator 13 and a frequency discriminator 241 connected to the output of VCO 421, producing the same effect as regards the output frequency of VCO 421 as do circuits 13, 14, 24 and 40 as regards VCO 42.

A mixer 2311 receives one input from the (upper) low-pass filter 22 and the other from VCO 421.

The Fig 7 circuit 1611 in the lower part of Fig 11 omits the Fig 8 circuit, and its VCO output is thus 90 out of the phase with its input from limiter 5, ie is cosQsst.

This output can thus be fed direct to multiplier 9, but it is preferred to feed it via mixer 231 as described, in order to obtain protection against an unlocked output from VCO 421 caused by the disappearance for any reason of the input to the PLL of which it forms part. This effect also applies to VCO 42 in circuit 161 and to VCO 15 in circuit 16 of Fig 1, and is protected against therein by the inclusion of circuits 21, 22 and 23. If the inputs to these PLL's disappear, the respective VCO's no longer have a locking signal and their output frequencies are liable to drift, giving subsequent spurious results. With the inclusion of these circuits, the output amplitude is always proportional to the PLL input amplitude, and hence if the latter goes to zero the output does likewise. This protection effect requires the time-response of the low-pass filter 22 to be shorter than that of the respective VCO within its loop; the latter is normally long anyway.

In Fig 11 the relationship between the loop timeresponses dependent on the low-pass filters 43 and 44 (Fig 6) in the PLL circuits 161 and 1611 and dependent on those of the frequency discriminators 13, 24 and 241 is significant. In order of decreasing speed these should be adjusted as follows: (1) dependent on filter 44, ie on C4.R4 in Fig 8: not less than about 10 cycles of the lowest value of Qss likely to be met; (2) dependent on discriminators 13, 24 and 24 * ie on C2.R2 in Fig 3: about 0.1 sec; (3) dependent on filter 43, ie on C3.R3 in Fig 8: several seconds.

Because Fig 11 avoids variations in phase-shift with changes in nip, the introduction of the variable phaseshifter 33 (Fig 4) is no longer necessary.

Claims (16)

Claims

1. A method of simultaneously extracting the two carriers of two amplitude-modulated signals forming a composite input signal, comprising: extracting the sinusoidal carrier of one of said signals; mixing the extracted carrier with the composite input signal to generate a signal at a beat frequency equal to the frequency difference between the two carriers; hard-limiting said beat-frequency signal to convert it to a square wave; processing said square wave to derive a sinusoidal waveform at said beat frequency; and combining said sinusoidal waveform with said extracted carrier by single-sideband generation to derive the carrier of the other of said signals.

2. A method as claimed in claim 1 wherein said processing of said square wave comprises substantially only low-pass filtering.

3. A method as claimed in claim 1 wherein said processing of said square wave comprises: applying said square wave to a phase-lock loop (PLL) which includes a voltage-controlled oscillator (VCO); and utilising said VCO output to provide said sinusoidal waveform for combination with said extracted carrier by said single-sideband generation.

4. A method as claimed in claim 3 wherein said square wave is applied to said VCO via frequency-discriminator means arranged to deliver a zero control voltage to said VCO when the VCO output is at least approximately at said beat frequency.

5. A method as claimed in claim 3 or claim 4 wherein said PLL forms the PLL in a method of providing said sinusoidal waveform comprising: applying said square wave to said PLL so that said VCO output is at said square-wave frequency; applying the DC error signal generated in the PLL to derive from said VCO output a modified output substantially in phase with said generated beat-frequency signal; mixing the modified VCO output with the generated beatfrequency signal before or after said hard-limiting thereof and detecting the product, and further mixing the DC detected product, after low-pass filtering, with said modified VCO output and detecting the product of said sinusoidal waveform for combination with said extracted carrier by said single side-band generation.

6. A method as claimed in claim 4 or in claim 5 as dependent on claim 4 wherein said frequency-discriminator means is arranged to deliver a DC control voltage to said VCO dependent on the difference between the DC outputs of frequency discriminators which receive said square wave and said VCO output respectively.

7. A method as claimed in any of claims 3 to 6 comprising controlling the phase of said derived sinusoidal waveform, before said combination by single-sideband generation, to compensate for any phase-change arising within said generator.

8. A method as claimed, in claim 7 as dependent on claim 6 comprising utilising the DC output of said frequency discriminator which receives said square wave to control said phase.

9. A method as claimed in claim 7 comprising: mixing said derived carrier of the other of said signals with said extracted carrier to generate a signal at said beat frequency; detecting the phase difference between said generated signal and said derived sinusoidal waveform; and utilising a DC signal corresponding to said phase difference to control said phase.

10. A carrier extraction circuit arranged to extract the two carriers of two amplitude-modulated signals forming a composite input signal by a method as claimed in any preceding claim.

11. A VCO circuit comprising: a VCO; a first frequency discriminator having an input connection for an input signal of given frequency and a DC output to one input of a differential amplifier; a second frequency discriminator having an input connection from the output of said VCO and a DC output to the other input of said differential amplifier; and a connection from the output of said differential amplifier to the control input of said VCO.

12. A circuit as claimed in claim 11 wherein said VCO is connected in a phase-lock loop.

13. A phase-lock loop circuit comprising: a mixer having a first input connection for an external input signal; a VCO having its output connected to a second input connection of said mixer; a connection from the mixer output to a first low-pass filter having a relatively slow response time; a connection from the mixer output to a second low-pass filter having a response time much faster than that of the first filter; and means for subtracting the output of the two filters and applying the difference to control the frequency of said VCO.

14. A method or circuit for extracting the two carriers of two amplitude-modulated signals forming a composite input signal substantially as hereinbefore described with reference to the accompanying drawings.

15. A voltage-controlled oscillator circuit having its output frequency aligned by frequency-discriminator means substantially as hereinbefore described with reference to Fig 1 or Fig 11 of the accompanying drawings.

16. A phase-lock loop circuit substantially as hereinbefore described with reference to Figs 6 to 10 of the accompanying drawings.