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GB2230116B - An improvement for pipelined decoding of instructions in a pipelined processor - Google Patents

An improvement for pipelined decoding of instructions in a pipelined processor

Info

Publication number
GB2230116B
GB2230116B GB9003351A GB9003351A GB2230116B GB 2230116 B GB2230116 B GB 2230116B GB 9003351 A GB9003351 A GB 9003351A GB 9003351 A GB9003351 A GB 9003351A GB 2230116 B GB2230116 B GB 2230116B
Authority
GB
United Kingdom
Prior art keywords
pipelined
instructions
improvement
decoding
processor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
GB9003351A
Other versions
GB2230116A (en
GB9003351D0 (en
Inventor
Beatrice Fu
Patrick P Gelsinger
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of GB9003351D0 publication Critical patent/GB9003351D0/en
Publication of GB2230116A publication Critical patent/GB2230116A/en
Application granted granted Critical
Publication of GB2230116B publication Critical patent/GB2230116B/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3818—Decoding for concurrent execution
    • G06F9/382—Pipelined decoding, e.g. using predecoding
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/22—Microcontrol or microprogram arrangements
    • G06F9/26—Address formation of the next micro-instruction ; Microprogram storage or retrieval arrangements
    • G06F9/262—Arrangements for next microinstruction selection
    • G06F9/268—Microinstruction selection not based on processing results, e.g. interrupt, patch, first cycle store, diagnostic programs
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
    • G06F9/30149—Instruction analysis, e.g. decoding, instruction word fields of variable length instructions
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
    • G06F9/3016—Decoding the operand specifier, e.g. specifier format
    • G06F9/30167—Decoding the operand specifier, e.g. specifier format of immediate specifier, e.g. constants

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Executing Machine-Instructions (AREA)
  • Advance Control (AREA)
GB9003351A 1989-04-07 1990-02-14 An improvement for pipelined decoding of instructions in a pipelined processor Expired - Fee Related GB2230116B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US33518689A 1989-04-07 1989-04-07

Publications (3)

Publication Number Publication Date
GB9003351D0 GB9003351D0 (en) 1990-04-11
GB2230116A GB2230116A (en) 1990-10-10
GB2230116B true GB2230116B (en) 1993-02-17

Family

ID=23310662

Family Applications (1)

Application Number Title Priority Date Filing Date
GB9003351A Expired - Fee Related GB2230116B (en) 1989-04-07 1990-02-14 An improvement for pipelined decoding of instructions in a pipelined processor

Country Status (5)

Country Link
JP (1) JP2847316B2 (en)
DE (1) DE4010895C2 (en)
FR (1) FR2645665B1 (en)
GB (1) GB2230116B (en)
HK (1) HK56295A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6230254B1 (en) 1992-09-29 2001-05-08 Seiko Epson Corporation System and method for handling load and/or store operators in a superscalar microprocessor
US6434693B1 (en) 1992-09-29 2002-08-13 Seiko Epson Corporation System and method for handling load and/or store operations in a superscalar microprocessor

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5438668A (en) * 1992-03-31 1995-08-01 Seiko Epson Corporation System and method for extraction, alignment and decoding of CISC instructions into a nano-instruction bucket for execution by a RISC computer
DE69425310T2 (en) * 1993-10-18 2001-06-13 Via-Cyrix, Inc. Micro control unit for a superpipeline-superscalar microprocessor
US5644741A (en) * 1993-10-18 1997-07-01 Cyrix Corporation Processor with single clock decode architecture employing single microROM
US5794026A (en) * 1993-10-18 1998-08-11 National Semiconductor Microprocessor having expedited execution of condition dependent instructions

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2059124A (en) * 1978-01-31 1981-04-15 Intel Corp Data processing system
EP0124402A2 (en) * 1983-03-31 1984-11-07 FAIRCHILD CAMERA & INSTRUMENT CORPORATION Microprocessor
GB2169115A (en) * 1984-12-29 1986-07-02 Sony Corp Method of operating microprocessors
EP0240606A2 (en) * 1986-03-27 1987-10-14 Kabushiki Kaisha Toshiba Pipe-line processing system and microprocessor using the system

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3629853A (en) * 1959-06-30 1971-12-21 Ibm Data-processing element
CA1174370A (en) * 1980-05-19 1984-09-11 Hidekazu Matsumoto Data processing unit with pipelined operands
US4574344A (en) * 1983-09-29 1986-03-04 Tandem Computers Incorporated Entry control store for enhanced CPU pipeline performance
US4812972A (en) * 1984-06-20 1989-03-14 Convex Computer Corporation Microcode computer having dispatch and main control stores for storing the first and the remaining microinstructions of machine instructions
JP2554050B2 (en) * 1986-02-26 1996-11-13 株式会社日立製作所 Data processing method
JPH0772863B2 (en) * 1986-10-30 1995-08-02 日本電気株式会社 Program counter relative address calculation method

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2059124A (en) * 1978-01-31 1981-04-15 Intel Corp Data processing system
EP0124402A2 (en) * 1983-03-31 1984-11-07 FAIRCHILD CAMERA & INSTRUMENT CORPORATION Microprocessor
GB2169115A (en) * 1984-12-29 1986-07-02 Sony Corp Method of operating microprocessors
EP0240606A2 (en) * 1986-03-27 1987-10-14 Kabushiki Kaisha Toshiba Pipe-line processing system and microprocessor using the system

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6230254B1 (en) 1992-09-29 2001-05-08 Seiko Epson Corporation System and method for handling load and/or store operators in a superscalar microprocessor
US6434693B1 (en) 1992-09-29 2002-08-13 Seiko Epson Corporation System and method for handling load and/or store operations in a superscalar microprocessor

Also Published As

Publication number Publication date
GB2230116A (en) 1990-10-10
JP2847316B2 (en) 1999-01-20
HK56295A (en) 1995-04-21
JPH03201030A (en) 1991-09-02
FR2645665B1 (en) 1994-04-15
DE4010895A1 (en) 1990-10-11
DE4010895C2 (en) 1998-09-24
FR2645665A1 (en) 1990-10-12
GB9003351D0 (en) 1990-04-11

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Legal Events

Date Code Title Description
PCNP Patent ceased through non-payment of renewal fee

Effective date: 20020214