GB2217108A

GB2217108A - Semiconductor device etching using indium containing etch stop

Info

Publication number: GB2217108A
Application number: GB8907074A
Authority: GB
Inventors: Tomonori Tanoue; Masayoshi Kobayashi; Chushirou Kusano; Tomoyoshi Mishima; Yoko Uchida
Original assignee: Hitachi Ltd
Current assignee: Hitachi Ltd
Priority date: 1988-03-30
Filing date: 1989-03-29
Publication date: 1989-10-18
Also published as: GB8907074D0; FR2629638A1; JPH01248524A

Abstract

A method of manufacturing a semiconductor device comprises a step of exposing an etching stop layer (5) containing indium by reactive dry etching using a gas containing a halogen element as a constituent element which is capable of selective etching with good controllability and high accuracy. A semi-conductor device which is manufactured using this method may be a Bipolar Transistor or a Field Effect Transistor, and may be a heterojunction device. <IMAGE>

Description

"A semiconductor device and a production method thereof The present invention relates to a semiconductor device and a production method thereof, and particularly to a thin film semiconductor device which is able to operate at high speed and a production method which is capable of manufacturing this semiconductor device with good control characteristics.

Conventional thin film semiconductor devices and production methods thereof are described in, for example, IEEE, Electron Device Letters, EDL-3 (1982), pp. 366 - 368.

In the above-described prior art, a base layer and an emitter layer are respectively formed by using GaAs and AlGaAs, and the AlGaAs alone is removed by wet etching using an HF solution so that the GaAs base is exposed.

The speed of etching of the AlGaAs layer with the HF solution greatly depends upon the Al content and the temperature conditions, and reproducibility is thus poor. In addition, there is a problem in that, since etching is effected in liquid, unstable conditions during agitation and so on cause non-uniform etching.

The dimensions of the device formed may also be inaccurate owing to the poor control characteristics, and thus it is virtually impossible to manufacture devices with a dimensional accuracy of 1 pm or less.

It is an object of the present invention to provide a method for manufacturing semiconductor devices which is capable of selectively etching with good control characteristics and high precision.

It is another object of the present invention to provide a semiconductor device which is able to operate at high speed with a high level of reliability and which has small dimensions.

The method of manufacturing semiconductor devices of the present invention is characterized by comprising a step of exposing an etching stop layer containing In by reactive dry etching using a gas containing a halogen atom or atoms as a constituent element.

In this method of manufacturing semiconductor devices, it is preferable that the etching stop layer comprises a semiconductor composed of a compound of elements in Groups III to V and that the In content is about 5% or more of the content of elements in Group III.

It has been thought that etching in a layer containing In would be stopped owing to the low vapor pressure of the In halide formed therein. Assuming that etching is stopped when the surface of the layer is covered with a monoatomic layer of In halide, and that the molecular dimensions of the In halide are the same as those of the area covered by the compounds of In with elements in Group V, a surface area equivalent in ratio terms to the ratio of the In component contained is covered with a monoatomic layer during the progress of etching for one monoatomic layer.With respect to defining the lower limit of the In content, if it is considered that etching is to be stopped within a thickness of 60 , it would be necessary for the In to be contained in about 20 atomic layers in an amount sufficient to produce one layer of In halide covering the surface, since the thickness of a monoatomic layer is about 3 . In other words, the ratio of the In component is the inverse of 20, i.e., about 5%. Since the actual molecular dimensions of the In halide are greater than what is described above, when a layer containing 5% of In is etched to a thickness of 20 to 30 , the etching stops. It is therefore preferable that the In content is about 5% or more.It will be apparent from the above description that when the requirements for the discontinuation of etching are less stringent, for example, when etching is to be allowed to progress to a thickness of about 100 , even a layer containing 5% or less of In is able to function as an etching stop layer.

The upper limit of the In content is determined by the critical film thickness which causes dislocation to form owing to non-conformity of a lattice. For example, when InGaAs is formed on GaAs, the critical film thickness is 10 , i.e., about 3 atomic layers, if the In content is about 80%. Although such a film thickness does not allow the etching stop layer to function properly, any increase in the film thickness causes the formation of dislocation and deterioration of the characteristics of the layer. In this case, therefore, the upper limit of the In content is 60%, i.e., a critical film thickness of about 15 A. When other materials are used, the upper limit of the In content is substantially equivalent to the value where the critical film thickness is 5 atomic layers or less.

A first semiconductor device in accordance with the present invention comprises a collector layer, a base layer and an emitter layer which each comprise a semiconductor layer composed of a compound of elements in Groups III to V and which are laminated in turn on a substrate. The emitter layer comprises a semiconductor of a type that is different from that of the base layer, as well as forming a hetero junction with the base layer. In the semiconductor device having a hetero junction bipolar transistor which is formed in a portion of the base layer by patterning using etching, a reactive dry etching stop layer containing In is also interposed between, at least, the base layer and the emitter layer.

A second semiconductor device in accordance with the present invention comprises a channel layer and a gate layer which each comprise a semiconductor layer composed of a compound of elements in Groups III to V and which are laminated in turn on a substrate. The gate layer comprises a sqmiconductor of a type that is different from that of the channel layer. In this semiconductor device which has a field-effect transistor formed in a portion of the channel layer by patterning using etching, a reactive dry etching stop layer containing In is interposed between, at least, the gate layer and the channel layer.

The present invention will now be described in greater detail by way of examples with reference to the accompanying drawings, wherein: Fig. 1 is a sectional view of a bipolar transistor in a first embodiment of the present invention; Figs. 2(a) to 2(c) are sectional views of a process of producing the bipolar transistor shown in Fig. 1; Fig. 3 is a sectional view of MISFET in a second embodiment of the present invention; Figs. 4(a) to 4(c) are sectional views of a process of producing the MISFET shown in Fig. 3; Fig. 5 is a sectional view of MISFET in a third embodiment of the present invention; and Fig. 6 is a sectional view of an example of conventional MISFET.

The In contained in an etching stop layer in the present invention reacts with gases which are generally used for dry etching and which contain as components halogen elements, such as fluoride gas, chloride gas, chlorine gas and the like, to form In halides. These reaction products are not easily etched, as compared with halides of elements in Groups III to V such as Ga, Al, As, Sb, P and so on, other than In.

The layer containing In thus functions as an etching stop layer for layers which are composed of compounds of elements in Groups III to V and which contain no In.

Example 1 Fig. 1 is a sectional view of a semiconductor device in the first embodiment of the present invention, and Figs. 2(a) to 2(c) are sectional views of a process of producing-this semiconductor device.

In the drawings, reference numeral 1 denotes a semiinsulating GaAs substrate; reference numeral 2, an N-type GaAs sub-collector layer; reference numeral 3, an N-type GaAs collector layer; reference numeral 4, a P-type GaAs base layer; reference numeral 5, an undoped In Ga gAs etching stop layer, reference numeral 6, an N-type Alo 3GaO 7As emitter layer; reference numeral 7, an N-type GaAs cap layer; reference numeral 8, a collector electrode; reference numeral 9, an emitter electrode; and reference numeral 10, a base electrode.

The structure of the semiconductor device is characterized by having the etching stop layer 5 containing In between the GaAs base layer 4 and the Al O.3Ga7As emitter layer 6. As the etching stop layer 5 contains In as a constitutive component, the speed of reactive dry etching in- the etching stop layer 5 using an etching gas such as C12, CC12F2, HC1 or the like, which contains a halogen element such as chlorine, fluorine or the like, is 1/100 or less that of GaAs or AlGaAs.

The method of manufacturing the semiconductor device shown in Fig. 1 is described below with reference to Figs. 2(a) to 2(c).

As shown in Fig. 2(a), on the semi-insulating GaAs substrate 1, the Si-doped (concentration of impurities, 5 x 1018/cm ) GaAs sub-collector layer 2 having a thickness of 5000 A, the Si-doped (5 x 1016/cm3) GaAs collector layer 3 having a thickness of 3000 A, 19 3 the Be-doped (4 x 1019/cm ) GaAs base layer 4 having a thickness of 300 , the undoped In 0.1Ga0.9 gAs etching stop layer 5 having a thickness of 30 A, the Si-doped 17/cm ) A10. 3Ga0.7AS emitter layer 3 (5 x 10 7/cm ) Al0.3Ga0.7As emitter layer 6 having a 18 3 thickness of 1000 and the Si-doped (5 x 10 /cm ) GaAs cap layer 7 having a thickness of 1000 A are in turn subjected to epitaxial crystal growth by a molecular beam epitaxial method or a metal organic chemical vapor deposition method. The cap layer 7 is provided for the purpose of reducing contact resistance produced when the electrode 9 is subsequently connected thereto.

The thickness of the etching stop layer is preferably less than the critical thickness which would lead to the formation of dislocation in this layer. For example, in the case of in ,GaO.gAs, the thickness is 500 A or less.

The Alo 3GaO 7As emitter layer 6 and the GaAs cap layer 7 are selectively removed by etching utilizing normal photolithography and a reactive ion etching method whereby the etching stop layer 5 is exposed, as shown in Fig. 2(b). The ratio of the etching speeds is 1 : 100 or more. The emitter electrode 9 composed of an AuGe alloy is then deposited on the cap layer 7 (after the electrode 9 has been provided, the layers 6, 7 may be dry-etched using the electrode 9 as a mask in a self-aligning manner).

As shown in Fig. 2(c), the layers 2 to 5 are then selectively dry-etched. The base electrode 10 composed of an AuZn alloy is then deposited on the etching stop layer 5 so that electrical contact with the base layer 4 having a very small thickness (300 A) can be obtained with good reproducibility and low resistance. Furthermore, InGaAs has the advantage that it has a narrower band gap than that of GaAs and can thus easily form ohmic contact. In this way, since the etching of the emitter layer using dry etching enables the thin base layer to remain, a transistor with micro-scale dimensions can be formed. Although not shown in the drawings, the collector electrode (denoted by reference numeral 8 in Fig. 1) composed of an AuGe Alloy is deposited on the exposed GaAs subcollector layer 2.

When a transistor having an emitter region with dimensions of 0.8 pm x 1.0 pm was manufactured in accordance with this embodiment, the yield of the diode (comprising the layers respectively denoted by reference numerals 10, 5, 4, 6, 7 and 9) between the emitter and the base was about 70% of the whole of a 3-inch wafer in terms of surface area, which was substantially the same yield as in the manufacture of a transistor having dimensions of 10 pm x 10 pm using prior art methods.

On the other hand, when a conventional wet etching process using a HF solution was used, the yield in the case of emitter dimensions of about 2 pm x 3 pm was about half that in the case of a large area (10 pm x 10 pm), and a transistor with dimensions of 0.8 pm x 1 pm did not operate. In a conventional structure without any InGaAs layer 5, when the base layer 4 was exposed by controlling the etching amount (time), although the results obtained when the thickness of a base layer was 1000 or more were the same as what obtained with this embodiment, the yields decreased to 30%, 8% and 0.2% as the thickness of the base layer was C O O reduced to 600 A, 300 A and 200 A, respectively, regardless of the size of the emitter area.This is because part of the AlGaAs layer 6 remains unetched ("underetching") owing to the distribution of the film thicknesses that occurs during the growth of crystals, as well as dispersion during etching, whereby the formation of ohmic contact is inhibited, or because a very thin base layer is etched ("overetching") which prevents the above-described diode from being properly formed. Even when the base layer has a thickness of 200 A, the present invention prevents any decrease in yield owing to the effect of the etching stop layer 5.

The results of high frequency measurements of the transistor shown in Fig. 1 revealed a cut off frequency (fT) of 65 GHz and a maximum oscillation frequency (fmax) of 42 GHz. These values are greater than fT = 40 GHz and fmax = 25 GHz, the values exhibited by a conventional transistor having a base layer thickness of 1000 and to InGaAs etching stop layer.

This is due to the reduction in base contact resistance owing to the formation of the InGaAs layer and the reduction in base transit time owing to the reduction in the base layer thickness.

Example 2 Fig. 3 is a sectional view of the second embodiment of the present invention, and Figs. 4(a) to 4(c) are sectional views of the process of manufacturing the device.

In the drawings, reference numeral 101 denotes a semi-insulating GaAs substrate; reference numeral 102, a highly pure GaAs buffer layer; reference numeral 103, a N-type GaAs channel layer; reference numeral 104, an undoped In Ga gAs etching stop layer; reference numeral 105, an undoped or N-type Al 3Ga0.7As gate layer; reference numeral 106, a gate electrode; reference numeral 107, a source electrode; and reference numeral 108, a drain electrode.

A description will now be given of the method of manufacturing the semiconductor device shown in Fig.

3 with reference to Figs. 4(a) to 4(c).

The GaAs buffer layer 102 having a thickness of 1000 and high purity (Si concentration less than 15 3 1 x 1015/cm3), the GaAs channel layer 103 having a thickness of 200 and a Si concentration of 2 x 1018/cm3, the undoped InO lGa0 gAs etching stop layer 104 having a thickness of 20 A and the Alo 3Ga0 7As gate layer 105 having a thickness of 200 A and a Si 18 3 concentration of 2 x 10 /cm or less were first laminated on the semi-insulating GaAs substrate 101 by a molecular beam epitaxial method or metal organic chemical vapor deposition method (Fig. 4(a)).

After the portion serving as a gate region had been then protected by a photo resist film (not shown) using normal photolithography, etching was effected by reactive ion etching using C12 gas to expose the etching stop layer 104. During this etching process, the ratio of etching speeds between the etching stop layer 104 containing In and the AlGaAs gate layer 105 was 1 : 500 or more (Fig. 4(b)).

The gate electrode, the source electrode and the drain electrode were then deposited on these layers and then processed by normal photolithography to obtain the element shown in Fig. 4(c). The processing of the gate region may be of course carried out by first forming the gate electrode and then performing dry etching using the gate electrode as a mask in a selfaligning manner.

The thus-formed transistor comprised an element which had a gate length of 0.5 pm and a distance between the source and the gate of 1 pm and which exhibited a source resistance of 0.5 Q mm and mutual conductance (gm) of 550 mS/mm.

As shown in Fig. 6, in a conventional method without using selective etching, ions of N-type impurities are implanted in portions below the source and drain electrodes 107, 108 and then subjected to heat treatment at a high temperature (7500C or higher) to form electrode regions (source and drain regions) 113. In this case, however, since the AlGaAs layer 105 is present between the electrodes 107 and 108 and the channel layer 103, the contact resistance is increased and thus the source resistance is above 1 Q mm. In addition, selective etching using wet etching is impossible in the case of a gate length of 0.7 pm or less.

Example 3 Fig. 5 is a sectional view of the third embodiment of the present invention.

In the second embodiment, the gate layer 105 was processed by reactive dry etching using the gate electrode 109 as a mask in a self aligning manner to expose the etching stop layer 104. An insulating film was then formed on the etching stop layer 104 and then subjected to anisotropic etching to form insulating film side walls 110 in the gate portions (the gate electrode 109 and the gate layer 105). Silicon oxide, silicon nitride, aluminium nitride or the like can be used as a material for the insulating film side walls 110.

18 18 3 Si-doped (1 x 10 to 5 x 10 /cm ) GaAs layers 111, 112 are then subjected to selective crystal growth in the source and drain electrode regions. Source and drain electrodes (not shown) are then formed on the GaAs layers 111, 112, respectively, in the same manner as in the second embodiment to obtain MISFET. In this case, the distance between the source and drain electrodes is substantially determined by the width of each of the insulating film side walls 110 and can be reduced to about 0.1 pm at minimum. The source resistance can thus be reduced to 0.1 Q mm.

Although the above description concerns a GaAs/AlGaAs system alone, FET bipolar transistors and so on can be manufactured by using other semiconductors of compounds of elements in Groups III to V such as GaSb, AlSb, GaP and the like, in which a layer containing In is inserted so as to function as an etching stop layer. The film thicknesses described above in the embodiments are just examples, and the film thickness can be of course freely selected within a range which is suitable for high speed operation of usual trans is tors. If the In content in the layer containing In is 5% or more of the total number of the atoms used in Group III, it is possible to obtain a satisfactory ratio of selective etching. If the In content is increased, however, since the lattice constants are changed, the composition of the elements in Group V or III must be changed for the purpose of compensating for this change, or the thickness must be selected to be less than the critical film thickness which causes the formation of defects such as dislocation and the like owing to lattice unconformity.

As described above, the present invention enables the surfaces of thin films composed of compounds of elements in Groups III to V to be easily exposed with good control characteristics, and thus has an effect of reducing the transit time of carriers and reducing the series resistance.

Claims

CLAIMS:

1. A method of manufacturing a semiconductor device comprising the step of exposing an etching stop layer containing In by reactive dry etching using a gas containing a halogen element as a constituent element.

2. A method of manufacturing a semiconductor device according to Claim 1, wherein said etching stop layer is composed of a semiconductor of a compound of elements in Groups III to V, the In content being within the range of about 5% to 60% of said elements in Group III.-

3. A method of manufacturing a hetero junction bipolar transistor comprising the steps of:: forming a collector layer on a substrate; forming a base layer on said collector layer; forming an etching stop layer on said base layer; forming an emitter layer on said etching stop layer; exposing said etching stop layer by etching of a given region of said emitter layer by reactive dry etching using a gas containing a halogen element as a constituent element; exposing said collector layer by etching a given region of said etching stop layer; forming an emitter electrode on said emitter layer; forming a base electrode on said etching stop layer; and forming a collector electrode on said collector layer.

4. A method of manufacturing a hetero junction bipolar transistor comprising the steps of: forming a collector layer on a substrate; forming a base layer on said collector layer; forming an etching stop layer containing In on said base layer; forming an emitter layer on said etching stop layer; forming an emitter electrode on said emitter layer; exposing said etching stop layer by etching said emitter layer by reactive dry etching using said emitter electrode as a mask and a gas containing a halogen element as a constituent element; exposing said collector layer by etching a given region of said etching stop layer; forming a base electrode on said etching stop layer; and forming a collector electrode on said collector layer.

5. A method of manufacturing a hetero junction bipolar transistor according to Claims 3 and 4, wherein said etching stop layer is composed of a semiconductor of a compound of elements in Groups III to V, the In content being within the range of 5% to 60% of said elements in Group III.

6. A method of manufacturing a hetero junction bipolar transistor according to Claims 3 and 4, wherein each of said collector layer and said base layer is composed of a semiconductor of a compound of elements in Groups III to V.

7. A method of manufacturing a semiconductor field-effect transistor comprising the steps of: forming a buffer layer on a substrate; forming a channel layer on said buffer layer; forming an etching stop layer containing In on said channel layer; forming a gate layer on said etching stop layer; exposing said etching stop layer by etching a given region of said gate layer by reactive dry etching using a gas containing a halogen element as a constituent element; forming a gate electrode on said gate layer; and forming a source electrode and a drain electrode on said etching stop layer with said gate layer held therebetween.

8. A method of manufacturing a compound semiconductor field-effect transistor comprising the steps of: forming a buffer layer on a substrate; forming a channel layer on said buffer layer; forming an etching stop layer containing In on said channel layer; forming a gate layer on said etching stop layer; forming a gate electrode on said gate layer; exposing said etching stop electrode by etching said gate layer by reactive dry etching using said gate electrode as a mask and a gas containing a halogen element as a constituent element; forming insulating films on the side walls of the gate portion comprising said gate layer and said gate electrode; and forming a source electrode and a drain electrode on said etching stop layer with said gate portion held therebetween.

9. A method of manufacturing a compound semiconductor field-effect transistor according to Claims 7 and 8, wherein said etching stop layer is composed of a semiconductor of a compound of elements in Groups III to V, the In content being within the range of 5% to 60% of said elements in Group III.

10. A method of manufacturing a compound semiconductor field-effect transistor according to Claims 7 and 8, wherein said channel layer is composed of a semiconductor of a compound of elements in Groups III to V.

11. A semiconductor device comprising: a substrate; a collector layer disposed on said substrate and having a first conducting type; a base layer disposed on said collector layer and having a second conducting type; an etching stop layer containing In and disposed on said base layer; an emitter layer disposed on said etching stop layer and comprising a semiconductor which has said first conducting type and is a different type from said base layer, and which is capable of forming hetero junction with said base layer; an emitter electrode disposed on said emitter layer; a base electrode disposed on said etching stop layer; and a collector electrode disposed on said collector layer.

12. A semiconductor device according to Claim 11, wherein said etching stop layer comprises a semiconductor of a compound of elements in Groups III to V, and the In content being within the range of 5% to 60% of said elements in Group III.

13. A semiconductor device according to Claim 11, wherein each of said collector layer and said base layer comprises a semiconductor of a compound of elements in Group III to V.

14. A semiconductor device comprising: a substrate; a buffer layer disposed on said substrate; a channel layer disposed on said buffer layer; an etching stop layer containing In and disposed on said channel layer; a gate layer disposed on said etching stop layer and comprising a semiconductor different from said channel layer; a source electrode and a drain electrode disposed on #said etching stop layer with said gate layer held therebetween; and a gate electrode disposed on said gate layer.

15. A semiconductor device according to Claim 13, wherein said etching stop layer comprises a semiconductor of a compound of elements in Groups III to V, the In content being within the range of 5% to 60% of said elements in Group III.

16. A semiconductor device according to Claim 13, wherein said channel layer comprises a semiconductor of a compound of elements in Groups III to V.

17. A semiconductor device substantially as herein described with reference to and as illustrated in the accompanying drawings.