GB2202661A - Gas plasma display - Google Patents

Description

41 - 1.

" 1 - P503OGB/ALMMf Description of Invention

2202661 "Improvements in or relating to a gas plasma display" THIS INVENTION relates to a DC gas plasma display panel system for use with a personal computer using,a multi-dot pixel arrangement which may be controlled in a manner to vary the intensity or shading of an active pixel.

Conventional DC plasma display technology includes a display panel comprising two glass plates having conductor arrays which are orthogonally positioned. These conductor arrays are encapsulated in a gas envelope, with the intersections of these arrays forming gas cells. To illuminate the gas cells, the row electrodes are scanned sequentially, one at a time. If a corresponding column electrode is energized, a voltage which exceeds the ionization potential of the gas is generated at the intersection and a gas discharge occurs.

AC gas plasma panels are also available and have been used in the past. The AC plasma panels differ from the DC plasma panels in that AC plasma panels utilise essentially 3 signals for display purposes (i.e. write, sustain and erase). The AC plasma panels are capable of maintaining an image on the screen with the use of a sustain voltage without a continous address to the pixels to be illuminated. In contradistinction the DC plasma panels will sustain an image on the screen only as long as the pixels to be illuminated are addressed.

Due to the nature of gas plasma display it has long been accepted to use a 2 x 2 dot array (i.e. four intersections or four dots) to form a single pixel in the low resolution graphics mode.

Prior art gas plasma devices have not been capable of producing shades. The prior art devices in essence have had one intensity level. The pel was thus illuminated when the data bit was true and extinguished when the data bit was zero.

The possibility of varying the intensity of a gas plasma display panel was discussed in "An AC Plasma Operating AS the CRT Video Display For an IBM PW by Criscimagna et al. Criscimagna suggests that highlighting be accomplished by dimming the pels which are to be highlighted. Criscimagna accomplished this by reducing the pels to half- brightness by skipping alternate frames, and controlling the anticipated flicker by a type of two-axis interlace. Criscimagna suggests that the pels of a character are to be dimmed, by interlacing the scan lines. Criscimagna suggests displaying even pels on even sweeps and odd pels on odd sweeps for even frames. For odd frames Criscimagna suggests displaying the odd pels on the even sweeps and the even pels on the odd sweeps.

It is an object of this invention to provide an improved gas plasma display panel controller and a display panel which are capable of displaying various shades by varying the manner in which the dots forming a panel are arranged and by alternating, at a frame rate, the illumination of the dots normally comprising an active pixel. This alternation of dots results in a apparent shade by "sparkling" the dots making up the pixel. The various shades which may be achieved are displayed in response to the colour attribute which is resident in the application software typically run on these types of personal computers.

j - i According to this invention there is provided a gas plasma display comprising: a gas plasma display panel; display logic incorporated in an integrated display controller (gate array); a character generator operatively connected to the gate array; a video memory operatively connected to the gate array; a conversion PROM operatively connected to the gate array wherein the integrated display controller is operatively connected to the display panel and video memory wherein said controller maps a pixel into a four dot display matrix when the panel is in a low resolution graphics mode, and said four dot matrix is used to vary the apparent intensity of the pixel by varying the display sequence and pattern of the dots which form the pixel.

Preferably the pixel display intensity and shading is varied by the setting of two global software bits.

According to another aspect of this invention there is provided a gas plasma display compatible with software written for colour monitors and other monochrome monitors comprising: a gas plasma display panel; a video memory; and an integrated display controller operatively connected to the display panel and video memory wherein said controller deciphers the colour attribute and selectively illuminates a four dot display matrix for each pixel to be displayed wherein the colour attribute resident in software is used to vary the intensity of the pixel which is displayed.

Preferably the shading of the pixel is varied by alternating the dots which are illuminated for a given pixelg said dots being alternately illuminatd on alternate scan lines for alternate frames which are displayed.

According to a further aspect of- the invention there is provided a gas plasma display compatible with software written for colour monitors and other monochrome monitors comprising: a gas plasma display panel; a video memory; and an integrated display controller operatively connected to the display panel and video memory wherein said controller deciphers the colour attribute written in software and selectively illuminates a four dot display matrix to provide apparent shades of intensity on the monitor, said apparent shades of intensity being produced by alternating the pattern of illumination of a four dot matrix for the pixels which are active.

Preferably the apparent shades of intensity are provided by alternating the dots which are illuminated for the active pixels, said dots being alternately illuminated on alternate scan lines for alternate frames which are displayed.

Conveniently the frames are changed at a rate of 60 times a second, or preferably the frames are changed at a rate of 50 times a second to be more compatible with equipment available in the United Kingdom.

A further embodiment of the present invention provides a gas plasma display panel which is capable of displaying graphics of various shades. The graphics of various shades are displayed in response to a custom gate array controller which is capable of interpreting the colour attribute resident in software and implementing a character sparkle controller which gives the appearance of a different shade by discretely alternating the illumination of the four dots which comprise a single pixel. 1 Preferred embodiments of the present invention have compatibility with IBM computer colour graphics adapter (CGA) and monochrome display adapter (MDA) while at the same time displaying information on a gas plasma t - 57 panel.

Thus the invention may be considered to provide a method of achieving compatibility with the CGA and monochrome display modes without the necessity of rewriting applications software which was written for personal computers which used a CRT display in lieu of the gas plasma display panel.

In order that the invention may be more readily understood, and so that further features thereof may be appreciated the invention will now be described by way of example with reference to the accompanying drawings, in which:

Figure 1 is a block diagram of the video controller board of the preferred embodiment of the present invention; Figure 2 is a partial connection diagram of the gate array and the video random access memory of the preferred embodiment of the present invention; Figures 3A and 3B is a partial schematic of the logic circuit for the low resolution graphics (i.e. 320 x 200) gas plasma mode of the preferred embodiment of the present invention; and Figure 4 is a partial schematic of the logic circuit for counting even and odd display frames in the preferred embodiment of the presnet invention.

The display panel in the preferred embodiment is a 640 by 400 dot DC gas plasma display panel. The display panel is operatively coupled to a display controller board consisting of a custom gate-array, a display memory RAM, a character generator RAM or ROM and a fakeout 6 parameter PROM. The display controller provides compatibility with the IBM PC display modes (or compatibles built to this PC standard) as well as allowing the option of extending the modes by reprogramming the hardware. The interconnection of the various components is illustrated in Figure 1.

The preferred embodiment of the present invention is designed to support a dual-mode plasma display for both text and graphics. The display controller can drive the plasma display emulating either a monochrome display adapter (MDA) or a colour graphics adapter (CGA). Additionally the display controller disclosed herein can support an external colour CRT as a CGA monitor.

A custom gate array controller provides all timing and control for the display controller board and plasma display panel. Functional schematics of the custom gate array controller are provided in APPENDIX A. The sche1 matics provided in APPENDIX A are incorporated by reference as if set forth in full herein.

In the preferred embodiment of the present invention the display controller board has 32 Kbytes of video memory on board and also contains a RAM-based character generator. The RAM-based character generator allows software to load and to display alternate character sets. In the alternative the standard character set can be loaded into 10 RAM from the character "look-up" tables resident in the BIOS stored in the system ROM.

To achieve a plasma display with similar features to the customary CRT display with standard applications' software written for the CRT display; the display controller in the present invention contains a CRT/plasma conversion programmable read-only memory (PROM) (also referred to as a "fakeout" PROM) that makes the differences between the plasma panel and the CRT transparent to 20 the applications software.

Referring now to FIG. 1, the following major components are illustrated:

1. 2. 3. 4.

Gate array controller Video display memory (RAM) Character-generator memory (RAM) CRT/plasma conversion PROM As is illustrated in FIG. 1 the display controller may be used to drive either a CRT monitor or a gas plasma_ display. The interconnection between the display con troller and the plasma panel is by means of a 20-pin signal connector. The control, address and data busses interface between the central processing unit (CPU) and the display controlle;r is by means of a 50-pin bus con- nector. Interconnections between the CPU, the display controller components, and the plasma panel are more fully set forth in the schematics attached hereto as APPENDIX B. The schematics provided in APPENDIX B are incorporated 5 herein by reference as if set forth in full herein.

A 64K x 4 dynamic RAM (DRAM) on the display controller board is used to provide the 32 Kbytes of display memory. The DRAM is addressed serially, 8 bits at a time in two 4-bit nibbles, so that display memory is organized as 32K x 8 array. The video controller is capable of operating in either the extended-mode or the normal mode. The extended mode is accomplished by setting the mode select register. In this mode the full 32 Kbytes of display memory are available. With the extended-mode bit reset only half of the display memory is effectively used. Therefore the display memory is dual-mapped in blocks of 16 Kbytes.

Referring again to FIG. 1, the character generator is an 8K x 8 bit,.high-speed static RAM, containing both a main character set and an alternate character set. The character sets are loaded into RAM by the system BIOS at power-up. The character-generator RAM is accessed by software by setting a bit of the Extended Mode Select register and addressing the video RAM address. The character-generator RAM contains only two character sets at any one time (e.g., the main character set and the alternate character set). The main character set is always used; the alternate character set can be used for highlighted characters if the alternate character set mode is selected in the Extended Mode Select register., There is also a capability for reprogramming the character sets. The main and alternate character sets are displayed in both the plasma character cell format and the C\ CRT character cell format. The character sets must be reloaded whenever the display is switched between the internal plasma mode and the external CRT mode. This character set reload is accomplished by software instruc5 tions to the gate array controller which may be initial ized at the time the display type is selected (or the selection of the display type is changed).

In the plasma mode, an 8 x 16-character cell format is used in the 80 x 25 (CGA and MDA) text mode and the 40 x 25 (CGA) text mode. An 8 x 8-character cell format is used when the plasma panel is in the 80 x 40 (CGA and MDA) and 80 x 50 (CGA and MDA) text modes. Selection of the CRT mode, results in the display of only an 8 x 8- character cell format. An illustration of the 8 x 8character cell format and the 8 x 16-character cell format which the preferred embodiment of the present invention is capable of displaying is set for in APPENDIX C.

Another important aspect of the present invention is the CRT/Plasma conversion (fake-out) programmable read only memory (PROM). As previously mentioned, compatibility between this invention and earlier generation machines is necessary in order to permit the current installed base of users to use this invention without losing the flexibility of any of their existing applications software and data bases. The CRT/Plasma conversion PROM makes this feature possible. The conversion or fake-out PROM converts standard CRT controller parameter data from the CPU so that the data is of the correct values for display on the plasma panel. The conversion PROM in the preferred embodiment is a 512 byte x 8,bit bipolar PROM.

The plasma display requires different CRT controller register programming than that for a CRT, the conversion \0 dt 1 1, PROM ensures maximum compatibility by converting CRT controller data so that the data is usable by the plasma display. In the plasma mode, CRT controller data received from the CPU is manipulated by the conversion PROM and corrected for use by the plasma display. In the CRT mode, CRT controller data are received directly from the CPU, and the conversion PROM is bypassed. In the plasma mode, the CRT controller data is sent from the CPU to the conversion PROM, then to the display registers. A complete listing of the source code of the conversion PROM is provided in APPENDIX D. The source code listing attached as APPENDIX D is incorporated herein by reference as if set forth in full herein.

The gate array controller provides all timing and control functions for the display controller board and the plasma display panel. Additionally the gate array provides full compatibility with the MDA and the CGA standard display modes. Functional schematics of the gate array 20 are provided in APPENDIX A.

The gate array (See function schematics in APPENDIX A) incorporates the following functions:

1) 2) 3) 4) 5) 6) 7) 8) 9) 10) 6845-Type CRT controller; All address decode and control registers for the video functions; Character-generator RAM interface; Color mapping logic; CRT/Plasma conversion PROM interface; Intensity mapping logic; Plasma and CRT drive logic; Screen blank timeout logic; Timing generator; and Video memory controller.

The display modes listed in TABLE I are supported by the gas plasma display controller and display panel of the present invention.

TABLE I

Display Mode 1) 40 x 25 Text 2) 80 x 25 Text 3) 320 x 200 Graphics 4) 640 x 200 Graphics 5) IBM Monochrome Text 6) 640 x 400 Graphics 7) 80 x 40 Text 8) 80 x 50 Text 9) 40 x 40 Text 10) 40 x 50 Text The display controller of the preferred embodiment will support the plasma display for all of the above listed modes, however, the controller will only support the modes listed in TABLE II (below) for a CRT display:

TABLE II

1) 40 x 25 Text 2) 80 x 25 Text 3) 320 x 200 Graphics A) 640 x 200 Graphics Text displays are character oriented. The dot patterns for the display are stored in the charactergenerator RAM. The character look-up tables from the system BIOS are loaded in RAM and retained there for ready access while the computer is on. In the event a character V), is to be displayed the appropriate dot pattern for a particular character can be accessed.

Graphics displays are pixel oriented.. A pixel is the smallest controllable display element i.e. a single dot or group of dots on the screen. In the preferred embodiment, the low resolution graphics mode (i. e., 320 x 200), the pixel is comprised of a group of four dots. In the CGA mode the color of each pixel is specified in video memory.

For text displays, the display controller board uses two bytes of video memory to define each character e.g. a character byte and an attribute byte. For graphics displays, the display controller board uses the video memory as the source of patterns which are to be displayed.

In the preferred embodiment the text modes listed in TABLE I are supported by the BIOS and the gate array controller. In the plasma mode, the character set format is 8 x 16 pixels or 8 x 8 pixels. In the CRT mode, the character set format is 8 x 8 pixels.

In the preferred embodiment of the present invention the 320 x 200 graphics mode listed in TABLE I above is supported by the BIOS and the gate array controller. In this graphics mode, software written text is obtained from the character tables in the BIOS ROM and written to video RAM. Graphics information and text information is read from video RAM and displayed on the plasma panel. In the 320 x 200 graphics mode on the plasma display, 2 data bits define a single pixel. The gate array controller maps a pixel into a 4-dot (2 horizontal x 2 vertical dot).configuration depending on the way that two data bits are set. Since the plasma display cannot replicate the four- color capability of a color CRT, this mapping provides graphic differentiation in the plasma mode for the viewer.

1'b This graphic differentiation is accomplished by a slight shading of the character not bya color differentiation on the plasma panel. The character shading is produced by a combination of dot pattern and pixel sparkle. The pixel sparkle effect is achieved by alternatingr at a frame rate, the illumination of the dots normally comprising an active pixel.

The 640 x 200 graphics mode in TABLE I above is supported by the BIOS and the gate array controller. In this graphics mode, software written text is obtained from the character tables in the BIOS ROM and written to video memory. Graphics information and text information is read from the video memory and displayed on the plasma panel.

The data is displayed on the plasma display by a single pixel defined by 1 data bit. This pixel consists of 2 dots configured in an array of one horizontal dot x 2 vertical dots.

The 640 x 400 graphics mode in TABLE I above (the high-resolution mode) is only available for the plasma display panel and is supported by the gate array con troller and by the BIOS. In this high resolution mode, 1 bit defines 1 pixel. In this high resolution mode 1 pixel is the equivalent of a single dot.

As previously indicated the gas plasma display panel is comprised of an array of conductor intersections. In the present invention the plasma display unit contains 640 x 400 dots. Each dot can be illuminated independently by exceeding the ionization potential of the gas at the conductor intersections. For the low resolution graphics mode (i.e. 320 x 200), the discrete dots are typically arranged in a 2 x 2 matrix and in the prior art devices the 2 x 2 matrixt treated as a pixel, is considered a single addressable eiement. Thus the majority of prior X art devices illuminate the entire 2 x 2 matrix (i.e. 4 dots) whenever the pixel is to be illuminated or have a pre-selected arrangement for dots to be illuminated for all frames scanned. These methods of illuminating the 2 x 2 matrix provide some apparent shades without completely emulating the CGA mode.

The treatment of a 2 x 2 matrix as a single pixel is also dictated by software considerations. Since most applications software for the personal computer industry is written by independent software writers (i.e. not associated with the computer manufacturer) it is imperative that new personal computers maintain at least a modicum of compatibility with the predecessor machines.

In the case of a gas plasma display, the predecessor machines have cathode ray tubes (CRT). The CRT displays typically have a 640 x 200 array. With the introduction of the gas plasma display, with a larger array, computer manufacturers realized the necessary compatibility by equating a pixel with a 2 x 2 dot array.

The implementation of a 2 x 2 dot array as a single pixel permits software written for the predecessor machines to be used on computers with a gas plasma display without any compensation for the larger display. However, this equation results in a treatment of the 2 x 2 array as a single addressable element and therefore a single indivisible element.

Of particular interest in the present invention is the 320 x 200 graphics mode. The shading of the pixels is implemented in the 320 x 200 graphics mode. Other.display modes of the preferred embodiment of the present inven tion, use the prior art display methods by addressing discrete-dots as indivisible pixels and make no differen- 1 11 ki tiation in the illumination of the dis the pixel.

crete dots within The plasma panel display controller of the present invention maps a pixel into a four display dot configuration depending on the setting of the two display data bits. In this mode two bits define a pixel. Bits 4 and of the color select register can be used to select the mapping of the pixel to the four dot configuration on the 10 plasma panel. TABLE III (shown below) illustrates the pixel/dot mapping arrangement for the sparkle display in the preferred embodiment.

TABLE III

Display Data Bits INO Color 1 E 1 1 0 0 1 1 25 1 Red 1-1 0 0 1 0 Even scan 1 1 1 Color Register (03D9h) Bits 5 & 4 (111-1) (111-2) (111-3) 4 glue Inten.

0 0 (111-4) 1 1 1 1 4 5 4 5 4 glue Inten. 1Rlue Inten. R1up Inten.

0 1 1 0 Vertical Frames 1 1 1 1 1 1 Even Odd Scan scan Green E 1 0 0 1Red&Greenj E 1 1 C) Odd Even Odd Even Odd scan scan scan scan Scan ( = Dot on, = Dot off) (E = Even, 0 = Odd) 1 In TABLE III above the bits represented under the "Display Data Bits" heading represent a pair of bits stored in the display memory. This pair of bits define the dots of the pixel to be illuminated. Prior art plasma panel devices neglect the color attribute resident in the applications' software. In essence color attributes in these prior art devices default to a value of zero-zero for bits 4 and 5 (see column III-1 of TABLE III above). With a default value of zero-zero assigned to bits 4 and

5, the panel display is essentially reduced to a 2 bit word. With a default value of zero-zero for bits 4 and 5, four possible intensities can be achieved with a 2 bit word. Those four possible combinations are illustrated i column III-1 of TABLE III. These four patterns are scanned identically for even and odd frames.

The present invention achieves the four intensities shown in column III-1 by assigning a value of zero-zero to bits 4 and 5 of the 3D9h register (color register). The present invention however can achieve 12 other combinations (e.g. 16 total combinations, only 10 visually perceptible combinations in reality) by various combinations of ones and zeroes for bits 4 and 5 of the 3D9h register. The 16 intensities are illustrated in TABLE III, four per column for columns 111-1, 111-2, 111-3 and 111-4.

Additionally, the present invention illuminates different combinations of the 4 dots for display data bit values zero-one and one-zero for odd and even refresh frames to achieve the previously mentioned pixel sparkle effect. These different combinations are shown in columns 111-3 and 111-4 for display data bit values zero-one and one-zero. The illumination of different combinations of dot patterns for display data bit values zero-one and one-zero in columns 111-3 and 111-4 for odd and even X 00 refresh frames results in a visually perceptible difference from the four dot combination shown in column 111-2 for display data bit values zeroone and one-zero.

The refresh rates are fast enough that no annoying flicker is perceived by the computer user. Although no flicker is perceived by the user, the different combinations shown in columns 111-2, 111-3 and 111-4 for display data bit values zero-one and one-zero result in a visually perceptible "sparkle" which gives the user the perception of a slight shading of the 2 x 2 matrix (4 dots = pixel). This slight shading is essentially the equivalent of the shading accomplished on a CRT through combinations of various colors.

As previously discussed the color attributes are used in the present invention to display shades. The color attributes are utilized in this fashion since the gas plasma display presently is not capable of displaying the colors normally associated with a color CRT. The color attribute is translated to a pixel intensity as illustrated in the TABLE III. As further illustrated in the TABLE III bits 4 and 5 of the color register provide a means to change the intensity of the pixels.

For color register bits 4 and 5 equal to zero the dot pattern shown in column III-1 is selected. For a CRT if no color is selected in the applications software the display data bits are set zero and zero. The display data bit values are set zero and one, the color red is selected. If the display data bit values are set one and zero, the color green is selected. If the display,data bit values are set one and one, the colors red and green are selected. The blue color bit is bit 5 of the color register illustrated at the top of TABLE III. Finally, the intensity of the pixel can be toggled by toggling t 1\ bit #4 of the color register also known as the intensity bit. Background colors are not used in the plasma mode.

In the 320 x 200 graphics mode the text is written into video RAM from the look-up character tables in the system BIOS stored in the ROM. This mode displays 320 pixels horizontally by 200 pixels vertically. For the plasma mode, the display controller maps a pixel into a four dot configuration depending on the setting of two display bits. These bits are subsequently modified by bits 4 and 5 set in the color register defined in the preferred embodiment as 3D9h. In this mode two display data bits define a 4 dot pixel.

The color register (3D9h) is functional in both the plasma and CRT modes, but only in the CGA display mode (not in the MDA) mode. The apparent color achieved by shading on the plasma panel is a result of varying the intensity and the arrangement of dots. This alters the appearance of the pixel by changing the pattern and illumination, on alternate frames, of the dots which make up the pixel. Causing a different dot arrangement to appear gives an operator the perception that the illumination of the dots which make up the pixel is being changed. In reality the dot intensity does not change; only the dot arrangement and pattern changes.

The arrangement of dots displayed on the screen is a result of the color register values and the display data bit values specified in video memory for each display location. For CRT displays in the two graphics modes, either 2 or 4 colors may be displayed at a time. For CRT displays in the text modes, 16 foreground and 16 background colors can be displayed simultaneously. In the plasma mode, only 2 apparent foreground and background colors can be simulated by providing different intensity

0 f.

C ^ 01-M levels for each. In the 320 x 200 graphics mode, on the plasma display panel the background colors are always OFF and the color-select bits specify different mappings for the 320 x 200 graphics mode. TABLE IV below sets forth the bit settings for the color register 7 6 5 4 3 2 1 0(Set bits red (R), blue (B) I R G B 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 1 0 1 0 1 0 (=1) enable green (G) r or intensity (I)) 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 0 1 1 0 0 0 0 1 1 0 1 1 DISPLAYED COLOR Black Blue Green Cyan Red Magenta Brown White Gray Light Blue Light Green Light Cyan Light Magenta Yellow Intense White Supplemental intensity enabledl Color Set2 0 = Standard (green, red, brown) 1 = Alternate (cyan, magenta, white) 00 (Reserved) Recall that bits 3, 2, 1 and 0 which represent the background colors are not used in the plasma mode

1. This is bit 4 shown in Table III.

2. This is bit 5 shown in Table III.

1. 1 Q\ Turning now to FIG. 2, the gate-array is illustrated as device U7. As previously mentioned a functional schematic of the custom gate array is found in Appendix A.

The gate array is connected to the CPU, (i.e. in this particular embodiment an Intel 80286 microprocessor) by means of lines identified in Figure 2.

The gate array is also operatively coupled to the video RAM, device Ul. The video RAM stores data sent by the applications software for display on the plasma panel or CRT.

Turning now to.FIG. 3A & 3B, the dot mapping and sparkle logic circuit for the 320 x 200 graphics mode for the plasma panel is illustrated. The logic circuits illustrated in FIG. 3A & 3B are contained within the gate array; however, the circuit is set out in discrete components in FIG. 3A & 3B to aid in the understanding of 20 this invention.

The data is received from the video RAM by 4 bit latch 25. The data is processed 4 bits at a time. The bits are arbitrarily labeled bits 0-3. The bits are clocked into logic circuits represented by areas sur rounded by broken lines. These areas have been arbi trarily labeled 26, 27, 28 and 29. Areas 26, 27, 28 and 29 correspond to bits 0, 1, 2 and 3, respectively. Signal DTACLK into 4 bit latch 25 is at a 4 MHz clock rate.

Logic circuits represented by areas labeled 26, 27, 28 and 29 are bypassed in the event the computer is in any CRT mode or plasma mode other than 320 x 200 graphics Referring now to FIG. 3A & 3B, 4 data bits are processed in parallel, as groups of 2 bits to generate 4 sequential dots for the plasma panel. These 4 bits are C\ C) 01 -1 shown at lines 30, 31, 32 and 33 as bits 0, 1, 2 and 3, respectively.

The logic circuit from 26 it equivalent to the logic circuit in frame 28. Similarly the logic circuit in frame 27 is equivalent to logic circuit in frame 29, however, frames 26 and 27 process bits 0 and 1 and frames 28 and 29 process bits 2 and 3 of the 4 bits stored in the 4 bit latch 25.

The logic circuits in frames 26, 27, 28 and 29 are used to process the following inputs:

a) b) c) d) e) two data bits from register 25; the color register bit 5; the color register bit 4; scan line information; and the odd/even frame information.

The global or color bit i.e., bit 5 of the color register (3D9h) is provided at line RG.GW<5>. The intensity bit i.e., bit 4 of the color register (3D9h) is provided at line RG.GW<4>. Odd and even scan line information is provided at line MR.LSL <0> while odd and even frame information is provided at lines labeled 110DDFRAME" and I'WNFRAME11 respectively.

The output bits 0, 1, 2 and 3 on lines 30, 31, 32 and 33 may be directly presented to the plasma panel for the 320 x 200 graphics mode. Additionally, logic diagrams are shown in Appendix A. However, this additional logic is merely used to integrate the text with any of the follow ing graphics information (a) 640 x 200; and (b) 640 x 400; or (c) 320 x 200, into a single video data stream.

1)-1 v 4 The logic diagrams in frame 26, 27, 28 and 29 essentially combine the data bits provided by latch 25 with the color register bits 4 and 5, scan line information (i.e., odd or even scan line) and the odd/even frame information to produce the clot arrangement and sparkle effect shown in TABLE III.

As is shown in TABLE III the illumination of different dot patters, for giving display data bits values, occurs for odd and even frame. Additionally, the illumination of the various dots for given display data bit values varies as a function of the scan lines (i.e., odd or even scan lines).

is Referring specifically to Table III above, some of the unique and novel aspects of the present invention are illustrated. Table III represents the dot patterns which are realized by the present invention in the low resolution graphics mode (i.e., 320 x 200).

Table III illustrates the dot patterns created for a single pixel by the circuit set forth in FIG. 3A & 3B for the various combinations of display data bit values and color register values. Table III also illustrates the dot patterns for a single pixel for odd and even frame refresh as well as odd and even scan lines.

The variations in dot patterns for given display data bit values creates a sparkle effect for each pixel (4 dot matrix) when the preferred embodiment is in the low resolution mode (i.e.. 320 x 200 graphics mode).

Referring now to FIG. 4, the even/odd frame counting logic is illustrated. Three input signals are presented at lines 34, 35 and 36 which represent "power on reset" (VS.RST); "vertical sync pulse" (BUFVSYNC); and Misplay 4f 1 A r enable" (DC.DED), respectively. DC.DED is a once per scan line pulse and is used to increment the scan line count used in text mode highlighting.

BUFVSYNC is a once per frame pulse used to toggle the odd/even frame count.

The output of the logic shown in FIG. 4 is VS.WNFRAME at line 37 and VS.ODDFRAME at line 38. The signals at lines 37 and 38 are sent to the control logic shown in FIG. 3A & 3B and presented at the appropriate lines (also labeled 37 and 38).

The logic circuits illustrated in FIG. 3A & 3B are interconnected in the manner shown in Appendix A. As previously mentioned the schematics in Appendix A are a functional equivalent of the gate array controller. The gate array controller is illustrated as a single chip in FIGS. 1 and 2 and in the preferred embodiment is a single chip which contains the functionality of the schematics in Appendix A.

The above detailed description describes the preferred embodiment for implementing the present invention.

Other improvements and modifications will become apparent to those skilled in the art having the benefit of this disclosure.

1 1

Claims (10)

CLAIMS:

1 1. A gas plasma display comprising: a gas plasma display panel; display logic incorporated in an integrated display controller (gate array); a character generator operatively connected to the gate array; a video memory operatively connected to the gate array; a conversion PROM operatively connected to the gate array wherein the integrated display controller is operatively connected to the display panel and video memory wherein said controller maps a pixel into a four dot display matrix when the panel is in a low resolution graphics mode, and said four dot matrix is used to vary the apparent intensity of the pixel by varying the display sequence and pattern of the dots which form the pixel.

2. A gas plasma display according to claim 1, wherein the pixel display intensity and shading is varied by the setting of two global software bits.

3. A gas plasma display compatible with software written for colour monitors and other monochrome monitors comprising: a gas plasma display panel; a video memory; and an integrated display controller operatively connected to the display panel and video memory wherein said controller deciphers the colour attribute and selectively illuminates a four dot display matrix for each pixel to be displayed wherein the colour attribute resident in software is used to vary the intensity of the pixel which is displayed.

4. A gas plasma display according to claim 3, wherein the shading of the pixel is varied by alternating the dots which are illuminated for a given pixel, said dots being alternately illuminated on alternate scan lines for alternate frames which are displayed.

1 I 11.

5. A gas plasma display compatible with software written for colour monitors and other monochrome monitors comprising: a gas plasma display panel; a video memory; and an integrated display controller operatively connected to the display panel andvideo memory wherein said controller deciphers the colour]attribute written in software and selectively illuminates a four dot display matrix to provide apparent shades of intensity on the monitory said apparent shades of intensity being produced by alternating the pattern of illumination of a four dot matrix for the pixels which are active.

6. A gas plasma display according to claim 5, wherein the apparent shades of intensity are provided by alternating the dots which are illuminated for the active pixels, said dots being alternately illuminated on alternate scan lines for alternate frames which are displayed.

7. A gas plasma display according to claim 4 or 6 wherein the frames are changed at a rate of 60 times a second.

8. A gas plasma display according to claim 4 or 6, wherein the frames are changed at a rate of 50 times a second.

9. A gas plasma display substantially as herein described with reference to and as shown in the accompanying drawings.

10. Any novel feature or combination of features disclosed herein.

Published 1988 at The Patent Office, State House, 66171 Holborn, London WC1R 4TP. Further copies may be obtained from The Patent OfEce, Sales Branch, St Mary Cray, Orpington, Kent BR5 3RD. Printed by Multiplex techniques ltd, St Maxy Cray, Kent. Con. 1187. bwes brancii, bt mary uray, urpii, isent ijro i5kw..rrmTen oy muiupiex Tecamques &Dc or, naary uray, zenT,. uon. im.r.