GB2296593A - Boosting voltage circuit for semiconductor memory device - Google Patents
Boosting voltage circuit for semiconductor memory device Download PDFInfo
- Publication number
- GB2296593A GB2296593A GB9526716A GB9526716A GB2296593A GB 2296593 A GB2296593 A GB 2296593A GB 9526716 A GB9526716 A GB 9526716A GB 9526716 A GB9526716 A GB 9526716A GB 2296593 A GB2296593 A GB 2296593A
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- United Kingdom
- Prior art keywords
- boosting voltage
- circuit
- signal
- generating
- boosting
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Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/4074—Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/408—Address circuits
- G11C11/4085—Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
- G11C5/143—Detection of memory cassette insertion or removal; Continuity checks of supply or ground lines; Detection of supply variations, interruptions or levels ; Switching between alternative supplies
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
- G11C5/145—Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Dram (AREA)
- Dc-Dc Converters (AREA)
Description
2296593 BOOSTING VOLTAGE CIRCUIT FOR SEMICONDUCTOR MEMORY DEVICE The
present invention relates to boosting voltage circuits for semiconductor memory devices, and is concerned particularly although not exclusively with highly integrated semiconductor memory devices using a low level of power supply voltage.
Recently, as dynamic random access memories (dynamic RAM) tend to pursue high density and low power consumption, a boosting voltage Vpp generator has been typically employed in a chip so as to prevent the deterioration of, for example, word line driving capability. This boosting voltage Vpp has a higher voltage level than an internally used power supply voltage Vcc, which serves to raise a word line driving voltage which tends to be weak due to the high density of the device. To read data "V' stored in memory cells, a sufficient voltage difference should be f ormed in distributing charge between the memory cells and bit lines. To this end, a sufficient level of voltage has to be supplied to the word line so that cell transistors can be fully turned on. However, since this effect can not be obtained with a lowered power supply voltage Vcc, such a boosting voltage Vpp having a greater potential than Vcc + Vth (where Vth is a threshold voltage of a cell transistor) becomes needed.
As is well known in the related art, methods of maintaining the potential of the boosting voltage Vpp are as follows. In a stand-by state, the Vpp level is detected through a stand-by level detector. Here, in the case where the detected level is lower than a predetermined reference level, a boosting voltage generator is driven to raise the detected level to the reference level. On the contrary, in the case where the detected level is higher than or equal to the reference level, operation of the stand-by boosting voltage generator is stopped. However, since a stand-by typical boosting voltage generator is of small capacity, another boosting voltage generator for active state use, having a significantly greater capacity, is further needed so as to supplement an amount of charge of the boosting voltage consumed during the active state.
A conventional boosting voltage circuit configuration is illustrated in Figures 1 to 5 of the accompanying diagrammatic drawings, in which:
Figure 1 is a schematic block diagram of the conventional boosting voltage circuit; Figure 2 is a timing diagram of Figure 1; Figure 3 is a circuit diagram of the boosting voltage generator control circuit 2 of Figure 1; Figure 4 is a circuit diagram of a first boosting voltage generator 3 of Figure 1; and Figure 5 is a circuit diagram of the second boosting voltage generator 4 of Figure 1.
A boosting voltage generator control signal 0 PC is generated by a circuit 2 every active state in response to a chip master clock 0 R, which in turn is generated in response to a row address strobe signal RASB, by a generator 1. First and second boosting voltage generators 3 and 4 are operated under the control of the signal PC, and are respectively used. for stand-by state and active state. As shown in Figures 2 to 5, the first and second boosting voltage generators 3 and 4 are operated in a complementary relation in accordance with the signal 0 PC. In the active state where the signal RASB is in a logic Relow" level, the first boosting voltage generator 3 generates the boosting voltage Vpp, and in the stand-by state where the signal RASB is in a logic "high" level, the second boosting voltage generator 4 generates the boosting voltage Vpp. Referring to Figure 4, during the stand-by state where the signal 0 PC is in the logic "low" level, a potential on a node 5 is raised by a MOS capacitor 7 and the raised potential is transmitted through a diode NMOS transistor 10 for transmission to a node 6. When the signal 0 PC is changed from the logic "low" level to the logic "high" level (the signal RASB falls to the logic "low" level and the active state is started), the potential on the node 6 is again boosted by a MOS capacitor 12 and generated as the boosting voltage Vpp through an NMOS transistor 11.
Here, by accurately detecting the charge amount of the boosting voltage Vpp consumed every active state, the capacity of the boosting voltage generator for the active state should be set to supply the detected charge amount of the boosting voltage Vpp. However, in the configuration of Figure 1, there are problems in that the charge consumption amount of the voltage Vpp is not accurately consistent with the capacity of the boosting voltage generator, and in the case where the capacity of the boosting voltage generator is larger than the charge consumption amount of the Vpp, the reliability chip deteriorates due to overdue current consumption and high electric field.
Preferred embodiments of -the present invention aim to 35 provide a boosting voltage circuit for a semiconductor memory device, which is capable of generating a boosting voltage consistent with the amount of charge consumption of the boosting voltage during an active state.
Another aim is to provide a boosting voltage circuit for a semiconductor memory device which is capable of supplying a boosting voltage, whilst ensuring reduction of current consumption and enhanced reliability of the device.
According to one aspect of the present invention, there is provided a boosting voltage circuit for a semiconductor memory device, the circuit comprising:
first circuit means for receiving a chip master clock determining a standby state and an active state and generating a detector control signal activated after a f irst delay time and having a first pulse width and a latch control signal activated after a second delay time and having a second pulse width; second circuit means for responding to said detector control signal and said latch control signal and generating a detecting signal indicative of a potential state of a current boosting voltage; third circuit means for generating a boosting voltage generator control signal simultaneously activated together with said detecting signal in response to said chip master clock; and boosting voltage generating means for respectively operating in said stand-by state and active state in response to said detecting signal and said boosting voltage generator control signal.
A boosting voltage circuit as above may include additional circuit means for receiving said detecting signal and generating a further detecting signal under control of said chip master clock, said boosting voltage generating 5 means being responsive to said further detecting signal.
Preferably, said additional circuit means comprises a register, such that said further detecting signal corresponds to the original detecting signal but is delayed with respect thereto by a period determined by said chip master clock.
Preferably, said boosting voltage generating means comprises first and second boosting voltage generating means for respectively operating in said stand-by state and active state.
According to another aspect of the present invention, there is provided a boosting voltage circuit for a semiconductor memory device, the circuit comprising generating means for generating a boosting voltage, monitoring means for monitoring the boosting voltage, and controlling means for controlling the generating means in accordance with the output of the monitoring means.
A boosting voltage circuit as above may further comprise any one or more of the features disclosed in the accompanying specification, claims, abstract and/or drawings, in any combination.
The invention extends to a semiconductor memory device provided with a boosting voltage circuit according to any of the preceding aspects of the invention.
- 6 For a better understanding of the invention, and to show how embodiments of the same may be carried into ef f ect, reference will now be made, by way of example, to Figures 6 to 18 of the accompanying diagrammatic drawings, in which:
Figure 6 is a schematic block diagram of a boosting voltage circuit according to an embodiment of the present invention; Figure 7 is a circuit diagram of a detector control circuit 20 of Figure 6; Figure 8 is a circuit diagram of a boosting voltage detector 30 of Figure 6; Figure 9 is a circuit diagram of a first boosting voltage generator 40 of Figure 6; Figure 10 is a circuit diagram of a boosting voltage generator control circuit 50 of Figure 6; Figure 11 is a circuit diagram of a second boosting voltage generator 60 of Figure 6; Figure 12 is a timing diagram of the circuit of Figure 6; Figure 13 is a schematic block diagram of a boosting voltage circuit according to another embodiment of the 30 present invention; Figure 14 is a circuit diagram of a register 70 of Figure 13; Figure 15 is a circuit diagram of the first boosting voltage generator 40 of Figure 13; Figure 16 is a circuit diagram of the second boosting 5 voltage generator 60 of Figure 13; Figure 17 Is a circuit diagram of a boosting voltage generator control circuit 80 of Figure 13; and Figure 18 is a timing diagram of the circuit of Figure 13.
In the figures, like reference numerals denote like or corresponding parts.
Referring to Figure 6, a boosting voltage circuit according to an embodiment of the present invention comprises chip master clock generator 1 for generating a chip master clock R in response to a row address strobe signal RASB; a detector control circuit 20 for generating a detector control signal DET and a latch control signal LAT in response to the chip master clock 0 R; a boosting voltage generator control circuit 50 for generating a boosting voltage generator control signal PC in response to the chip master clock R; first and second boosting voltage generators 40 and 60 for generating boosting voltages Vpp under control of the boosting voltage generator control signal 0 PC; and a boosting voltage detector 30 for supplying to the f irst and second boosting voltage generators 40 and 60 a signal 0 PD sensing the potential of the voltage Vpp under the control of the signals DET and LAT.
Referring to Figure 7, in the detector control circuit 20 of Figure 6, the signal 0 DET is generated by a configuration having a first pulse shaping circuit composed of a NAND gate ND31 whose one input terminal is connected to the output of five inverters 121 to 125 connected in serial with each other from the chip master clock 0 R and whose other input terminal is directly connected to the chip master clock 0 R, and an inverter 126 for inverting the output of the pulse shaping circuit.
The signal LAT is generated by a configuration having a second pulse shaping circuit composed of a NAND gate ND32 whose one input terminal is connected to the output of three inverters 127 to 129 connected in serial with each other from the chip master clock 0 R and whose other input terminal is directly connected to the chip master clock 0 R, and three further inverters 130 to 132 connected in serial to each other, for inverting and delaying the output of the second pulse shaping circuit.
Referring to Figure 8 showing the boosting voltage detector 30 of Figure 6, the gate of an NMOS transistor N31 connected between a power supply voltage Vcc and a 20 detecting node 31 is connected to receive the boosting voltage Vpp. An NMOS transistor N32 is connected between the drain of an NMOS transistor N33 having a source connected to ground Vss and the detecting node 31, the gate of which transistor N32 is connected to receive the detector control signal DET. The gate of the NMOS transistor N33 is connected to receive the boosting voltage Vpp. The detecting node 31 is connected to an input terminal of a transmission gate T31. An N type electrode of the transmission gate T31 is connected to the signal 0 LAT and a P type electrode thereof is connected to an output terminal of an inverter 133 receiving the signal 0 LAT. On another path between the transmission gate T31 and an inverter 136 there are provided inverters 134 and being serially connected to each other. The signal 0 PD detecting the potential of the voltage Vpp is generated from the inverter 136.
Referring to Figure 9 showing the first boosting voltage generator 40 of Figure 6, the first boosting voltage generator 40 has the same configuration as the first boosting voltage generator 3 of Figure 4 except for a NAND gate ND41 for inputting the signals PC and PD and an inverter 141 for inputting the output of the NAND gate ND41.
Referring to Figure 10 showing the boosting voltage generator control circuit 50 of Figure 6, this structure comprises six inverters 151 to 156 connected serially to each other. When compared with the conventional structure of Figure 3, the increment of the number of inverters is to operate the first and second boosting voltage generators 40 and 60, after the detecting signal PD is generated in accordance with the potential state of the Vpp detected by the boosting voltage detector 30.
Referring to Figure 11 showing the second boosting voltage generator 60 of Figure 6, since the second boosting voltage generator 60 operates in a complementary relation with the first boosting voltage generator 40, the generator 60 has the same configuration as the second boosting voltage generator 4 of Figure 5 except for a NAND gate ND61 for inputting the signals PC and 0 PD replacing the inverter 14 of Figure 5.
Referring to Figure 12 showing a timing diagram of the circuit of Figure 6, the operation characteristic according to the this example of present invention is shown when the voltage Vpp-changes from a low potential to a high potential. As the signal RASB is changed to the - logic "low" level from the logic "high" level at a time tl, the signal OR is generated at the logic "high" level at a time t2 and the signal 0 DET is generated as a pulse of the logic "high" level at a time t3. After that, the signal 0 LAT is generated as a pulse of the logic "high" level at a time t4. In the meanwhile, the boosting voltage detector 30 of Figure 8, during a precharge cycle where the signal RASB is in the logic "high" level, since the signals 0 DET and 0 LAT are all in the logic "low" level, the potential of the detecting node 31 is precharged to the power supply voltage Vcc by the NMOS transistor N31 and the transmission gate T31 is turned off. If the signal 0 DET becomes a pulse of the logic "high" level at the time period t3 and the pulse is applied to the gate of NMOS transistor N32, the potential of the detecting node 31 is dependent upon the potential state of the voltage Vpp. When the potential of the voltage Vpp is high, the potential of the detecting node 31 goes to the logic "high" level and to the contrary, when the potential thereof is low, the potential thereof falls to the logic "low" level. If the level of the signal 0 LAT become high at the time period t4, the transmission gate T31 is turned on and the signal 0 PD is generated at the logic "low" level (when the potential of the voltage Vpp is high) or the logic "high" level (when the potential of the voltage Vpp is low).
Then, when the level of the signal 0 LAT becomes low and the transmission gate T31 is turned off, the current status is maintained by the inverters 134 and 135. The generation of the signals 0 DET and 0 LAT as pulses is made to prevent unnecessary power consumption by the operation of the boosting voltage detector 30 only during the time necessary for detecting the potential of the Vpp in the active state.
Referring to Figures 9 and 11, the first boosting voltage generator 40 operates in response to the time point when the signal RASB is changed to the logic "low" level from the logic "high" level, and the second boosting voltage generator 60 operates in response to the time point when the signal RASB is changed to the logic "high" level from the logic "low" level. In the case where the voltage Vpp has a high potential, since the signal PD is applied at the logic "low" level, the first and second boosting voltage generators 40 and 60 maintain the non-activation state. In the case where the voltage Vpp has a low potential, since the signal PD is applied at the logic "high" level, the first and second boosting voltage generators 40 and 60 are in turn operated in accordance with the signal RASB and the toggled signal PC. The operations of the first and second boosting voltage generators 40 and 60 are executed in the same manner as those of Figures 4 and 5.
Figure 13 is a schematic block diagram of a boosting voltage circuit according to another embodiment of the present invention. In addition to the structure of Figure 6, a register 70 is disposed between the boosting voltage detector 30 and the first and second boosting voltage generators 40 and 60. In other words, the signal 0 PD generated from the boosting voltage detector 30 passes through the register 70 and is then applied to the first and second boosting voltage generators 40 and 60.
It can be appreciated that the register 70 is, as shown in Figure 14, a common shift register comprises transmission gates T71 and T72 controlled by the signal R (directly and through an inverter T71) and latches L71 and L72. While the signal 0 R is in the logic "low" level, the transmission gate T71 is turned on and the signal 0 PD generated f rom the boosting voltage detector 30 in the previous active state is stored in the latch L71. On the other hand, while the signal 0 R is in the logic "high" level, the transmission gate T72 is turned on and the state temporarily stored in the latch L72 in the previous active state is output as the signal 0 SPD. Thereafter, when the signal OR falls to the logic "low" level, the transmission gate T71 is turned on and the transmission gate T72 is turned off, this resulting in the change of storing status of latch L71. That is, the register 70 is acted to allow the signal OPD set in the previous active state to determine whether driving of the first or second boosting voltage generator 40 or 60 is executed.
Instead of the signal 0 PD of Figures 9 and 11, the signal SPD is, as shown in Figures 15 and 16, input to NAND gates ND41 and ND61 of the first and second boosting voltage generators 40 and 60. Furthermore, the boosting voltage generator control circuit 80 in the embodiment of Figure 13 is constructed not with the six inverters shown in Figure 6 to meet with the time period during the generation of the signal PD, but with two serial inverters 181 and 182 shown in Figure 17. When compared with the structure of Figure 6, this ensures a sufficient operation time of the boosting voltage generator.
Referring to Figure 18 showing a timing diagram of the circuit of Figure 13, in the case where the voltage Vpp is low, the boosting voltage generators operate when the signal RASB is in the active state, and the generators operate even although the potential of the Vpp is in the logic "high" level in the next cycle by the signal SPD latched in the previous active state. In the next active state, the signal 0 SPD i.s in the logic "low" level by receiving the status latched in the previous active state 13 - and the boosting voltage generators are in non-activated states. Although operation of the boosting voltage generators is delayed by one cycle, the voltage Vpp has a large loading characteristic, such that the potential thereof is not unduly influenced.
In the above-described examples of the present invention, the boosting voltage generator is controlled in accordance with the potential state of the boosting voltage Vpp, thus ensuring reliability in generating and supplying the voltage Vpp.
The reader's attention is directed to all papers and documents which are filed concurrently with or previous to this specification in connection with this application and which are open to public inspection with this specification, and the contents of all such papers and documents are incorporated herein by reference.
All of the features disclosed in this specification (including any accompanying claims, abstract and drawings), and/or all of the steps of any method or process so disclosed, may be combined in any combination, except combinations where at least some of such features and/or steps are mutually exclusive.
Each feature disclosed in this specification (including any accompanying claims, abstract and drawings), may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise. Thus, unless expressly stated otherwise, each feature disclosed is one example only of a generic series of equivalent or similar features.
The invention is not restricted to the details of the foregoing embodiment(s). The invention extends to any novel one, or any novel combination, of the features disclosed in this specification (including any accompanying claims, abstract and drawings), or to any novel one, or any novel combination, of the steps of any method or process so disclosed.
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Claims (8)
1. A boosting voltage circuit f or a semiconductor memory device, the circuit comprising:
f irst circuit means for receiving a chip master clock determining a stand-by state and an active state and generating a detector control signal activated af ter a f irst delay time and having a f irst pulse width and a latch control signal activated after a second delay time and having a second pulse width; second circuit means for responding to said detector control signal and said latch control signal and generating a detecting signal indicative of a potential state of a current boosting voltage; third circuit means for generating a boosting voltage generator control signal simultaneously activated together with said detecting signal in response to said chip master clock; and boosting voltage generating means for respectively operating in said stand-by state and active state in response to said detecting signal and said boosting voltage generator control signal.
2. A boosting voltage circuit according to claim 1, including additional circuit means for receiving said detecting signal and generating a further detecting signal under control of said chip master clock, said boosting voltage generating means being responsive to said further detecting signal.
16
3. A boosting voltage circuit according to claim 2, wherein said additional circuit means comprises a register, such that said further detecting signal corresponds to the original detecting signal but is delayed with respect thereto by a period determined by said chip master clock.
4. A boosting voltage circuit according to any of the preceding claims, wherein said boosting voltage generating means comprises first and second boosting voltage generating means for respectively operating in said standby state and active state.
5. A boosting voltage circuit substantially as hereinbefore described with reference to Figures 6 to 12 or Figures 13 to 18 of the accompanying drawings.
6. A boosting voltage circuit for a semiconductor memory device, the circuit comprising generating means for generating a boosting voltage, monitoring means for monitoring the boosting voltage, and controlling means for controlling the generating means in accordance with the output of the monitoring means.
7. A boosting voltage circuit according to claim 6, further comprising any one or more of the features disclosed in the accompanying specification, claims, abstract and/or drawings, in any combination.
8. A semiconductor memory device provided with a boosting voltage circuit according to any of the preceding claims.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019940038503A KR0137317B1 (en) | 1994-12-29 | 1994-12-29 | Boost circuit of semiconductor memory device |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| GB9526716D0 GB9526716D0 (en) | 1996-02-28 |
| GB2296593A true GB2296593A (en) | 1996-07-03 |
| GB2296593B GB2296593B (en) | 1997-07-23 |
Family
ID=19404725
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB9526716A Expired - Lifetime GB2296593B (en) | 1994-12-29 | 1995-12-29 | Boosting voltage circuit for semiconductor memory device |
Country Status (7)
| Country | Link |
|---|---|
| JP (1) | JP2828942B2 (en) |
| KR (1) | KR0137317B1 (en) |
| CN (1) | CN1045838C (en) |
| DE (1) | DE19547796C2 (en) |
| FR (1) | FR2729020B1 (en) |
| GB (1) | GB2296593B (en) |
| TW (1) | TW282544B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2301211A (en) * | 1995-05-17 | 1996-11-27 | Samsung Electronics Co Ltd | Voltage boosting circuit for a semiconductor memory |
| GB2307317A (en) * | 1995-11-13 | 1997-05-21 | Samsung Electronics Co Ltd | Internal voltage booster for a semiconductor memory device |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6094395A (en) * | 1998-03-27 | 2000-07-25 | Infineon Technologies North America Corp. | Arrangement for controlling voltage generators in multi-voltage generator chips such as DRAMs |
| CN1299432C (en) * | 2001-10-29 | 2007-02-07 | 旺宏电子股份有限公司 | Driving voltage generator that reduces the influence of operating voltage and temperature |
| KR100846484B1 (en) | 2002-03-14 | 2008-07-17 | 삼성전자주식회사 | RMIM electrode, manufacturing method thereof and sputtering apparatus employing the same |
| KR100741471B1 (en) * | 2006-09-29 | 2007-07-20 | 삼성전자주식회사 | Boosting scheme without latch-up |
| JP5137545B2 (en) * | 2006-12-25 | 2013-02-06 | 株式会社半導体エネルギー研究所 | Semiconductor device and driving method thereof |
| US9502119B2 (en) * | 2014-11-20 | 2016-11-22 | Samsung Electronics Co., Ltd. | Distributed capacitive delay tracking boost-assist circuit |
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| EP0271686A2 (en) * | 1986-12-19 | 1988-06-22 | International Business Machines Corporation | On chip multi-level voltage generation system |
| GB2232829A (en) * | 1989-06-10 | 1990-12-19 | Samsung Electronics Co Ltd | An internal voltage converter in a semiconductor integrated circuit |
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| GB2262821A (en) * | 1991-12-23 | 1993-06-30 | Samsung Electronics Co Ltd | Dual voltage generator |
| GB2265770A (en) * | 1992-03-30 | 1993-10-06 | Samsung Electronics Co Ltd | Charge pump circuit |
| US5329168A (en) * | 1991-12-27 | 1994-07-12 | Nec Corporation | Semiconductor integrated circuit device equipped with substrate biasing system selectively powered from internal and external power sources |
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| JPS63153791A (en) * | 1986-12-17 | 1988-06-27 | Mitsubishi Electric Corp | Word line drive signal generation circuit |
| US5272676A (en) * | 1990-11-20 | 1993-12-21 | Hitachi, Ltd. | Semiconductor integrated circuit device |
| JPH04287418A (en) * | 1991-03-18 | 1992-10-13 | Fujitsu Ltd | Semiconductor integrated circuit |
| JPH05174591A (en) * | 1991-12-25 | 1993-07-13 | Sharp Corp | Charge pumping circuit |
| JP3179848B2 (en) * | 1992-03-27 | 2001-06-25 | 三菱電機株式会社 | Semiconductor storage device |
| US5337284A (en) * | 1993-01-11 | 1994-08-09 | United Memories, Inc. | High voltage generator having a self-timed clock circuit and charge pump, and a method therefor |
-
1994
- 1994-12-29 KR KR1019940038503A patent/KR0137317B1/en not_active Expired - Fee Related
-
1995
- 1995-12-09 TW TW084113127A patent/TW282544B/zh not_active IP Right Cessation
- 1995-12-20 DE DE19547796A patent/DE19547796C2/en not_active Expired - Lifetime
- 1995-12-28 JP JP7342653A patent/JP2828942B2/en not_active Expired - Fee Related
- 1995-12-28 FR FR9515663A patent/FR2729020B1/en not_active Expired - Fee Related
- 1995-12-29 GB GB9526716A patent/GB2296593B/en not_active Expired - Lifetime
- 1995-12-29 CN CN95120640A patent/CN1045838C/en not_active Expired - Lifetime
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0271686A2 (en) * | 1986-12-19 | 1988-06-22 | International Business Machines Corporation | On chip multi-level voltage generation system |
| GB2232829A (en) * | 1989-06-10 | 1990-12-19 | Samsung Electronics Co Ltd | An internal voltage converter in a semiconductor integrated circuit |
| GB2244392A (en) * | 1990-04-06 | 1991-11-27 | Mosaid Inc | High voltage boosted word line supply charge pump and regulator for dram |
| GB2249412A (en) * | 1990-10-30 | 1992-05-06 | Samsung Electronics Co Ltd | Substrate voltage generator for a semiconductor device |
| GB2262821A (en) * | 1991-12-23 | 1993-06-30 | Samsung Electronics Co Ltd | Dual voltage generator |
| US5329168A (en) * | 1991-12-27 | 1994-07-12 | Nec Corporation | Semiconductor integrated circuit device equipped with substrate biasing system selectively powered from internal and external power sources |
| GB2265770A (en) * | 1992-03-30 | 1993-10-06 | Samsung Electronics Co Ltd | Charge pump circuit |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2301211A (en) * | 1995-05-17 | 1996-11-27 | Samsung Electronics Co Ltd | Voltage boosting circuit for a semiconductor memory |
| GB2301211B (en) * | 1995-05-17 | 1998-05-27 | Samsung Electronics Co Ltd | Voltage boosting circuits |
| GB2307317A (en) * | 1995-11-13 | 1997-05-21 | Samsung Electronics Co Ltd | Internal voltage booster for a semiconductor memory device |
| GB2307317B (en) * | 1995-11-13 | 1998-01-14 | Samsung Electronics Co Ltd | Internal voltage booster for a semiconductor memory device |
Also Published As
| Publication number | Publication date |
|---|---|
| GB2296593B (en) | 1997-07-23 |
| CN1045838C (en) | 1999-10-20 |
| FR2729020B1 (en) | 1998-07-10 |
| DE19547796C2 (en) | 1998-04-16 |
| KR960025707A (en) | 1996-07-20 |
| GB9526716D0 (en) | 1996-02-28 |
| TW282544B (en) | 1996-08-01 |
| JPH08235859A (en) | 1996-09-13 |
| DE19547796A1 (en) | 1996-07-11 |
| KR0137317B1 (en) | 1998-04-29 |
| FR2729020A1 (en) | 1996-07-05 |
| CN1127919A (en) | 1996-07-31 |
| JP2828942B2 (en) | 1998-11-25 |
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| Date | Code | Title | Description |
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| PE20 | Patent expired after termination of 20 years |
Expiry date: 20151228 |