GB2293033A - Control circuit enabling program modification - Google Patents

Description

2293033 -I- CONTROL CIRCUI The present invention relates to a control

circuit for an electronic apparatus.

A one-chip microcomputer containing a mask-type read only memory (hereinafter called the "mask ROM") on which writing is allowed only once is used in a very wide variety of fields, because it reduces the scale of integrated circuit (hereinafter called the 11IC11) and is low in cost.

However, program instructions or data are written in a mask ROM when the IC is manufactured. Thus, it is impossible to change the program after the IC is completed.

Therefore, if an error is found in the program after the IC has been manufactured, it is necessary to manufacture the IC again, which is time consuming and expensive. In addition, if an error is found while a product containing the IC is being manufactured, rather than during the manufacturing of the IC itself, a large amount of damage would be caused.

The present invention seeks to minimize as far as possible the damage caused by a defective program.

According to the present invention, there is provided a control circuit for an electronic apparatus comprising:

a read-only memory containing instructions relating to the operation of the electronic apparatus, the instructions being stored at respective addresses; a rewritable memory for storing data relating to a desired alteration in the operation of the electronic apparatus; a first register for storing an address of the operating instruction which is about to be performed; a second register for storing an address derived from stored data relating to a desired alteration of the operating instructions; means for comparing the stored addresses in the first and second registers, and, when the stored addresses are equal, carrying out an operating instruction other than the operating instruction about 5 to be performed.

The control circuit of the invention is therefore arranged to be capable of replacing a section having the error in the program produced in a mask ROM with data in another rewritable non-volatile memory, in particular, an EEPROM (electric erasable programmable read only memory). This enables it to correct the program in the mask ROM, which has been impossible. Thus, even if an error is found in a program after completion of the IC, it becomes possible to take is measures by changing data in an EEPROM without remanufacturing the IC.

The invention may be applied to the control circuit for a camera.

For a better understanding of the present invention, and to show how it may be brought into effect, reference will now be made, by way of example, to the accompanying drawings, in which:

Figure 1 is a block diagram of a control circuit for a camera according to an embodiment of the present invention.

Figure 2 is a diagram illustrating the modification of the instruction code by an embodiment of the present invention.

Figure 3 is a diagram illustrating the addition/formation of an instruction code by an embodiment of the present invention.

Figure 1 shows a block diagram of an embodiment of the present invention. A ROM 11 is a mask ROM arranged in a chip 10 when manufacturing an IC, and stores an application program. A random access memory (hereinafter called the "RAM") 12 is provided for temporarily storing data during execution of the program. A step-register 13 is a register for storing information relation to the number of data instructions to be added or modified, and, for example, stores the contents of Ox - Fx. Here, x is a symbol indicating that it is a hexadecimal number.

A mode register 14 is a register for specifying whether an instruction is "add", "modify", or "ignore". The mode register 14 may be arranged, for example, to store 0 for "add", 1 for "modify", and 2 for "ignore". A command register 15 is a 16-byte register in which an instruction code to be executed after addition or modification is stored. A command address register 17 is a register which specifies an address in the command register 15. A multiplexer 16 selects the ROM 11 or the command register 15 depending on a signal, and outputs a selected instruction through a bus 24 to an operation circuit 22, which will be described later. A command address counter 19 is a counter which compares contents of an address setting circuit 18 and a program counter 20, and outputs a signal to a PC control circuit 23 when the contents of the address setting circuit 18 and the program counter 20 coincide. The PC control circuit 23 will be described later. The coincident signal being held is cleared by a signal from the PC control circuit 23. The address setting circuit 18 is a register which specifies an address of the ROM 11 at which an instruction should be added, modified or ignored.

The program counter 20 specifies an address of an instruction held in the ROM 11, which is incremented by 1 when each instruction is executed, and is set with a branched address when executing a jump instruction, a call instruction, or a return instruction. A stack pointer 21 temporarily stores the content of the program counter 20 when a subroutine is executed, and sets the program counter 20 to the address held in the stack pointer 21 when returning from the subroutine. The operation circuit 22 controls the operation of the electronic apparatus according to the program instructions output from the multiplexer 16. The PC control circuit 23 controls the multiplexer 16 for adding or executing a program, and controls the program counter 20 and the command address counter 19.

In addition, a liquid crystal display control circuit 25, a D/A convertor 26, an A/D convertor 27, and each circuit of a timer 28 and an interface 29 are connected through a bus 24, and an EEPROM 30 is connected to the interface 29. An oscillation circuit 32 is also provided. A resonator 31, which generates a fundamental clock signal, is connected to the oscillation circuit 32. A frequency divider 33 receives the output from the oscillation circuit 32, and supplies the divided output to the operation circuit 22.

At the start of operation of,the operation circuit 22 the program stored in the ROM 11 is executed, and the operation circuit 22 reads program instructions stored at a predetermined address in the EEPROM 30, a mode flag, and an address specifying the number of instructions and a change point, and sets respective data in each of the step register 13, the mode register 14, the command register 15, and the address setting circuit 18. The instructions for these initial processes are previously stored in the lower address of the ROM 11, and the same initial processing instructions are performed every time the operation circuit 20 starts to operate. After the initial processing is executed the stored program is executed.

For example if the invention is applied to a control circuit for a camera, a series of exposure operation, stroboscope charging control, film feeding control, and zooming according to known conditions for a release switch or a zooming switch are carried out.

For the purpose of illustration it is assumed that the program for zooming the shooting lens erroneously contains an instruction flashing the stroboscope while the shooting lens is being zoomed when the zooming switch of the camera has been pressed. Erroneous flashing of the stroboscope is a critical defect for a camera, leading to immediate stopping of the production.

In order to correct the erroneous flashing of the stroboscope, values to be written in the step register 13, the mode register 14, the command register 15, and the address setting circuit 18 are stored in the EEPROM 30 to modify the erroneous section in the program. That is, the address setting circuit 18 is set with the address in the ROM 11 in which the instruction code causing the erroneous flashing of stroboscope in the program controlling zooming is stored; an instruction code to replace the incorrect instruction code is stored in the command register 15; data indicating the mode of instruction modification is stored in the mode register 14; and a value corresponding to the number of instructions after modification is stored in the step register 13.

When the zooming control switch of the camera is pressed, and the zooming processing reaches the address where the error of the program exists, the command address counter 19 outputs a signal indicating coincidence of the addresses held in the address setting circuit 18 and the program counter 20. The PC control circuit 23 receives the coincidence signal from the command address counter 19, and outputs a signal to the multiplexer 16 for switching from the ROM 11 to the command register 15. Accordingly, subsequent instructions are executed according to the content of the command register 15, instead of'the ROM 11.

Figure 2 shows the operation of the program when the operation "modify" is performed. Here, it is assumed that the instructions held at addresses from 0109x to 010Cx in the ROM 11 are to be replaced by the instructions held at addresses 002Fx to 0032x in the EEPROM 30. The number of instructions in the command register 15 which are to be executed, i.e. 4, is stored in the step register 13, and the content of the step register 13 is initially transferred to the PC control circuit 23. Every time one byte of instructions in the command register 15 is executed the number of instructions to be executed is decremented, and the command address register 17, which specifies an address in the command register 15, is incremented. At the same time, the program counter 20 is also incremented. When the number of instruction steps to be executed reaches zero by repeating these steps, the PC control circuit 23 outputs a switching signal to the multiplexer 16 and, at the same time, outputs the clear signal to the command address register 17 to initialize the command address register 17, and the process returns to the program stored in the ROM 11.

Figure 3 shows the operation path of the program when performing "add." Here, it is assumed that instructions in addresses 002Fx to 0032x in the EEPROM 30 are to be added between an address 0108x and an address 0109x in the ROM 11. When the program reaches the address at which the extra instructions are to be added, the command address counter 19 outputs a signal indicating the coincidence of the address held in the address setting circuit 18 and the program counter 20. The PC control circuit 23 receives the coincidence signal from the command address counter 19, outputs a switching signal to the multiplexer 16, and proceeds to the execution of the extra program instructions in the EEPROM 30. The number of instruction in the command register 15 which are to be executed, i.e. 4, is stored in the step register 13, and the content of the step register 13 is initially transferred to the PC control circuit 23. Every time one byte of instructions in the command register 15 is executed the number of instructions to be executed is decremented, and the command address register 17, which specifies an address in the command register 15, is incremented. In order to prevent displacement of the address when returning to execution of the program in the ROM 11, the program counter 20 is not changed. When these steps have been repeated so that the number of instructions specified by the step register 13 have been executed, the PC control circuit 23 outputs a switching signal again to the multiplexer 16, outputs a clear signal to the command address counter 17 to reinitialize the command address counter 17, and continues executing the program stored in the ROM 11.

If it is desired to delete an instruction erroneously flashing the stroboscope, for example, the erroneous flashing of the stroboscope is inhibited by setting a non-operation code (NOP) in a command register 15, and 1, indicating "modify" in the mode register 14. Alternatively if mode register 14 is loaded from the EEPROM with 2, indicating "ignore", erroneous instructions stored in ROM 11 can be ignored.

In addition, as a modification of "add," when it is desired not to perform the operation of a specific length of instruction code after a specific address, a code is set in the command register 15 to jump the address next to the last address of the instruction. Then, the instruction code is not executed so that the instruction code of the specific length is effectively "ignored."

Although replacement and deletion of an instruction are separately described in the above embodiment, if they are performed in combination, more complicated errors in the program can be handled. In addition, it is needless to say that the number of correction points and correctable instructions may be appropriately increased or decreased.

Furthermore, although the embodiment describes the EEPROM 30 to be externally connected through the interface 29, it may be contained in the chip 10.

other circuits may be suitably arranged to be contained or externally connected according to a design considerations.

Addition or modification to a program written in a mask ROM can thus be performed by rewriting data in an EEPROM even after the ROM has been manufactured. Thus, it is significantly advantageous that correction of an error in the program becomes easy so as to minimize time and cost for correction.

Claims (12)

1. A control circuit for an electronic apparatus comprising:

a first read-only memory containing instructions relating to the operation of the electronic apparatus, the instructions being stored at respective addresses; a second memory for storing at least one operating instruction relating to a desired alteration in the operation of the electronic apparatus and data relating to an address in the first memory; a first register for.storing an address of the operating instruction in the first memory which is about to be performed; a second register for storing an address derived from the data stored in the second memory; means for comparing the stored addresses in the first and second registers, and, when the stored addresses are equal, carrying out the operating instruction stored in the second memory rather than the operating instruction in the first memory about to be performed.

2. A control circuit as claimed in claim 1, wherein the second memory is rewritable.

3. A control circuit as claimed in claim 1 or 2, wherein the second memory contains an instruction to carry out the operating instruction at a specified address in the first memory.

4. A control circuit as claimed in claim 1, 2 or 3, further comprising: 30 selection means connected to the first and second memories for outputting an operating instruction stored in either the first or second memory; and means for counting the number of executed operating instructions from the second memory; wherein 35 the selection means outputs an operating instruction stored in the first memory until the stored addresses in the first and second registers are equal, and then outputs an operating instruction stored in the second memory until the number of executed operating instructions from the second memory reaches a preset

5 number.

S. A control circuit as claimed in claim 4, wherein the second memory contains data relating to the number of operational instructions to be executed by the second memory.

6. A control circuit as claimed in claim 4, further comprising means for controlling the operation of the electronic apparatus in accordance with the output operating instructions.

7. A control circuit as claimed in claim 2, wherein the second memory is an EPROM.

8. A control circuit for an electronic apparatus comprising operation means operating according to a plurality of programs which controls the electronic apparatus, a first counter for storing an execution address of a first program, a second counter for storing an execution address of a second program, comparator means for comparing the addresses stored in said first and second counters and generating an output when they coincide, first and second storage means for storing said plurality of programs, selection means selecting either one of the first and second means and outputting a selected program to said operation means, third counter for holding the number of programs in said second storage means, changing according to execution, and outputting a signal when the execution completes, control means causing said selection means to select said second storage means according to the output of said comparator means and causing said selection means to select the first storage means according to the output of said third counter.

9. A control circuit substantially as herein described, with reference to the accompanying drawings.

10. An electronic apparatus incorporating a control circuit as claimed in any preceding claim.

11. A camera incorporating a control circuit as claimed in any one of claims 1 to 9.

12. A method of controlling the operation of electronic apparatus incorporating a control circuit as claimed in any one of claims 1 to 9, comprising storing operating instructions in the first memory during manufacture of the apparatus, and, in the event that an error is found in the stored operating instructions, storing amended operating instructions in the second memory.