GB2281467A - Image edge detractor and processor - Google Patents

Abstract

An image edge detection and processor performs real time reduction in the volume of data input (figure 4) 25 from an image sensor used as a front end sensor of a processing system, and a reduction in the necessary processing by a computer system to extract edge detection information by extracting pattern outline and relief contour detail 38, 39, 40 contained in an image and characterised by luminance frequency excursions through preset upper 40 and lower frequency limits 38. Such data input to a processing system may be image mapped edge data 38, 39, 40 or compressed data comprising partitioned lists of edge element identities. <IMAGE>

Description

IMAGE PATTERN THREAD PROCESSOR This invention relates to an image pattern thread processor.

Irnage sensors COO or equivalent, typically with operating bandwidths of Snshz or greater, generate on a continuous basis considerable volumes of data. Analogue to digital converters are becoming increasingly faster making real time input of data fro such devices, used as front end sensors, to computer processing systems a reality.

However the software task of real time data reduction to extract important image pattern thread i nf ormat ion, particularly when the images relate to a dynariiic scenario, presents a considerable processing load to any computer, Many applications could benefit from hardware data reduc t i on techniques which improves the image pattern thread information to data ratio of the input from such image sensors to computer systems.

The image pattern thread information contained in the composite video signal of an image sensor is generally contained in the upper region of the image sensor bandwidth, and spectral analysis or equivalent processing of this signal yields the binary event information of elements of image pattern threads.

The position within a CCD raster scan, that is within the field of view of the image sensor, of the occurrence of such binary events is also determinable Both the binary event information and event identities may be input to a computer system, the binary event data as an image mapped array, whilst the binary event identification lends itself to data compression techniques allowing partitioned (on the basis of line scan and attribute) lists of data to be formed further e:: < pediating the subsequent analysis of such data by other processing systems. Double buffering of memories used to pass such data to an e:: < ternal processing system allows, on a frame basis, a continuous throughput of data.

Visibility of the output of the image pattern thread processor is possible by the display of a composite video signal synthesised the by real time combination of the binary event signal with current stripped frame and line sync information from the image sensor According to the present invention there is provided an image patters thread processor capable of the real time e > .'.traction of important image pattern thread information from the composite video signal of an image sensor, COD or equivalent, comprising a luminance signal spectral analyser or equivalent capable of identifying image pattern outline and relief contour detail derived from luminance signal frequency excursions transi ting through a preset upper frequency 1 i ml. t or falling below a preset lower frequency limit where such events generate in real time a binary event signal and an associated identity for each such event and where such information may be passed to a further processing or display system.

specific embodiment of the invention will now be described by way of example with reference to the accompanying drawing in which Figure 1 shows a system block diagram identifying fur.--=tional areas comprising the image pattern thread processor and important signal i nf ormati on passed between these functions Figure 2 shows circuitry of lurisinance differential processor employed in identifying image pattern thread elements, Figure 3 shows detail of the double buffered memories comprising the inter processor data link.

Figure 4 shows images and waveforms associated with the system.

Referring to the drawing and in particular to figure 1 Composite Video CV1 waveform 26 from a CCD or equivalent image sensor IS 1 observing a real world scenario 25 is fed to the Frame Line Mask FLM 2 circuitry and to the Luminance Differential Processor LDP 3 circuitry and Display D 11.

The purpose of the Frame line mask circuitry FLM 2 is to strip from the Composite video signal CV1 26 the Frame and line sync information L 28 and pass this signal to the Video Mixer VM 4, and ADdress Generation ADG 5 circuitry, The Frame line mask FLM 2 circuitry also uses this stripped sync information L 2 to generate two further signals a Frame begin signal F 27, and a Luminance Mask signal M 33, both of these signals are sent to the address generation ADG S circuitry, the Mask signal M 33 is also sent to Luminance differential processor LDP 3, and Stack Pointer SP 6 circuitry, Referring in particular to figure 2 the Luminance differential processor LDP 3 circuitry operates on the Composite video signal CV1 waveform 26 performing spectral analysis on this signal to identify frequency excursions of the waveform through upper or lower settatle limits, This is achieved simply in this example by feeding the variatle gain signal frorn an emitter follower waveform 29, shown at the time slice ZZ, to two time differentiating OR circuits whose outputs 30 each drive a PNP transistor 12 and 13, one 12 biased on, and the other 13 biased off, Positive going differentials (frequency excursions through an upper limit) do not affect the transistor 12 biased on, but momentarily switch on the transistor 13 biased off and the output waveform 31 from this transistor feeds a schrflitt trigger inverter 14, Similarly for negative going differentials (frequency excursions falling below a lower limit) do not affect the transistor 13 biased off, but momentarily switches off the transistor 12 biased on the output waveform 32 feeds a double schmitt trigger inverter 1.5, The outputs from the inverters 14 and IS are combined and shaped by a monostable before gating with the Mask signal M 33 to produce the Binary Event BEC signal waveform 35 which is passed to the switch 24.

Similarly the shaped component upper and lower frequency excursion binary event signals BElJ and BEL waveforms 36 and E4 respectively are passed to switch 24, Switch 24 allows one of the signals BEC, BEU or BEL to be selected and passed to the Stack pointer SP 6 circuitry, Video mixer VM 4 circuitry and Write Memory Control WMC 7 circuitry.

The frequency characteristics of an image sensor ' 5 luminance signal are inherently polarised according to the relative alignment of the image sensors line scan and viewed features, Mixing of the composite video signal OVi with a signal 21 from a clock operating at the maximum bandwidth frequency of the image sensor allows some reduction in this polarisation for a single sensor system.

Referring again in particular to figure 2 the address generation ptDG 5 circuitry utilises a clock operating at the maximum bandwidth frequency of the image sensor and gated by the Mask signal M 33 the output from which drives cascaded counters within each luminance period, Elements of the cascaded counters are reset from characteristics of the Frame begin signal F waveform 27, and Frame and line sync signal L waveform 28, and the counters thereby generate a compound identity, equivalent to every luminance resolution period in the image sensors raster scan, that is for each pixel position in each line VI and every line scan within a frame SI both these signals are passed to the Write Memory Control WMC 7 circuitry, Frames of data are also counted by the Address generation NDG .5 circuitry and this signal FO is also passed to the Write memory control WMC 7 circuitry, the External Computer system ExCs 8 and The double buffered memories MAB 9 to allow synchronised use of these memories by WMC 7 and ECs 9, The Address generation P"DG .5 circuitry also generates an End Marker signal EM 37 which indicates the end of any particular luminance period and this signal is passed to the Stack pointer SP 6 circuitry and the Write memory control WMC 7 circuitry, Referring in particular to to figure 3 which shows the organisation of the MAB 9 memories comprising the pair of physically and logically partitioned memories M1A 50 and M1B 51. The memories Ni SC) and M1B 51 are si2ed according to the number of line scans in a frame, and resolution periods in a line scan, The memories are capable of registering data written within the resolution period of the image sensor.The memory address and data lines are accessed via sets of three state gates one set 52, 53, 54, 55 dedicated to the Write memory control WMC 7 and the other set 56, 57, 58, 59 to the read memory control of the External computer system ExOs 8. These memories are continuously selected and during each frame data is written by WMC 7 and read by the External computer system ExCs 8 these processes being performed one frame out of phase for each of the memories M1A 50 and M1 B 51, The Write memory control WMC 7 generates a write address Wi1 and data WD1 which are presented to the sets of three state gates 52, 54, and 53, 55 respectively, During frames when FO=1 the outputs from the gates 54 and 55 are enabled and drive memory M1B 51, write enable pulses WE1B are generated by WMC 7. For the read addresses Ri presented by the read memory control of the External computer system ExCs 8 to the sets of three state gates 56 and 58 only the gates 56 are enabled for frames when FO=1 and during these frame periods data RD1 in response to the OE1A signals generated by the External computer system ExCs 8 is returned through the enabled three state gates 57, On the subsequent cycle write addresses WN1 and data WD1 are presented to M1 via the sets of enabled three state gates 52 and 53 respectively while data RD1 is read from M1B using the enabled three state gates 59 corresponding to the read addresses RA1 presented via the enabled three state gates 5, Referring again in particular to figure 1 the Stack pointer SP 6 circuitry accepts the End marker signal EM, waveform 37 and the switch 24 selected binary event signal BEC waveform 35, or EEI.I waveform 36, or BEL waveform 34 and counts events within a line scan to allow sequential address generation P within logically partitioned stacks defined within the memories M1A A SO and M1B 51, where each new address is the address into which the ne:'.t entry in any particular stack will be made. The stack pointer P is reset at the beginning of each new line scan by the action of the Mask signal M oi going low, For data compression of image pattern thread data the Write memory control WMC 7 has at any particular time the identity of the available memory M1A SO or M1B 51 decided in this case by the Frame FO signal, the current logically partitioned stack base within memory SI (line number within the frame), it also has the vector identity VI (representing the position in a line scan of any possible luminance frequency excursion binary event).Further during any particular line scan the address P from the Stack pointer SP 6 circuitry indicates the sequential word in a particular stack to be written, When a frequency excursion event occurs the associated binary event in the signal BEC waveform 35 or BEL waveform 34, or BEU waveform 36 depending on switch 24 position is used by the Write memory control WMC 7 circuitry to generate the WE for the memory in question for this particular frame period. when the data WD1 written into the word, indicated ty the address combination WN1, formed from the stack identity SI and the stack address P, will be the vector identity VI (WA1=SI+P WD1=VI), At the end of each line's luminance period the end marker signal EM 37 will be interpreted as though it were a binary event and will cause a word WD1 to be written to the current stack whose identity is unique and indicative on reading that the logical end of a particular stack of data has been reached.During alternate frames stacks written by the Write memory control WMC 7 circuitry in the previous frame may be read asynchronously by the E < ternal computer system E' < Cs 8, For the writing of image mapped binary event data, the Write memory control WMC. 7 circuitry again identifies the appropriate memory to write to, for the current frame, on the basis of FO but now generates an apprc.priate write enable command WE1A or WEIB for every address WA1=EI+VI with data WD1=(BEC or BEU or BEL) as a function of the switch 24 setting, Continuous asynchronous access to data written during the previous frame can be made by the External computer system E < Cs 8, The Video Mixer VM 4 combines Binary event data BEC, BEU, or BEL (function of switch 24) with Frame and line sync signal L 28 to form a composite video signal CV2 which is passed to the Display D 11 allowing operator observation of the image pattern thread processor output 38 for lower frequency excursion events, 39 for combined upper and lower frequency excursion events, and 40 for upper frequency excursion events, The Display D 11 also allows viewing of composite video CVi representing the normal video image 25 waveform 26,

Claims (7)

1. ; - .rt-)--; : P I#CIIMS '- -' An image

   -capable-of the real time extraction of important image patterN tnreaa information from the composite video signal of an image sensor, CCD or equivalent, comprising a luminance signal spectral analyser or equivalent capable of identifying image pattern outline and relief contour detail derived from luminance signal frequency excursions transiting through a preset upper frequency limit or falling below a preset lower frequency limit where such events generate in real time a binary event signal and an associated identity for each such event and where such information may be passed to a further processing or display system,
2. 2 Sn image pattern thread processor as claimed in Claim 1 wherein real time identification means is provided to log the position within the image sensors raster scan, that is within the field of view of the image sensor, of each binary event representing elements of image pattern threads,
3. 3 fin image pattern thread processor as claimed in Claim 1 or Claim 2 wherein real time identification means is provided to count the sequential binary events of particular attributes (upper or lower frequency excursion events) within each line scan of the image sensor,
4. 4 Sn image pattern thread processor as claimed in Claim 1 or Claim 2 or Claim 3 wherein communication means are provided to output for system external processing at the image sensors frame rate partitioned sequential terminated lists of binary event identities representative of imaged pattern thread elements.
5. S An image pattern thread processor as claimed in Claim 1 or Claim 2 or Claim 3 or Claim 4 wherein communication means are provided to output for system external processing at the image sensor frame rate the binary event data as an image mapped array.
6. 6 An image pattern thread processor as claimed in Claim 4 or Claim 5 wherein output double buffering of image pattern thread data means are provided to pass such data to an external processing system allowing continuous data output at the image sensor frame rate with maximum data latencies of 20ms (UK),
7. 7 An image pattern thread processor as claimed in any preceding Claim wherein data reduction means is provided to expediate the further analysis of image pattern thread data 8 An image pattern thread processor as claimed in any preceding Claim wherein interference means are provided whereby the mixing of a clock signal operating at the maximum bandwidth frequency of the image sensor allows a reduction in the polarisation effects of relative imaged feature and and line scan orientation for single sensor systems, 9 An image pattern thread processor as claimed in any preceding claim wherein visibility of the output of the image thread processor is possible in real time by the display of composite video synthesised by the combination of the binary event signal with current stripped frame and line sync inforrnation from the image sensors composite video signal, 10 An image pattern thread processor as claimed in any preceding claim wherein a variety of such processors are employed to simultaneously identify image pattern thread elements with differing attributes for simultaneous output to a further processing or display system, 11 Sn image pattern thread processor substantially as described herein with reference to figures 1-4 of the accompanying drawing.