GB2274738A - Cooling for 3-D semiconductor packages - Google Patents

Abstract

A high density, three-dimensional thermal packaging system for integrated circuits is provided which accommodates the requirements for heat dissipation in high power, three dimensional arrays of ICs. Thermal units 22 are provided in parallel planes to the integrated circuit die and external package interconnects 18, while stacking of the units occurs orthogonally thereto. Each individual die has its own exclusive heat dispersion unit (heat sink or spreader). The die within the centre of the three-dimensional stack should therefore not get substantially hotter during operation than those die at the extremities of the three-dimensional stack. <IMAGE>

Description

COOLING FOR 3-D SEMICONDUCTOR PACKAGES The present invention relates to the packaging of semiconductor devices in three dimensional arrays, and in particular to apparatus for providing adequate heat-sinking for the requirements of such devices in such three dimensional arrays.

As the operational speed of processor chips increases, access to greater amounts of memory space in correspondingly shorter times is required. If the memory devices providing such memory space are not accessed and written to at comparable rates to that at which a central processor unit (CPU) is working, the value of having such a high speed CPU is compromised, or may be lost altogether. Access times are, in part, determined by the physical distance between the CPU and the memory devices, and conventional printed circuit board (PCB) or multi-chip module (MCM) layouts may result in inter-chip distances effectively too large to permit the access times required.

Various solutions to this problem by achieving high memory density (ie.

multiple memory devices located within a short distance of the CPU devices) have been proposed. A number of proposals include the use of threedimensional packaging systems in which devices are not only distributed about an x-y plane of a PCB or MCM, but are also stacked in a z-direction perpendicular thereto.

While this format achieves desirable effects with respect to the memory density, a number of other problems arise in connection with this strategy.

Various three-dimensional packaging systems employ array interconnection techniques by way of "buses" running vertically up and down the edges of a plurality of devices placed in a stack formation. Since the device connections are commonly provided at the perimeters of the packaged devices, this array interconnection technique is a convenient mechanism for such three dimensional structures. However, this overlooks the important consideration of heat dissipation, and generally the thermal management requirements of modern, high speed, highly integrated devices.

With current trends toward increasing component integration and reduction in minimum feature sizes, future memory devices will have even further increased operating power thus exacerbating the problem of providing adequate thermal management. Present memory device power outputs are of the order of 1W. This is close to the present performance limit of conventional packaging technology, and already the capabilities of some standard packaging types have been exceeded. It is envisaged that power dissipation requirements of between 2.25 and 20W might reasonably be anticipated over the next fifteen years given present trends.

It is therefore an object of the present invention to provide a three dimensional packaging strategy which provides adequate thermal management of both current and future device power dissipation requirements.

It is a further object of the present invention to provide such thermal management in conjunction with the high density packaging techniques necessary for high speed operation of electronic systems.

It is a further object of the present invention to provide such a three dimensional packaging strategy using modifications to existing standard packaging styles, including plastic- and ceramic-based.

According to one embodiment of the present invention, there is provided a package for a semiconductor device comprising: a body for the encapsulation of the device; a chip attachment portion within the body for locating the chip in an x-y plane; heat dissipation means extending outward beyond the body in at least one direction parallel to the x-y plane; a plurality of electrical interconnects extending outward from the chip substantially parallel to the x-y plane to at least one edge of the package; engagement means for coupling a plurality of said packages in a stack formation extending in a z-direction perpendicular to said x-y plane, with each heat dissipative means being parallel to but separated from adjacent heat dissipative means.

Each individual chip, or die, has its own exclusive heat dispersion unit (heat sink or spreader). A die within the centre of a stack formation will thus not operate at a substantially higher temperature than a die operating at an extremity of the stack formation. In prior art examples, heat generated at the centre of the stack must pass through other die and packaging material in order to be dissipated to the ambient surrounds.

Embodiments of the present invention will now be described by way of example, and with reference to the accompanying drawings in which: Figure 1 shows diagrammatically: (a) plan view, (b) end elevation and (c) perspective views of plastic encapsulated, vertical connection type packages according to the present invention; Figure 2 shows diagrammatically: (a) plan view and (b) end elevation of a plastic encapsulated, J-lead array interconnection type package according to the present invention, and (c) an end elevation of a plurality of such packages assembled; Figure 3 shows diagrammatically: (a) plan view and (b) end elevation of a glob-top encapsulated, J-lead array interconnection type package according to the present invention, and (c) an end elevation of a plurality of such packages assembled; Figure 4 shows diagrammatically: (a) plan view and (b) end elevation of a glob-top encapsulated, J-lead array interconnection type package with silicon heatsink arrangement according to the present invention, and (c) an end elevation of a plurality of such packages assembled; Figure 5 shows diagrammatically: (a) plan view and (b) end elevation of a glob-top encapsulated, conductive adhesive array interconnection type package according to the present invention, and (c) an end elevation of a plurality of such packages assembled; and Figure 6 shows diagrammatically: (a) plan view and (b) end elevation of a plastic lid encapsulated, wire bond array interconnection type package according to the present invention, and (c) an end elevation of a plurality of such packages assembled.

A number of embodiments of the invention are provided in figures 1 to 6. The present invention is readily applicable to most common package types and these are exemplified herein. Low cost package types are exemplified by figures 1 to 3, typically using plastic packaging technology. Higher performance packaging designs are exemplified in figures 4 to 6 which use more exotic materials and fabrication techniques of greater complexity.

With reference to figure 1, a package 10 comprises a plastic moulded body 12 in which is encapsulated an integrated circuit die 14, such as a RAM device. The bonding pads of the die 14 are wire bonded in known manner to a conventional lead frame type planar interconnect 16 which provides interconnections to a plurality of edge pin connectors 18 which extend outward from one edge 20 of the body 12 of the package 10. A heatsink, or thermal unit 22 to which the die 14 is attached within the body 12 extends outward from the opposite edge 24 of the body 12. Engagement means in the form of pins 26 and holes 28 are provided in the body 12 for connection of a plurality of the packages into a three dimensional array 30. The array interconnection system providing inter-package electrical coupling is provided by way of a printed circuit board into which the pins 18 locate.This embodiment exemplifies the use of an x-y plane in which the chip or die 14 lies, with planar interconnect and package electrical connections provided therefrom parallel to the x-y plane of the chip. The package contacts (pins 18) to the device are provided in, for example, the positive x-direction, and the thermal unit 22 is provided extending in the negative x-direction, thereby allowing stacking of packaged devices in the z-direction to form a three dimensional array. The package contacts may be arranged in a zig-zag format to increase pin density as in ZIP style conventional packages. The body 12 of the package effectively provides a minimum physical separation of the thermal units 22, necessary to provide adequate flow of air or other thermal energy transfer medium therebetween.

In the remaining figures, component parts which are functionally equivalent in each embodiment are provided with reference numerals corresponding to figure 1.

With reference to figure 2, a package 40 also comprises a plastic moulded body 12 in which is encapsulated an integrated circuit die 14, such as a RAM device. The bonding pads of the die are of the centred type, extending the length of the die in the centre thereof. These are wire bonded 15 in known manner to a conventional lead frame type planar interconnect 16 which provides interconnections to a plurality of contacts 18 in the form of J-lead edge connections which extend from two opposing edges 20 of the body 12 of the package 40. A heatsink, or thermal unit 42 comprising a plurality of fins is attached to the die 14 within the body 12 and extends outward from both opposing edges 24 of the body 12. The engagement means for stacking a plurality of packages is provided by the J-lead array interconnections 46 to form a three dimensional array 50.Inter-package electrical coupling is also provided thereby. Metallic interconnections may be formed by solder dipping, conductive paste, plating processes etc. This embodiment exemplifies the use of an x-y plane in which the chip or die lies, with electrical connections provided therefrom parallel to the x-y plane of the chip. The package contacts (J-leads 46) to the device are provided in, for example, the positive and negative x-direction, and the thermal unit 42 is provided in the positive and negative y-direction, thereby allowing stacking of packaged devices in the zdirection. The body 12 of the package again effectively provides a physical separation of the thermal units 42, necessary to provide adequate flow of air or other thermal energy transfer medium therebetween.

Figure 3 shows a package 60 of similar arrangement to figure 2, but wherein the wire bonding 15 is effected from bonding pads to an interconnect substrate 62. Thermal unit 42 is mounted on the underside of the interconnect substrate 62. Here, the "body" of the package comprises the thermal unit upon which the die is mounted, and a glob-top encapsulation 66. The use of an interconnect substrate 62 carrying the body and thermal unit allows the formation of additional passive components 64 on the substrate 62. Separation of the thermal units is effected by the J-lead array interconnections 46.

With reference to figure 4, a package 70 comprises a combined interconnect substrate and thermal unit 74 from bonding pads to a plurality of package contacts 18 in the form of J-lead edge connections which extend from the die 14 to two opposing edges 20 of the substrate 72. In this embodiment, the substrate 72 also acts as the thermal unit, and in this aspect extends outward from the die in both x- and y-directions. The engagement means for stacking a plurality of packages is provided in the form of the J-lead edge connections to form a three dimensional array 80. The array interconnection system providing inter-package electrical coupling is also provided thereby. The die protection 66 and the combined thermal/interconnect substrate form the "body" 62 of the package.This embodiment exemplifies the use of an x-y plane in which the chip or die lies, with electrical connections provided therefrom parallel to the x-y plane of the chip, carried on the thermal unit 72. The package contacts (J-leads 46) to the device are provided in, for example, the positive and negative x-direction on the thermal unit 72, which also extends outwards from the die in the positive and negative x- and y-directions, thereby allowing stacking of packaged devices in the z-direction to form the three dimensional array 80. The body 62 of the package or the discrete components (eg. chip capacitor 64) again effectively determines a minimum separation of the thermal units 72 necessary to provide adequate flow of air therebetween.

Figures 5 and 6 demonstrate similar variations on the package 70 of figure 4, with the following distinctions. Package 90 (figure 5) offers an alternative surface mount array interconnection style in which the engagement means used to create a three dimensional array 92 of packages 90 is in the form of a conductive adhesive 94 between the contacts 18. Figure 6 shows a package 100 according to a further arrangement using wire bonded array interconnection system 104 providing the inter-package electrical coupling. The body of the package encapsulating the die is provided by the substrate and a plastic moulding 106, which also provides the engagement means 108,110 for stacking a plurality of packages to form the three dimensional array 102.

The foregoing embodiments are illustrative only, and it will be understood the principle underlying the invention can be applied to a wide range of different packaging styles, planar interconnection and array interconnection techniques, which may be influenced by many factors, such as the functional specification of the chip or suitability of existing assembly production lines.

A number of different materials and processes may be employed in combination to form the various packaging styles, and typical examples are given in the following table.

Example Thermal unit Planar Array inter- Die protection figure no interconnect connection substrate 1 Lead frame Wire bonding to Printed circuit Plastic alloy leadframe to board encapsulation PCB 2 High thermal Wire bonding to Soldered J-leads Plastic conductivity leaciframe encapsulation materials 3 Metal I ceramic Wire bonding to Soldered J-leads Glob top copper / polyimide substrate 4 Silicon Wire bonding to Conductive Glob top screen printed adhesive conductors over connections to dielectric layer leads S Aluminium Wire bonding to Conductive Die coat thin film adhesive to plated edge connections 6 Polysilicon Wire bonding ~ Wire bonding Plastic lid Other examples: Lead frame FR4. TAB Ceramic lid.

alloys. Culpolyimide. connections. Metal lid.

Aluminium. BT. Plating. Plastic cover.

Copper. Screen printed Solder Plastic Metal filled conductors. connections. moulding.

ceramics. Thin film Conductive Dam and gel Silicon. deposited pastes. coat.

Metals. conductors. Welded unit. Other methods Ceramics. Printed circuit Interpossers. of die W/Cu . boards. Conductive protection.

Molybdenum. TAB tape. bumps.

Other heatsink Other types of Pins.

or heat conductor on Flexible or rigid dispersive dielectric substrates.

materials. materials. Other types of electrical connection processes.

It will be understood that the combinations in the table are exemplary only, and not exhaustive. A range of semiconductor chips (not only memory chips) with relatively low pin counts (eg. less than 50) may be adaptable to this type of three-dimensional stacking with individual cooling, for example buffer / driver chips. Although this type of heat dispersion has been illustrated in respect of low pin count packages where pins project from only one or two sides, it will be understood that higher pin count package three-dimensional stacks are achievable with pins projecting from three or four sides by suitable modification of, for example, the embodiments of figures 4, 5 or 6. This could also be done, for example, by using vias through the heat dispersing element while still retaining the basic cooling features described so far. The examples given can be further developed to include not only packages containing a single chip, but also multiple chip packages.

Claims (8)

1. A package for a semiconductor device comprising: a body for the encapsulation of the device; a chip attachment portion within the body for locating the chip in an x-y plane; heat dissipation means extending outward from the body in at least one direction parallel to the x-y plane; a plurality of electrical interconnects extending outward from the chip substantially parallel to the x-y plane to at least one edge of the package; engagement means for coupling a plurality of said packages in a stack formation extending in a z-direction perpendicular to said x-y plane, with each heat dissipative means being parallel to but separated from adjacent heat dissipative means.

2. A package according to claim 1 wherein the engagement means forms part of an electrical array interconnection system between a plurality of stacked packages.

3. A package according to claim 1 wherein the engagement means forms part of the heat dissipation means of each package.

4. A package according to any previous claim wherein the electrical connections extend outward generally in the positive x-direction to a plurality of contacts at one edge of the package, and the heat dissipation means extends outwards from the body generally in the negative x-direction.

5. A package according to any one of claims 1 to 3 wherein the electrical interconnects extend outward in both positive and negative x-directions, and the heat dissipation means extends outwards from the body in at least one of the positive or negative y-directions.

6. A package according to any preceding claim wherein the heat dissipative means comprises a finned or ribbed structure.

7. A package according to any one of claims 1 to 3 wherein the heat dissipative means extend outward generally in the positive and negative xdirections; wherein the electrical interconnects are formed thereon; said package further including a plurality of contacts at the outer edges of the heat dissipative means.

8. A package according to any one of claims 1 to 3 wherein the heat dissipative means extend outward generally in the positive and negative x- and y-directions; wherein the electrical interconnects are formed thereon; and further including a plurality of contacts at the outer edges of the heat dissipative means.