GB2274193A - Disk copying apparatus - Google Patents

Abstract

A disk copying apparatus having a master control circuit and a respective disk drive control circuit for each of a number of disk drives arranged to receive and write on respective target disks onto which the data or program material is to be copied, in which the master circuit includes master memory means of adequate capacity to store the entire material to be copied, and each drive control circuit includes respective drive memory means to store a portion of the material to be copied, in which each drive control circuit is arranged to cause its disk drive to write such portion of material to a disk therein autonomously, and in which the master circuit is arranged to poll each drive control circuit successively and supply a further portion of material to any drive control circuit which has completed the writing of a previously supplied portion of material. <IMAGE>

Description

IMPROVEMENTS IN OR RELATING TO APPARATUS AND METHOD FOR COPYINGININFORMATION ONTO DISK MEDIA The oresent invention relates to a high speed, multi-format disk duplication system, which is particularly but not exclusively for use in a production environment.

It is an object of the present invention to provide an apparatus and method for reproducing or copying software and/or data, on floppy disk media of various formats. or on other similar media.

Accordingly in one aspect the present invention provides a disk copying apparatus having a master control circuit and a respective dis drive control circuit for each of a number of disk drives arranged to receive and write on respective target disks onto which the data or program material is to be copied, in which the master circuit includes master memory means of adequate capacity to store the entire material to be copied, and each drive control circuit includes respective drive memory means to store a portion of the material to be copied, in which each drive control circuit is arranged to cause its disk drive to write such portion of material to a disk there in autonomously, and in which the master circuit is arranged to poll each drive control circuit successively and supply a further portion of material to any drive control circuit which has completed the writing of a previously supplied portion of material.

Preferably such portions of material comprise streams of bits of data or program information which are of a chosen length, such length being independent of any track capacity upon the target disks.

Preferably the apparatus is arranged to be used in association with a microprocessor based computer including a suitable disk drive by which the material to be copied may be loaded from a master disk bearing the material, into the master memory means.

Preferably such computer includes a fixed storage disk system onto which such material may be copied and stored before being written to the master memory means.

Preferably said master circuit includes a master microprocessor arranged to control the function of the master circuit.

Preferably the disk drive control circuits each include a respective drive microprocessor arranged to control the operation of the disk drive control circuit.

In order to promote a fuller understanding of the above, and other, aspects of the present invention, an embodiment will now be described, by way of example only, with reference to the accompanying drawings in which: Figure 1 shows an overall schematic view of an embodiment of the invention in association with a user interface in the form of a microprocessor based personal computer, Figure 2 shows a scnematic view of a tower which houses a number of floppy disk drives in the embodiment of Figure 1.

Figure 3 shows a block circuit diagram of a disk drive board whicn is provided one for each disk drive in the embodiment of Figure 1.

Figure 4 shows a backplane to receive and connect a number of the disk drive boards of Figure 3 together with a master board, Figure 5 shows a block circuit diagram of the master board of the embodiment of Figure 1 which is associated with a number of the master boards of Figure 3, and Figure 6 shows a block circuit diagram of a link adapter used in the embodiment of Figure 1, within the computer.

Fig 1 shows the overall system as presented to the user. It consists of a user interface and one or more disk towers. Extra towers can be added indefinitely to provide the required copying throughput.

The user interface is based on a standard personal computer, with the addition of an adaptor card to enable it to communicate with the towers. It provides a keyboard and screen, a fixed disk drive for storage of the embodiment operating software, and a floppy disk drive for receiving software updates. The fixed disk drive is also used for storing images of floppy disks for duplication.

Each tower contains up to 10 disk drives, each with a red and a green LED to indicate the copy status of the disk in that drive. The towers can be configured for a variety of different drive types, including 5.25' HD, 3.5" HD. and 3.5" ED. For simplicity present software requires that all the drives within one tower be of the same type.

Connections between the user interface and the first tower, and between towers, is made using a high speed point-to-point data link.

Inside the tower Inside each tower there is a "drive board" connected to each installed disk drive, a "backplane" into which the other cards are plugged, a "master board", and a power supply. The connections between these items are illustrated in Fig 2.

The essential operation of the system is as follows. The master board has a block of DRAM large enough to store an image of the entire disk to be duplicated. The drive boards have enough RAM to store one or more tracks of data (ideally two - one track on each side of the target disk). The master board polls each drive board in turn until it finds one which is ready to copy; it then halts the processor on that drive board, loads in some data to be copied, and then allows the processor to continue. The drive board performs a copy and/or verify of the given data completely autonomously, during which time the master board deals with the other drive boards. When a drive board has finished an operation, it raises a flag which indicates that it is ready to be given another task, i.e. some more tracks to be copied.

Status information is passed between the master boara and the tre board using reserved locations within the drive board's memory. The drive board can thus signal problems (e.g. verify errors',, which the master board can relay back to the user interface.

The autonomous operation of each arive board means that no synchronisation whatever is required between the disk drives, eliminating the "belts and pulleys approach of some other bulk copying systems. In addition, batches of disks do not have to be loaded simultaneously since each drive board keeps track of how far it has progressed through copying its own disk. This means that disks can be loaded in rotation very efficiently by the operator.

The individual boards are described in more detail in subsequent sections.

Copying strategy A floppy disk encodes data as a series of flux transitions; the disk drive presents these to the drive board as a series of pulses. Since these pulses always occur (nominally) at the centre of a fixed bit cell period, the embodiment records the presence or absence of a pulse as a '1' or a '0' respectively. No attempt is made by the drive board to decode the disk data further than this, e.g. into bytes or sectors.

This "low-level" approach has great advantages. The embodiment can copy data streams of any format, e.g. FM, MFM, GCR. It can also copy "copy-protected" disks, i.e. disks where the data format has been deliberately corrupted to enable it to be identified as a master disk.

since the corrupted data stream is copied verbatim.

The disadvantage is that more memory is required to store each track, since the presence or absence of both "clock" and "data" pulses is recorded - for FM and MFM, this doubles the memory requirement.

However, compression is applied to the data before storing the image on the user interface fixed disk, so the only overhead is additional RAM on the drive boards and master board.

After writing a track, to verify that the copy reads back correctly it is necessary to synchronise the data being read off disk with the data image stored in RAM on the drive board. It is not sufficient simply to wait for the index hole to come round. Synchronisation is performed by waiting for a special sequence of pulses known as an "address mark" to occur; each disk format has its own address mark sequence(s) used to indicate the start of a sector header or the start of sector data. The address marks break the normal data coding rules, so that user data cannot be mistaken for an address mark.

The embodiment drive board implements the address mark detector as a programmable finite state machine. This works because any data pattern to be matched can be represented as a regular expression, which can be mechanically turned into an NFA (non-deterministics finite state automaton) and then into a DFA ideterministe finite state automaton.

This approach allows any address mark pattern, up to the size of tne DFA state table, to be detected.

Some care is also required when reading the master disk. in case no so or dirt causes it to be misread. The embodiment reaas each track twice, and accepts the track if the two versions tally (using address marks to synchronise between the two streams). In addition, high-level decoding of the data is performed on the master board, using a knowledge of the recording systems and disk formats in general use. It performs all the data checking that a conventional disk controller would perform, such as CRC checking. If an error is detected, a warning is issued to the user, but the process is allowed to continue; such a format error may just be part of a copy protection system. The system can be expanded to process new modulation systems and/or disk formats simply by updating the operating software.

When reading in the master disk, care must also be taken with write splice points, i.e. those points where the disk head was switched in and out of write mode when the master disk was originally made. These points can cause a track on the master disk to read differently each time (necessitating the use of address marks to re-synchronise, as referred to above), but could also create stretches of "uncopyable" data. This is data which cannot be guaranteed to copy and verify back correctly, such as a long stream of O's (i.e. a long period without any flux transition), or for MFM, two adjacent 1's (MFM requires one, two or three gaps between each flux transition). However, since write splice points are by definition outside of the useful data area of the disk, the master board alters these areas into suitable, verifiable sequences (e.g. 10101 for MFM).

The drive board Fig. 3 shows a block diagram of the drive board. High-speed CMOS (HC) technology is used throughout for low power consumption. The processor used is an 80C188; the HOLD and RESET lines, plus an interrupt line (labelled "Host Flag") can be controlled by the master board via the backplane; the HOLDA line, plus a data bit (labelled "Slave Flag") can be polled by the master board. When the processor is in the HOLD state, it relinquishes its local data bus and the master board can take it over to load up programs and data. 64K of RAM is sufficient to hold the drive control program and 2 tracks of HD data; 128K is required for ED.

The PIO (Parallel Input/Output) is used for a number of purposes. PIO lines are buffered and used to directly access the majority of control and status lines on the drive itself, plus the status LEDs. PIO lines are used to control the various state machines on the board, e.g. to select the data rate division ratio. In addition, the PIO is used to double-buffer the data going to or from disk. Data is transferred 8 bits at a time between the PIO and the data shift register; the PIO then raises its "interrupt request" line which is connected to the "DMA request" line of the microprocessor, causing another data byte to be transferred. This double buffering means that the exact time of the DMA data transfer is not critical, as long as it happens within 8 ri cells.

The bit cell data clock is generated by a clock extraction state machine, which either phase-locks to the incoming data stream (for read or verify), or generates a fixed-rate clock (for write). This clock may be 1, 1/2 or 1/4 times the maximum data rate for the board, which is set by the master crystal installed. The board is designed to handle a maximum MFM data rate of 1250kbps, corresponding to a bit cell rate of 2500kbps and a crystal frequency of 40MHz. Most drives have a maximum MFM data rate of lDOOkbps or 500kbps.

The address mark detector consists of a "current state" latch, feeding the address inputs of a "state lookup" RAM, whose outputs feed back into the "current state" latch. One of the address inputs also comes from the current data bit read from disk, and one of the data outputs connects to the data transfer state machine to act as a "match" flag.

The 80C188 can program any required state table, and thus match any address mark sequence, up to the maximum number of states which can fit into the RAM (128 in this implementation). It is also possible to program the state machine to search for two or more different address mark sequences simultaneously. For extra flexibility, 3 bits from the PIO are used to select one of 8 stored state tables to use.

The data transfer state machine transfers data from the PIO to the shift register (for write or verify), or from the shift register to the PIO (for read), every 8 data clocks. For verify, it also waits until an address mark has been found before commencing, and compares the data coming off disk with that coming out of the shift register bit-for-bit.

If a mismatch is detected, the transfer is terminated and the microprocessor interrupted.

The write precompensation state machine turns a '1' from the shift register into a pulse, indicating to the drive that a flux transition is required. The pulses at the start and end of a pulse train (1010101...) are adjusted in their timing according to the standard MFM write precompensation algorithm.

The backplane The master card and the drive cards communicate over an 8-bit bus, and the backplane provides the electrical connections between the cards and termination for the signal lines. In addition, the backplane is responsible for selecting one of the drive cards for the master card to communicate with. It does this by latching the data on the bus during a card select" bus cycle, and then asserting the CRDSEL input to the appropriate card (and deasserting CRDSEL on all other cards). A card will only respond to bus cycles when its CRDSEL input is active.

The bus consists of the following lines. All are driven by the master board except where indicated, and all are commoned except for CRDSEL.

BUSSTB Data strobe. Data is latched on the trailing edge.

BRESET Global reset signal, resets all cards.

FCO-2 Bus function code (see below AO-7 Low address DO-7 Data (driven by master card for write cycle, drive card for read cycle) CRDSEL Card select (driven by latch and demultiplexor on backplane) The direction and function of each data transfer are determined by the function code lines FCO-2, as indicated in the following table together with the activity on the address and data lines at the same time.

"Write" indicates transfer of data from the master card.

FC Direction Cycle AO-7 DO-7 000 Reserved 001 Write Mid address N/A mem A8-15 010 Write High address N/A mem A16-23 011 Write Card select N/A Card no. to select 100 Write Control N/A DO-2 = reset, hold, hflag 101 Read Status N/A DO-3 = 0, holda, sflag, 0 110 Write Data mem AO-7 data to write 111 Read Data mem AO-7 data read The middle and high addresses are latched in separate bus cycles on the drive board. This means that an uninterrupted burst of up to 256 byte transfers can occur before having to perform another write mid address or write high address cycle.

The read status cycle is also used to detect the presence or absence of a drive card, since DO and D3 are driven low. If the card is absent, they will float high due to 2pullups on the backplane. By selecting "drive" 15. the backplane itself is selected and will respond to a read status cycle to verify it is present.

For systems using drives whose maximum data rate is 500kbps, there is less bus activity and it is possible to link two backplanes together to control up to 20 cards from one master board. This is illustrated in fig 4.

A spare backplane slot is provided to interface to a disk autochanger subsystem.

The master board The master board is responsible for storing the entire disk image, transferring tracks to the drive boards for copying, and returning results to the user interface (including relaying results from other towers further down the chain). A block diagram of the master board is shown in Fig. 5.

The master board is based on the Inmos T400 transputer. This 32 bit processor includes two high-speed asynchronous serial links, timing strobe and refresh generation for DRAM, and 2K of workspace RAM on a single device. The instruction set of the transputer (which includes CRC calculation and block move) is particularly suitable for this application. 4Mb of DRAM is sufficient to hold the image of a Hu rsk; SMb is required for an ED disk.

Interfacing between the 32 bit data bus of the transputer and the 8 bit backplane bus is achieved using four 8 bit bidirectIonal data latches and a state machine. The backplane is mapped into the transputer's memory space; whenever a write access is made into this space, the current state of address lines A2-11 is registered, along with the 32 bit data word. The registered values of A2-7 generate backplane addresses A2-7; A8-10 generate FCO-2; and All indicates to the state machine whether a single byte or four bytes are to be transferred.

The bus state machine performs the appropriate bus cycle(s), enabling one of the four 8 bit registers onto DO-7, and generating bus AO and Al. Meanwhile, the transputer is free to fetch the next data word to be transferred; if it attempts to write this word to the backplane before the previous transfer has completed, it is held off using the transputer's MemWait input. This overlapped fetching and outputting of data, combined with the transputer's block move instruction, gives full bus usage when writing data, which forms the bulk of bus activity when copying or verifying disks.

When reading from the bus, the transputer is held using MemWait until the correct number of values have been read from the bus into the data latches; MemWait is then released to enable the transputer to read the value and continue.

The transputer has Reset and Analyse inputs which are required for processor initialisation, and provides an Error output to monitor for serious software errors. These three lines are known collectively as "System Services". The master board has an "Up" port, where Reset and Analyse are inputs and Error is an output, and a "Down" port where the reverse is true. "Up" connects to the previous tower (or the user interface), and "Down" connects to the next tower. Each port also provides a buffered Inmos link for communicating data.

The "Up" services directly control the transputer on the master board.

A memory-mapped services PAL enables the transputer to assert "Down" Reset and Analyse, and to monitor the "Down" Error signal.

The transputer receives its program directly from one of its links after Reset; no ROMs are required for bootstrapping.

The services PAL provides a number of other functions: it generates the BRESET bus signal from software, and it enables reading of a 4-bit ID word set by on-board links. This 4-bit number encodes the drive type installed in this tower, so the system software can determine the drive type(s) present in multi-tower systems.

At reset, communication from the "Down" link is disabled by this same PAL until explicitly enabled in software. This prevents spurious data being received on this link if it is unconnected, which would prevent the processor from booting, until the program is running.

Data connection The data link between user interface and towers is a high speed, point to-point serial link. Connections are made using 9 pin D connectors, with the following signals: differential transmit (+ and differential receive (+ and -); reset; analyse; error; data ground; frame ground.

Buffered asynchronous Inmos links are used for data transfer, at 10 or 20 megabits per second. (See "The Transputer Databook" (Inmos, 3rd edition 1992) pp22-24 for a description of Inmos links). Differential buffers ensure high noise immunity at these high data rates, and enable cable lengths of 5m or more to be used if required.

The Reset and Analyse signals required by the transputer on the master board are transmitted using 9V Ras232 levels to ensure that induced noise does not result in spurious system resets. The Error signal, which is polled, is transmitted in the opposite direction using 5V levels.

On the master board, the "Up" and Down connectors are of opposite gender to prevent incorrect connection.

The link adaptor card, which is installed in the user interface, has a "Down" connector only. A block diagram of this card is shown in fig 6.

An Inmos C012 link adaptor provides the transmission and reception of serial data, whilst a PAL allows software control of the system services, and decodes the card into I/O address space. The card may also be driven by the DMA controller within the PC.

System software The system software is held on the fixed disk on the user interface.

The master board software is booted over the serial link, followed by software for the drive boards.

Software running on the user interface itself allows the user to read a master disk and create an image on the fixed disk, to create bulk copies from one of these images, or to perform diagnostic operations.

These operations are performed by communicating requests to the master board(s), and processing reply messages. A log file is kept which records the number of copies made of each master image, the number of disks copied in each drive, and the number of failures suffered by each drive. These statistics can be used to spot drives which may need servicing or realignment.

Write Splice Patching When data is written to a formatted disc, noise is created at the points where the head write current is turned on and off. When reading the disk, this noise causes phase locked loops to jump out of lock (a synchronisation pattern follows the splice point to bring them back into lock). A more important problem for a disk copier is that the data read back during this time may be such that it could not be copied onto another disk.

For example, let us represent a flux transition by a '1 and an absence of a flux transition by a '0'. When using the MFM encoding system, each '1' is separated by one, two or three '0's (X.e. 101, 1001, 10001). When reading over a write splice point, invalid sequences may be read (e.g. 11 or 100001). The pattern 11 has flux transitions too close, and cannot be recorded on the media. If there is too large a gap between flux transitions, such as with 100001, there are no pulses to keep the phase locked loop in lock when reading the data back.

The solution is to apply an algorithm to the data stream which leaves valid data alone, but which patches the noise at write splice points so that it can be written and verified successfully. Various algorithms could be used; the one which is used is as follows. The data is processed in a bitwise fashion, where is a pointer to the current bit. The bits at and following the current position are checked to see which of the templates below they match, and the data and pointer position are updated as shown.

11 -- > 10 (fix '1's too close) 101 -- > 101 1001 -- > 1001 A 10001 -- > 10001 A 10000 -- > 10100 (fix '1's too far apart) Note that the pointer is always left pointing to a '1', so there is no need to consider cases where it points to a '0' (except at the very start of the track). Long sequences of '1's or '0's are both converted to '101010...

The arrangement of the above embodiment uses a fast version of this algorithm to process data 8 bits at a time, using a lookup table. The table is indexed by the current 8 bits and the previous and following 2 bits, and gives the replacement value for the current 8 bits. Except where write splice noise is present, this will be the same as the current 8 bits of course.

Once the data which has been read off the track has been processed in this way, two important advantages are achieved: (1) When making a copy of the track, the entire track can be written and verified bitwise. No verify errors will occur at the write splice points, and no knowledge is required of the encoding system(s) or sector organisation in use. All that is required is to know the position and pattern of the first address mark present, to synchronise the start of the verify pass.

(2) There will be no write splice noise present in the copy, so the phase locked loops in the system which is reading the copy will stay fully locked while the whole track is being read. This means that the copy may be more reliable in use than the original master disk.

Claims (6)

1. A disk copying apparatus having a master control circuit ana respective disk drive control circuit for each of a number of disk drives arranged to receive and write on respective target disks onto which the data or program material is to be copied, n which the master circuit includes master memory means of adequate capacity to store the entire material to be copied, and each drive control circuit includes respective drive memory means to store portion of the material to be copied, in which each drive control circuit is arranged to cause its disk drive to write such portion of material to a disk there in autonomously, and in which the master circuit is arranged to poll each drive control circuit successively and supply a further portion of material to any drive control circuit which has completed the writing of a previously supplied portion of material.

2. A disk copying apparatus as claimed in Claim 1, in which such portions of material comprise streams of bits of data or program information which are of a chosen length, such length being independent of any track capacity upon the target disks.

3. A disk copying apparatus as claimed in Claim ; or 2, to be sued in association with a microprocessor based computer including a suitable disk drive by which the material to be copied may be loaded from a master disk bearing the material, into the master memory means.

4. A disk copying apparatus as claimed in Claim 3, in which such computer includes a fixed storage disk system onto which such material may be copied and stored before being written to the master memory means.

5. A disk copying apparatus as claimed in any preceding claim, in which said master circuit includes a master microprocessor arranged to control the function of the master circuit.

6. A disk copying apparatus as claimed in any preceding claim in which the disk drive control circuits each include a respective drive microprocessor arranged to control the operation of the disk drive control circuit.