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GB2273801A - Data validity - Google Patents

Data validity Download PDF

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Publication number
GB2273801A
GB2273801A GB9226944A GB9226944A GB2273801A GB 2273801 A GB2273801 A GB 2273801A GB 9226944 A GB9226944 A GB 9226944A GB 9226944 A GB9226944 A GB 9226944A GB 2273801 A GB2273801 A GB 2273801A
Authority
GB
United Kingdom
Prior art keywords
data
disk
processor
file
master records
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
GB9226944A
Other versions
GB2273801B (en
GB9226944D0 (en
Inventor
Frederick Finlay
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
I P TECHN Ltd
Original Assignee
I P TECHN Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by I P TECHN Ltd filed Critical I P TECHN Ltd
Priority to GB9226944A priority Critical patent/GB2273801B/en
Priority to BE9300014A priority patent/BE1005227A6/en
Publication of GB9226944D0 publication Critical patent/GB9226944D0/en
Publication of GB2273801A publication Critical patent/GB2273801A/en
Application granted granted Critical
Publication of GB2273801B publication Critical patent/GB2273801B/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/22Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2205Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
    • G06F11/2221Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test input/output devices or peripheral units
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/14Error detection or correction of the data by redundancy in operation
    • G06F11/1402Saving, restoring, recovering or retrying
    • G06F11/1471Saving, restoring, recovering or retrying involving logging of persistent data for recovery

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  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Debugging And Monitoring (AREA)
  • Information Retrieval, Db Structures And Fs Structures Therefor (AREA)

Abstract

An array of disk drives 11 - 15 are connected via multi-ported disk controllers to a processor. The processor being arranged to carry out on-line transaction processing 20 in communication with a plurality of master records 27 and a user interface 26. Online transaction data is automatically stored in history, back-up and report generation files 29,30,31. A batch process 21, carried out at certain time intervals, monitors 32 and collates data 33 in the master records, generates monitor reports 34 and stores the collated data in a general file 42. A test process 22 is carried out to ensure data validity by comparing parameter values 40 determined from the contents of the master records with the data stored in the general file 42. The results are recorded in a balancing file 43. Test data may be fed back 23 for processing data in an audit trail file 44. <IMAGE>

Description

wA Data Processing APParatus with Data Validation" The invention relates to a data processing apparatus which has the following technical objectives: (a) The carrying out of online transaction processing in communication with user interfaces in an efficient manner so that there are fast response times, and (b) To activate various processes so that there is little cross-disruption of processing and to ensure that data is validated in a comprehensive manner.
European patent specification No. EP-Bl-OO10190 describes a data processing apparatus with memory access protection.
It is in particular addressed to serialising the various tasks being performed by the system so that one task which seeks conflicting access to an object will be forced to wait until the processor is finished operating on the object in question. This is indeed one of the reasons why data corruption may occur where a processing unit carries out a number of processes in communication with the same data storage devices. In this specification, access restrictions are used for the execution of instructions.
The present invention is directed towards achieving both of the above-mentioned objectives (a) and (b) by the carrying out and sequencing of processes within the constraints of the available processing capacity.
According to the invention, there is provided a data processing apparatus comprising: a processing unit comprising a processor having a plurality of intelligent interfacing channels, and a random access memory circuit; a user interface connected to a channel; a plurality of disk controllers connected to the interfacing channels of the processor; and a plurality of disk drives connected to the disk controllers, wherein, the disk controllers are multi-ported and are each connected to at least two interfacing channels; at least one disk controller is connected to a plurality of disk drives; at least one disk drive is sequentially connected to at least one additional disk drive in an hierarchial manner; the processor is constructed to carry out on-line transaction data processing in communication with a plurality of transaction master records stored on a disk and with the user interface;the processor comprises means for automatically communicating with different disk drives via the controllers and the hierarchial links to record online transaction data in stored history, backup and report generation files; the processing unit includes a real time clock and clock monitoring means for initiating a batch process of the processor at periodic intervals, the batch process monitoring data of the master records, collating monitored data, automatically generating monitor reports, and recording the collated data in a general file on a disk; and the processor comprises test means for accessing disks storing the master records and the general file, means for determining parameter values from the master records and for testing data validity on receiving data from the general file and the determined parameter values, and recording resulting balancing data in a balancing file on a disk.
In one embodiment, the test means automatically writes test data to an audit trail file and the processing unit further comprises a feedback means for processing data in the audit trail file and feeding it back as in input to the test means.
Preferably, the feedback means also feeds back data to the balancing file.
In another embodiment, the processor comprises means for carrying out additional transaction processing in communication with the master records, and for automatically recording the batch transaction data in the history, back-up and report generation files.
The invention will be more clearly understood from the following description of some preferred embodiments thereof, given by way of example only with reference to the accompanying drawings in which: Fig. 1 is a diagram showing a data processing apparatus of the invention; Fig. 2 is a diagram showing a manner in which the apparatus operates.
Referring to Fig. 1, the apparatus 1 comprises a processor 2 having ports and addresses and data buses 3 communicating with various interfacing devices including workstation controllers which are in turn connected to user workstations, to printers, to cartridge controllers and to a communications controller. The communications controller allows communication with a large number of user interfaces spread over a wide geographical area.
This allows the apparatus 1 to be used, for example, by a financial institution having a large number of branches.
The processor 2 is connected to a random access memory 4 of 128 MB capacity. There are a total of 32 intelligent interfacing channels in the processor 2 and eight of these are shown and indicated by the reference numeral 5. These are the channels which the processor 2 uses for interfacing with disk controllers 7 via bi-directional links 6. The channels 5 are constructed so that they may be signalled during a process to access data and may perform the access operations intelligently while allowing the process or continue its other operations. The channel 5 may then generate a signal when the access is complete so that the data may be used for the process. This helps to ensure efficiency of the processes because data access times are considerably longer than processing operations of micro-processors in the processor 2.
An important aspect of the apparatus 1 is that each disk controller 7, 8 and 9 is multi-ported. This allows it to be connected to at least two of the channels 5. The input ports are . identified by the letters A and B, as appropriate. The output ports are identified by P0, P1, P2, and P3, as shown in the diagram. Another important aspect of the invention is the fact that at least one of the controllers 7, 8 and 9 is connected via bi-directional links with at least two disk drives, 11, 12 and 13.
Indeed, in the embodiment shown each of the disk controllers is connected to at least two disk drives. It is also important that one of the disk drives is connected in an hierarchial manner to additional disk drives and in this case the disk drive 13 is connected to a pair of disk drives 14 and 15 by a total of four links. The capacities of the disks are, 11 - 20GB, 12 - 12GB, 13 - 12GB, 14 - 15GB, and 15 - 15GB. There is thus a total of 72GB in storage capacity.
In this embodiment, the processing unit comprises the processor 2 incorporating the channels 5, the various interfacing devices 3 and the random access memory 4. The processor 2 comprises a number of microprocessors which are programmed for the carrying out of various processes, described below.
Alternatively, the processing unit may comprise a set of dedicated processors each for the carrying out of a particular process only and being hard-wired and hardcoded for that purpose. The manner in which the processors operate is not important to the invention, what is important is the set of technical steps which are carried out to ensure both fast response times and thorough data validation. This, we believe, is achieved by the configuration of the apparatus illustrated in Fig.
1 in conjunction with the following processes which are carried out by the processing unit.
Referring specifically to Fig. 2, the set of disk drives 11 to 15 are shown diagrammatically as comprising a number of records and files, all of which are identified and described below. A number of primary processes are illustrated including an online transaction process 20, a batch process 21, a test process 22, and a feedback process 23. An important aspect of the invention is the manner in which each of these processes operates and the sequencing of the processes themselves.
In the online transaction process 20 in step 25 the processor 2 communicates via the devices 3 with user interfaces, either local or remote in an interactive manner as indicated by the step 26. The online transaction processing step 25 involves accessing one of a very large number of master records 27 and one of the disks 11 to 15. This involves fetch cycles to the disk being directed by a channel 5 while processing is carried out within a microprocessor of the processor 2. The nature of the transaction processing is not important.
Data may be inputted, or instructions may be inputted for the processing of data which is stored, and at the end of a particular process, data is updated in a master record 27. The processor 2 is programmed to automatically record the amended transaction in a history file 29, a back-up file 30 and a report generation file 31. This is indicated by the step 28 and is carried out by use of a plurality of channels 5 communicating with a plurality of disks. In this respect, the hierarchial linkage of the disks 13, 14 and 15 is very important as it allows fast operation of the channel 5, particularly in recording of amended transaction data in the files 29, 30 and 31. For example, these files may be stored on the disks 13, 14 and 15 respectively.The online process 20 takes place in an on-going basis and in practice would be carried out during working hours for an organisation such as a financial institution By reference to a real time clock (not shown), the processor 2 is automatically activated to carry out the batch process 21. In practice this may be during nighttime. The batch process 21 comprises a pair of subprocesses carried out in parallel. One sub-process involves accessing the master records 27 to carry out batch transaction processing and updating and subsequentially recording the amended transaction data in step 31 in the history file 29, the back-up file 30 and the report generation file 31. This processing is not totally dissimilar to the online transaction processing.
The differences are that it is carried out in a batch process at a particular time and the nature of the transaction processing which is carried out is not interactive. The second sub-process involves in step 32 the processor accessing the master records 27 to monitor the contents of the records and subsequently in step 33, collating the monitored data. The collated monitored data is recorded in a general file 42 and is also used for the generation of monitor reports in step 34. The step 32 involves sequentially accessing each record in turn to determine flagged changes which may be collated in the step 33.
Also at periodic intervals as determined with reference to a real-time clock, the test process 22 is carried out. In step 40 of this process, the processor 2 again accesses the master records 27 and carries out various calculations to determine values for a pre-set group of parameters. In step 41 the processor retrieves both the determined parameter values and data from the general file 42 and carries out balancing operations to test the data for consistency. The output of the step 41 is automatically recorded in a balancing file 43 and in an audit trail file 44.
An important aspect of the invention is the fact that the processor 2 carries out a feedback process 23 which uses the contents of the audit trail file 44 in order to feed back instructions to the test process 22 and in particular at the step 41. This allows the test process to be carried out more intelligently and efficiently.
It will be appreciated that by sequencing the online transaction, batch, test and feedback processes as described above, there is little chance of conflicting data access requirements occurring. It will also be appreciated that maximum utilisation is made of the processor 2, and further because of the manner in which the batch process and the test processes are carried out, data validation is ensured.
The invention is not limited to the embodiments hereinbefore described, but may be varied in construction and detail.

Claims (5)

1. A data processing apparatus comprising: a processing unit comprising a processor having a plurality of intelligent interfacing channels, and a random access memory circuit; a user interface connected to a channel; a plurality of disk controllers connected to the interfacing channels of the processor; and a plurality of disk drives connected to the disk controllers, wherein, the disk controllers are multi-ported and are each connected to at least two interfacing channels; at least one disk controller is connected to a plurality of disk drives; at least one disk drive is sequentially connected to at least one additional disk drive in an hierarchial manner; the processor is constructed to carry out on-line transaction data processing in communication with a plurality of transaction master records stored on a disk and with the user interface; the processor comprises means for automatically communicating with different disk drives via the controllers and the hierarchial links to record online transaction data in stored history, back up and report generation files;; the processing unit includes a real time clock and clock monitoring means for initiating a batch process of the processor at periodic intervals, the batch process monitoring data of the master records, collating monitored data, automatically generating monitor reports, and recording the collated data in a general file on a disk; and the processor comprises test means for accessing disks storing the master records and the general file, means for determining parameter values from the master records and for testing data validity on receiving data from the general file and the determined parameter values, and recording resulting balancing data in a balancing file on a disk.
2. An apparatus as claimed in claim 1, wherein the test means automatically writes test data to an audit trail file and the processing unit further comprises a feedback means for processing data in the audit trail file and feeding it back as in input to the test means.
3. An apparatus as claimed in claims 1 or 2, wherein the feedback means also feeds back data to the balancing file.
4. An apparatus as claimed in any of claims 1 to 3, wherein the processor comprises means for carrying out additional transaction processing in communication with the master records, and for automatically recording the batch transaction data in the history, back-up and report generation files.
5. An apparatus substantially as hereinbefore described, with reference to and as illustrated in the accompanying drawings.
GB9226944A 1992-12-24 1992-12-24 A data processing apparatus with data validation Expired - Fee Related GB2273801B (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
GB9226944A GB2273801B (en) 1992-12-24 1992-12-24 A data processing apparatus with data validation
BE9300014A BE1005227A6 (en) 1992-12-24 1993-01-07 Device with data processing data validation.

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB9226944A GB2273801B (en) 1992-12-24 1992-12-24 A data processing apparatus with data validation
BE9300014A BE1005227A6 (en) 1992-12-24 1993-01-07 Device with data processing data validation.

Publications (3)

Publication Number Publication Date
GB9226944D0 GB9226944D0 (en) 1993-02-17
GB2273801A true GB2273801A (en) 1994-06-29
GB2273801B GB2273801B (en) 1996-08-21

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Family Applications (1)

Application Number Title Priority Date Filing Date
GB9226944A Expired - Fee Related GB2273801B (en) 1992-12-24 1992-12-24 A data processing apparatus with data validation

Country Status (2)

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BE (1) BE1005227A6 (en)
GB (1) GB2273801B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6850953B1 (en) * 1999-08-23 2005-02-01 Sun Microsystems, Inc. Creating multiple sets of data by spawning a secondary virtual machine

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6850953B1 (en) * 1999-08-23 2005-02-01 Sun Microsystems, Inc. Creating multiple sets of data by spawning a secondary virtual machine

Also Published As

Publication number Publication date
GB2273801B (en) 1996-08-21
GB9226944D0 (en) 1993-02-17
BE1005227A6 (en) 1993-06-01

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PCNP Patent ceased through non-payment of renewal fee

Effective date: 20041224