GB2268014A - A differential amplifier using a diamond differential stage - Google Patents

Abstract

A differential amplifier has an input differential pair and following diamond differential and complementary differential amplifying stages, allowing truly symmetrical feedback paths to the emitters of the input differential pair, giving low distortion, a high CMRR and high slew rate. Use as a preamplifier, a transformer coupled output amplifier and a differential summing amplifier is described (Figures 1, 2, 3 respectively). <IMAGE>

Description

AN AMPLIFIER The present invention relates to a differential amplifier.

Differential amplifiers using a pair of transistors (bipolar or field effect) as input devices, biased with current sources in their emitter or source paths, the differential signals from the collectors or drains feeding the inputs of an operational amplifier are widely used in applications requiring good linearity, input Common Mode Rejection Ratio, and low noise over a wide gain range. Feedback is provided to the emitters or sources of the input devices, the gain being set by a resistor, variable or fixed, connected between these points. The feedback to one emitter or source is taken from the output of the operational amplifier, and the feedback to the other from either a ground reference point or a complementary signal derived by passing the output of the operational amplifier through an additional inverting amplifier.

However such circuits suffer from problems associated with the asymmetry of the feedback path, and/or the phase margin and siew rate of the operational amplifier and additional inverting amplifier, giving rise to significant distortion at high gain settings, high frequency instability, and poor rejection of high frequency interfering signals due to reduced high frequency Common Mode Rejection and low slew rate.

The present invention seeks to provide an amplifier circuit which, by having symmetrical feedback paths and a high slew rate offers improved performance over a wide gain and frequency range and is equally applicable to preamplifier, line amplifier and power amplifier stages.

According to the present invention there is provided an amplifier circuit comprising a first amplifying stage having two transistors connected as a differential pair, the bases or emitters of the said differential pair being arranged to receive input signals to said amplifying stage, said differential pair being biased by each of their emitters being connected to additional transistors connected as current sources, and the collectors of said transistors being coupled to a second amplifying stage through a biasing network, the second amplifying stage having two pairs of transistors connected as a diamond differential, the collectors of said four transistors being connected to a third amplifying stage having a complementary differential pairs of transistors, the collectors of corresponding comprementary devices therein connected to form the two outputs of the amplifier circuit, feedback paths being provided from said outputs to the emitters of the said first stage differential pair, and a resistor fixed or variable, for varying the gain of the amplifier circuit connected between the emitters of the said first stage differential pair, wherein the feedback paths include feedback resistors.

In an embodiment, a respective additional transistor is connected in cascode with each of said first stage differential pair transistors.

In an embodiment, additional transistors configured as complementary emitter followers are connected through a suitable biasing network to the said outputs, wherein the output and feedback signals are taken from the emitters of said emitter followers.

In an embodiment, a transformer couples the feedback signals from said outputs of the amplifier to the respective feedback resistors, one or more additional windings giving additional isolated outputs.

In an embodiment, the input signals may be presented through resistors to the emitters of said first stage differential pair transistors, the bases of said transistors being connected to a reference voltage.

In an embodiment said additional transistors connected as current sources biasing the said first stage differential pair may be replaced by resistors returned to the power supply rail.

In an embodiment a servo amplifier comparing the common mode output voltage at said outputs with a reference voltage applies an offset voltage to the bases of the transistors said third amplifying stage so as to force the common mode output voltage to the reference voltage.

In an embodiment any or all of said pairs of transistors may be field effect transistors, aforementioned base connections being made to the gate, emitter connections to the source and collector connections to the drain.

Specific embodiments of the present invention will now be described, by way of example, with reference to the accompanying drawing in which: Figure 1 shows a circuit diagram of an embodiment of an amplifier of the invention, that is designed to be a preamplifier amplifying low level AC signals, the output driving a medium to high impedance load.

Figure 2 shows a circuit diagram of an embodiment of an amplifier of the invention, that is designed to be a transformer coupled output amplifier.

Figure 3 shows a circuit diagram of an embodiment of an wTplifie of the invention, that is designed to be a differential summing amplifier.

Referring to Figure 1, the preamplifier circuit has differential inputs and outputs. The first amplifying stage comprises two NPN transistors Q1 and Q2 connected as a differential pair. The input signals are coupled to the bases of the transistors Q1, Q2 by way of respective capacitors Cl and C2, the bases being biased by resistors RB. Field effect transistors 23, Q4 are connected as self biasing cascodes with transistors Q1, Q2 to reduce nonlinearity due to The Early effect and Miller capacitance. Respective collector resistor RC connects the drain of each field effect transistor to the positive supply V+ through respective matched biasing networks VREF.The bases of second stage transistors Q5, Q6, Q7, Q8 are connected across biasing networks VREF, VREF so as to maintain a small DC bias voltage across emitter resistors RD. The quiescent current of Q5, Q6, Q7, Q8 is determined by: Iq = (VREF-2Vbe)/2RD For a small voltage difference VSIG between the drains of Q3 and Q4, VSIG < (VREF-Vbe), transistors Q5, Q6, Q7, Q8 are all conducting: the current in Q5 and Q8 is given by: IQ5 = IQ8 = Iq + VSIG/2RD And the current in Q6 and Q7 is given by: IQ6 = IQ7 = Iq - VSIG/2RD Thus the output signal currents IQ5 = IQ8 and IQ6 = IQ7 are equal and opposite, giving equal and antiphase output voltages at points OUTPUT + and OUTPUT -, when further amplified by symmetrical third stages Q9 and Q10, Q11 and Q12. For excursions of VSIG greater than (VREF -2Vbe) one of the diagonal pairs Q5 and Q8, Q6 and Q7 will be cut off, whereas the other pair will be conducting a current given by: I = (VSIG + VREF - 2VBE)/2RD The maximum value of this current is limited only by the available voltage swing at the drains of Q3 and Q4, and the input impedance of the third amplifying stage: with typical component values it can be 10 times greater than Iq, and since this increased current is further amplified by the third stage it gives a useful increase in slew rate for large rapidly changing input signals.

Resistors R1 and R2 being of substantially identical value sum the common mode output voltage whilst cancelling any differential signal voltage, the resultant being applied to the non inverting input of operational amplifier Al, which is connected with C3 and R1 as a non inverting offset servo amplifier. The output of Al feeds four resistors RS which are in turn connected to the bases of transistors comprising the third amplifying stage QD, QlO, Q11, Q12: this forms a negative feedback loop around the third stage forcing the common mode output voltage to ground, at a rate determined by the time constant of C3 and R1.

The operating point of the differential pair Q1, Q2 is determined by bias resistors RE, which for small common mode input voltage swings provide a relatively constant total current through Q1, Q2. The gain of the amplifier circuit is set by the feedback resistors RF and a gain resistor RG connected between the emitters of the transistors Q1,Q2 in parallel with the sum value of the bias resistors RE. Each of the three stages of the amplifier is inherently linear and symmetrical, and the total open loop gain is large. These factors provide high linearity over a gain range of typically 3 to 60dB and a high common mode rejection ratio.

Referring to Figure 2, the transformer coupled output amplifier has three amplifying stages substantially identical to those described in Figure 1. Additional complementary emitter followers Q13, Q14, Q15, Q16 biased by networks VREF2 connected to the collectors of third stage transistors Q9, QlO, Qil, Q12 provide additional current gain and increased maximum output current for driving low impedance loads, the primary of the transformer and servo amplifier input resistors R1, R2 being connected to the emitters of Q13, Q14, Q15, Q16. The output common mode voltage servo amplifier Al works as described before.

AC feedback is taken from a second feedback winding through resistors RF to the emitters of differential pair Q1, Q2.

Resistors RF' provide feedback at frequencies below those that will pass through the transformer, giving DC stability and are typically much larger than RF giving sufficient gain margin around the transformer to substantially reduce any nonlinearities it may introduce due to properties of the core material.

Capacitors CF maintain negative feedback at frequencies higher than those that will pass through the transformer. The output signal of the amplifier is taken from a third winding. The operating point of the differential pair Q1, Q2 is determined by transistors Q17, Q18 which are connected to form current sources, and thereby have a high output impedance, which can be discounted when assessing the gain of the circuit. The use of current sources instead of emitter resistors enables the amplifier to operate down to gains close to unity even with 1:1:1 ratio transformers, and allows a larger common mode input voltage.

Referring to Figure 3, the differential input, differential output summing amplifier has three amplifying stages substantially identical to those described in Figure 1. The bases of the input differential pair Q1, Q2 are returned to ground potential, and the input signals are summed by pairs of substantially identical resistors RIN 1, RIN 2 through RIN N into the AC virtual ground thus created at the emitters of Q1 and Q2. The gain of the circuit to a particular input with input resistors RIN is given by the ratio RF/RIN.

The three circuits illustrated in Figures 1,2 and 3 include a number of resistors, diodes and capacitors which have not been specifically identified that set the bias conditions for the various transistors. Voltage references VREF, VREF2, VREF3 generate a substantially constant voltage across their two terminals whilst passing a wide range of current; they may be implemented by various means.

It will be appreciated that variations and modifications to the circuit particularly described may be made within the scope of the invention.

Claims (8)

1) An amplifier circuit comprising a first amplifying stage having two transistors connected as a differential pair, the bases or emitters of the said differential pair being arranged to receive input signals to said amplifying stage, said differential pair being biased by each of their emitters being connected to additional transistors connected as current sources, and the collectors of said transistors being coupled to a second amplifying stage through a biasing network, the second amplifying stage having four transistors connected as a diamond differential pair, the collectors of said four transistors being connected to a third amplifying stage having a complementary differential pairs of transistors, the collectors of corresponding complementary devices therein connected to form the two outputs of the amplifier circuit, feedback paths being provided from said outputs to the emitters of the said first stage differential pair, and a resistor fixed or variable, for varying the gain of the amplifier circuit connected between the emitters of the said first stage differential pair, wherein the feedback paths include feedback resistors.

2) An amplifier circuit as claimed in Claim 1, wherein a respective additional transistor is connected in cascode with each of said first stage differential pair transistors.

3) An amplifier circuit as claimed in Claim 1 or 2, wherein additional transistors configured as complementary emitter followers are connected through a suitable biasing network to the said outputs, wherein the output and feedback signals are taken from the emitters of said emitter followers.

4) An amplifier circuit as claimed in Claim 1, 2 or 3, wherein a transformer couples the feedback signals from said outputs of the amplifier to the respective feedback resistors, one or more additional windings on the transformer giving additional isolated outputs.

5) An amplifier circuit as claimed in Claim 1, 2, 3 or 4 wherein the input signals may be presented through resistors to the emitters of said first stage differential pair transistors, the bases of said transistors being connected to a reference voltage.

6) An amplifier circuit as claimed in Claim 1, 2, 3, 4 or 5 wherein said additional transistors connected as current sources biasing the said first stage differential pair may be replaced by resistors returned to the power supply rail.

7) An amplifier circuit as claimed in Claim 1, 2, 3, 4, 5 or 6 wherein a servo amplifier comparing the common mode output voltage at said outputs with a reference voltage applies a offset voltage to the bases of the devices in said third amplifying stage so as to force the common mode output voltage to the reference voltage.

8) An amplifier circuit as claimed in Claim 1, 2, 3, 4, 5, 6 or 7 wherein any or all of said pairs of transistors may be field effect transistors, aforementioned base connections being made to the gate, emitter connections to the source and collector connections to the drain.