GB2265055A - Battery charger - Google Patents

Description

2265055 z COMPACT LOW NOISE LOW POWER DUAL MODE BATTERY CHARGING CIRCUIT

CROSS-REFREENCE TO RELATED APPLICATION

This application is a continuation-in-part of commonly assigned copending allowed patent application Serial No. 621,014, filed November 30, 1990, and entitled f1COMPACT LOW NOISE LOW POWER DUAL MODE BATTERY CHARGING CIRCUIT", now Patent No. 5,111,131, issued May 5, 1992, by the present inventor. BACKGROUND OF THE INVENTIO

The invention relates to a system for charging batteries, particularly nickel cadmium batteries. The invention relates more particularly to very small, compact battery charger circuits suitable for charging batteries of communications products without introducing electrical noise that may interfere with 6peration thereof.

A fully charged state of a nickel cadmium battery is achieved by controlling the charging when the terminal voltage falls or "droops" by a certain amount (for example, 100 millivolts) from its peak value during high current charging. Nickel cadmium batteries are known which are able to withstand a relatively high charging rate. A high battery charging rate is desirable in order to reduce the charging time and therefore the amount of time a battery is out of service. ror a typical fast charge, a current that is numerically equal in amperes to the battery capacity in ampere hours is supplied to the battery for 1 2 approximately one hour. It is known that high current charging of a nickel cadmium battery should be stopped soon after the onset of a negative rate of change of the battery voltage. There are known battery chargers that automatically sense a fully charged condition of a battery and then terminate the main charging current produced by the charger and substitute a trickle current. As the battery reaches full charge, the charging rate is reduced to a trickle charge or stopped. it is important to control the cutoff of charging so as to assure that the battery has been fully charged, and also to prevent overcharging that may damage the battery cells.

It Is known that many communications products, such as portable cellular telephones, are highly sensitive to presence of electrical noise.. Prior battery chargers generally introduce a substantial amount of electrical noise onto conductors connected to the terminals of the battery being charged. Furthermore, radiated high frequency interference may be pi&ed up by rf amplifiers. If a communications product such as a portable cellular telephone is being used while its battery is being charged, such electrical noise is likely to deleteriously affect performance of the cellular telephone.

It would be highly desirable to provide a compact, low noise battery charger with low power dissipation that could be incorporated easily in a communications product or a power cord thereof to continually charge nickel cadmium batteries whenever the power cord is connected to a source of AC line current.

3 Prior battery chargers which are inexpensive enough for this purpose unfortunately require a long (e.g., twelve hours) charging time. More elaborate "fast" battery chargers are expensive, large, consume too much power, and/or generate too much electrical noise to be used simultaneously in most communication products. STJMMA,'RY OF THE INVENTION Accordingly, it is an object of the invention to provide a low cost, low noise, compact, highly efficient battery charging apparatus and method.

ide such a It is another object of the invention to prpV battery charging apparatus and method which provides very fast charging of a nickel cadmium battery without causing damage due to overcharging.

It is another object of the invention to provide a very compact battery charger capable of being incorporated in a power cord,and applying sufficiently low electrical noise across its output terminals or radiated from within to allow use of noisesensitive communications products and the like while rechargeable batteries thereof are being charged.

Briefly described, and in accordance with one embodiment thereof, the invention provides a battery charger that includes a first rectifier receiving a line voltage and producing a rectified sinusoidal voltage. A transformer has a primary winding coupled to receive the rectified sinusoidal voltage, and second secondary winding. A second rectifier is coupled between L+ the terminals of the first secondary winding and the terminals of a battery being charged. A switch is coupled between a terminal of the primary winding and a filter or other circuit that produces a signal indicative of current flowing through the primary winding. A first circuit produces a battery condition voltage that is proportional to the voltage present between the terminals of the battery being charged. A gecond circuit produces a timing signal in response to the rectified sinusaidal voltage. A third circuit is coupled to the output of a ratchet DAC to compare an output voltage of the ratchet DAC to a reference voltage proportional to the battery cgidition voltage. The ratchet DAC performs a.peak detect and hold function. The third circuit produces an incrementing signal that is synchronized with the timing signal to increment the ratchet DAC until its output voltage exceeds the reference voltage. A fourth circuit is coupled to the output of the ratchet DAC to produce a low charging mode signal when the battery condition falls a predetermined threshold voltage below the DAC output voltage after a peak of the battery condition voltage has been attained. A fifth circuit is coupled to receive the low charging mode signal and the signal indicative of current flowing through the primary winding in order to produce a control signal. The control signal is applied to the switch to control flow of current through the primary winding in accordance with the battery sense voltage. The control signal applied to the switch is.controlled to produce a very low duty cycle when the battery charger is in its low charging current mode. When the battery charger is in its high charging current mode, the on time of the switch is modulated continuously between the valleys and peaks of the rectified sinusoldal voltage in order to keep voltage across the switch from exceeding its breakdown voltage while obtaining R maximum charging current to the battery. This is accomplished by circuitry that produces constant turn off times for the switch and variable turn on times for the switch in response to the signal indicative of current in the primary winding. This technique also accomplishes zero voltage, zero current switching of the switch, minimizing switching noise and po;er dissipation in the switch. The constant turn off tine is set to one-half of the resonant frequency of the primary winding circuit to accomplish the zero voltage switching. The primary f lyback voltage therefore has a half sine waveform returning to zero before the switch is turned on for the next cycle. Power loss in the switch is minimized, and the noise generated by the flyback voltage waveform is concentrated at the relatively high resonant frequency, with less energy at higher multiples of the frequency than would be the case with nonsinusoidal waveforms. BRIEF DESCRIPTION OF THE DRAWINGS

Fig. 1 is a block diagram of the battery charger of the present invention.

- Fig. 2 is a logic diagram of part of the battery charger circuit of Fig. 1.

Fig. 3 is a detailed logic diagram of another part of the (:7 battery charger circuit of Fig. I.

Figs. 4 is a timing diagram useful in describing the operation of the circuit of Figs. 1-3.

Fig. 5 is a block diagram of an alternate embodiment of the battery charger.

Fig. 6 is a logic diagram of a AV detector and a LED driver circuit in Fig. s.

Fig. 7 is a more detailed block diagram of a modulation and control circuit in Fig. 5.

Fig. 8 is a timing diagram useful in describing the embodiment of the invention shown in Figs. 5-7., Fig. 9 is a block diagram of another embodiment of the battery charger- Fig. 10 is a block diagram disclosing part of the circuitry in block 15B of Fig. 9.

Fig. 11 is a block diagram of part of the circuitry contained in block 5B of Fig. 9. DF,TAILED 6ESCRIPTION OF THE PRUERRED EMBODIMENTS 1 Referring to Fig. 1, battery charger circuit 1 receives AC line voltage 2 and rectifies it by means of a conventional fullwave rectifier 3 to produce the rectified HVDC (High Voltage DC) signal on its output conductor 4. Rectifier 3 has a ground terminal connected to -a main ground conductor 25. Conductor 4 supplies HVDC to an input of a AV detector/control logic circuit 5 and also to one terminal of an inductance 6. Inductance 6 may be a discrete inductor, or it may be the leakage inductance of -7 QI the primary winding 7A of a transformer 7.

Transformer 7 has a secondary winding 7B the terminals of which are connected to a half-wave rectifier 10. Rectifier 10 has a ground terminal connected to an "isolated" ground conductor 25A, and an output terminal IOA connected to the positive terminal of a nickel cadmium battery 11 to be charged.

Detector/control circuit 5 receives on conductor 14 a voltage V that accurately represents the present voltage of battery 11, and causes the charing rate of battery 11 to be decreased from a high current charging rate to a low current charging rate or trickle charge mode when a V SENS, voltage reduction or "droop" AV of the peak value 97 (Fig. 4) is detected. A signal RESET produced on conductor 8 by "on time" modulator circuit 15 is applied to an input of detector/ control circuit 5, which produces an EN signal on conductor 12 and an ILO ('low current charging mode) signal on conductor 13. conductors 12 and 13 are applied to control inputs of modulator circuit 15. A voltage VIsEmsE produced on conductor 21 by filter circuit 20 is applied to a feedback input of modulator circuit 15.

Modulator circuit 15 produces an output signal on conductor 16 that controls the "on timell of a switch 19 so as to determine the charging rate of battery 11. S witch 19, when closed, conducts current flowing through primary winding 7A through conductor 17 into an input of filter circuit 20 and into resistor 26. A capacitor 18 having capacitance C. is connected between conductor 17 and HVDC conductor 4.

9 Transformer 7 has a ferrite core 7D which magnetically coupls an additional secondary winding 7C to primary winding 7A. One terminal of secondary winding 7C is connected to main ground conductor 25, and the other terminal of inductor ?c is connected to an input of a half-wave rectifier 28. Rectifier 28 produces the voltage VSENSE on conductor 14.

Fig. 2 shows the details of detector/control circuit 5. The signal HVDC on conductor 4 is applied via a resistive voltage divider 35,36 and a capacitor 37 to the inverting input of an operational amplifier 38, the output of which produces a timing signal SYNC on conductor 23. The noninverting.nput of operational amplifier 38 is connected to ground conductor 25. Conductor 23 is connected through an inverter 24 to the input of one end of a shift register 42. Shift register 42 is comprised of six D type flip-flops. The Q output of the right hand flipflop is connected to one input of a NOR gate 43 and to an input of a.divider circuit 44 that divides that Q output signal by 2 15 The output of the right hand flip-flop of shift register 42 is connected to one input of a two input NOR gate 45 which produces a signal SYNCIII and applies it to the input of an OR gate 46. The Q output of the adjacent flip-flop of shift register 4.2 is connected to the other input of NOR gate 43 and to the other input of NOR gate 45. The output of OR gate 46 produces the signal BN on conductor 12.

The battery condition signal VsEmsE on conductor 14 is applied to tle collector of NPN transistor 34, to one terminal of Ct resistor 32. and to one terminal of resistor 47A. The other terminal of resistor 32 is connected to one tertinal of resistor 35 and to the cathode of a zener diode 33. The cathode of zener diode 33 also is connected to the base of NPN transistor 34. The anode of zener diode 33 is connected to the main ground conductor 25. The emitter of transistor 34 produces a constant reference voltage V,,,, equal to the breakdown voltage of zener diode 33 minus the V,,, voltage of transistor 34 on conductor 22. Thus, current, and hence operating power supplied to VREF conductor 22 comes from V SENSE conductor 14 through the collector and emitter of transistor 34. V conductor 22 supplies curre.p'c, and hence REF 1 operating power, to DAC 50. Also, V SENSE conductor 14 supplies operating power to the circuitry including resistor 36 and capacitor 37. VPtEF conductor 22 is connected to the reference input of digital-to-analog (DAC) converter 50. Digital-to-analog converter 50 can be a Model DAC 7541 marketed by the assignee, although only 7 of the 12 bits are used.

VREF conductor 22 also is connected to the inverting input of a comparator 60. The non-inverting input of comparator 60 is connected via conductor 44 to the non-inverting input of a comparator 51, the inverting input of comparator 52, and to the junction between resistor 47A and a resistor 47B. The other terminal of resistor 47B is connected to main ground conductor 25.

The output of DAC 50 produces a voltage V. on conductor 57, which is connected to the inverting input of comparator 51 and the non-inverting input of coinparator 52. Comparator 52 has a 100 inillivolt input offset voltage.

The seven inputs of digital-to-analog converter 50 are connected to the outputs of a seven bit ripple counter 55. Ripple counter 55 is reset by the signal RESET generated by the circuit of Fig. 3. Divide-by-215 circuit 44 also is reset by the signal RESET. Ripple counter 55 is incremented by a signal RCHT ("ratchet") on conductor 53A by AND gate 53. One input of AND gate 53 is connected to SYNC signal conductor 23. Another input of AND gate 53 receives the signal UP fram the output of comparator 51 to cause the output voltage V. of PAC 50 to "ratchet" higher. The remaining input of AND gate 53 receives the signal ILO on conductor 13N, which is connected to the U output of a D type flip-fldp 56. The signal ILO on conductor 13 also is applied to one input of OR gate 46. As subsequently will become apparent when the operation of the invention is described, QAC 50, ripple counter 55, AND gate 53 and comparator 51 co-act to produce a peak detect and hold function.

The clock input (CK) of flip-flop 56 is connected to SYNC conductor 23. The reset (R) input of flip-flop 56 is connected to RESET conductor S. The set (S) conductor of flip-flop.56 receives the signal TO (time-out) produced on conductor 48 by divider circuits 42 and 44. The Q output of flip-flop 56 produces the signal ILO (low current charging mode) on conductor 13. The D input of flip-flop 56 is connected to the output of an OR gate 54, one input of which receives the signal FULL It (indicating that battery 11 is fully charged) from the output of comparator 52. The other input of OR gate 54 receives the signal VHI (referring to a high voltage condition occurring because no battery is connected to charger circuit 1) produced at the output of comparator 60.

Referring next to Fig. 3, the details of on-time modulator circuit 15 and switch 19 are shown. The VRSF voltage on conductor 22 is applied via a resistive voltage divider 64B,75B to the noninverting input of error amplifier 63, the output of which is applied to the inverting input of comparator 66 and also to the inverting input of comparator 62. The noninver+,irig input of comparator 62 is connected to a ramp signal generator 64, which generates a 500 kilohertz ramp signal. Ramp generator circuit 64 is implemented by a circuit in which a constant current through resistor 64C flows charges up a capacitor 64D. One-shot 70 is ttiggered when the ramp voltage exceeds the output voltage of etror, amplifier 63. The one-shot resets the ramp to zero, and turns MOSFET 19 off. When one-shot 70 times out, it restarts ramp generator 64 by-turning off transistor 64E.

The "divided down" representation of V REF appearing on conductor 22A is epplied to the non-inverting input of errpr amplifier 63. The inverting input of error amplifier 63 is connected by resistor 76 to the ILO signal on conductor 13.

The output of comparator 62 is connected to the input of one microsecond one-shot circuit 70, the output of which is connected to one input of NOR gate 71. The other input of NOR gate 71 is 12- connected by conductor 12 to receive the signal The output Of NOR gate 71 produces the signal GATE and applies it to the gate electrode of X channel MOSPET 191 the drain of which is connected to a lower terminal of primary winding 7A and to the lower terminal of capacitor 18. The source of MOSPET 19 is connected by resistor 26 to ground conductor 25. The source of MOSFET 19 also is connected by resistor 20B to VISEN5a conductor 21 to the inverting input of operational amplifier 63. Resistor 20B and capacitor 20A constitute filter 20 of Fig. 1.

VsEmsE conductor 14 is connected to the D input of D type flip-flop 80. The clock input of flip-flop 80 connected to the output of comparator 66. The Q output of flip-flop 80 is connected by RESET conductor 8 to one terminal of resistor 94. The other terminal of resistor 94 is connected to the reset input of flip-flop 80 and to one terminal of capacitor 95, the other terminal of which is connected to main ground conductor 25.

A RESET pulse is generated by either a power turn on condition or a battery load condition. During power turn on, the soft start capacitor 20A initially causes the output of error amplifier 63 to be low. resulting in an initial Taininum on time for switch 19 and a clock edge to flip-flop 80 from coiaparator 66. Resistor 94 and capacitor 95 determine the width of the RESET pulse.

During a battery load condition, VIS'ENSE rises, causing the output of operational amplifier 63 to fall below the divided down reference voltage V,,,,, lge to initiate the causing a clock ed 1 _) 1 RESET pulse as described for a power turn on condition.

The basic operation of battery charger 1 is that the 60 hertz, 120 volt AC line voltage is rectified by full wave rectifier 3 to produce the sinusoidal HVDC waveform shown in Fig. 4. This waveform is input to the differentiating circuit 40 (Fig. 2) to produce the SYNC signal shown in Fig. 4. The leading edge of each SYNC pulse occurs at a maximum value of HVDC, i.e., at the middle of each rectified half wave. The trailing edge of each SYNC pulse occurs at a -minimum value of HVDC.

The SYNC signal is applied to the input of AND gate 53 and D type flipflop 56 (Fig. 2). The seven bit rippl,,ecounter 55 is resent by the signal RESET. If battery charger 1 is in its high current inade, ILO is a "I" enabling SYNC to produce the RCHT signal on conductor 53A, causing stepwise incrementing of VO as indicated by numeral 84 in Fig. 4. When V. exceeds V SENSE-D on conductor 44, comparator 51 causes the signal UP to go to zeo, disabling SYNC from producing the RCHT signal. When ILO goes to a '1011 as a result of a FULL--11111 signal being applied by comparator 52 to an input of NOR gate 54, the SYNC signal is disabled, so ripple counter 55 is no longer incremented, and the analog signal V, produced_by DAC 50 stops at level 83 in Fig. 4.

In accordance with the present invention, ratchet DAC 50 accurately holds level 83 until it is reset. Thus, RCHT is produced only while DAC 50 is being incremented, and flip-flop 56 then indicates either that the battery is fully charged or the battery is not connected. In either case, the Q output of flip- 1 _ flop 56 forces the circuit into a low charging current mode.

If charger circuit 1 is not connected to battery 11, the voltage V,,,,, obviously will increase to a high value, as the output current of battery charger 1 has nowhere to flow. Comparator 60 detects this condition and sets the signal VHI (voltage high) to a "111, forcing flip-flop 56 to establish a low current or trickle current charging mode. (The reason that it is desirable for battery charger circuit 1 to go into the low current mode if no battery is connected to the charger is because it is desirable to avoid wasteful power dissipation in the transformer.) The FULL signal goes to a 11111 to indicate that the battery has been fully charged when the voltage VSEWSE-D has "drooped" or fallen more than approximately 100 millivolts, as indicated by numeral 85 in Fig. 4, at which point V. exceeds V SE9SE-D by more than the 100 millivolt offset of comparator 52.

The inverting input of comparator 60 receives the VREF voltage on conductor 22, which is compared to VSEMSP-D. A high value of vseusE produced by winding 7C and rectifier 28 under a "no load" condition on conductor 10A results in VH1 going from a 11011 to a 11119, setting flip-flop 56, and initiating low current inode operation.

The voltage VSENSE produced by rectifier 28 (Fig. 1) has two functions, one being to accurately represent the battery voltage if a battery is connected, and the other being to supply power to the detector, controller, and modulator circuits.

1 is- Shift register 42 performs a divide-by-ii function. Divideby-11 shift 'register 42 and a separate divide-by-215 circuit 44 generate a tine out (TO) signal on conductor 48 that performs a "fail safe" function of setting the battery charger to a low current charging mode after one hour of high current charging operation. The divide circuits 42 and 44 divide the 60 hertz line frequency down enough to produce the signal To after one hour. Shift register 42 and NOR gate 43 are configured as a socalled "walking ring" counter which performs the divide-by-11 function needed in conjunction with the divide-by-215 function to obtain the one hour delay by division of the 6o,hertz line frequency.

Divide-by-11 shift register 42 performs a second function, which is to implement the low current mode op,_ration by producing an.enable pulse on conductor 12 every eleventh SYNC pulse. The FN_ signal on conductor 12 is gated by the ILO signal on conductor 13N.1 The rising edge 88 (Fig. 4) of ILO results in a corresponding falling edge of ILO that gates the SYNC111 signal through OR gate 46 to produce ER. The SYNC/11 signal is a 11011 every eleventh SYNC pulse, and is a 11111 the rest of the time. The 'tN signal therefore has a 11011 value indicated by nume.ral 90 in Fig. 4 during the SYNCIII pulse if ILO is positive. The output of one-shot circuit 70 produces pulses that are gated through NOR gate 71 by ER as shown in Fig. 3, producing the burst of GATE pulses indicated by numeral 91 during every eleventh SYNC pulse. This turns MOSFET switch 19 on and off at approximately 16 the 500 kilohertz rate and thereby causing the trickle current or low current charging.

The widths of the GATE pulses during the high current mode, when TELO is a 11011 as indicated by numeral 92 in Fig. 4, and is determined by circuitry in the on-time modulator 15, as shown in detail in Fig. 3.

The voltage on the VI5EmsE conductor 21 is an analog voltage which is initiated by the source electrode of MOSFET switch 19 at the frequency of on time modulator 15 (which is a frequency of about 500 kilohertz). The high frequency component is filtered out of this by filter 20. At each peak value of, IVDC there is a peak of current and ot V,,,,,,, and at each minimura or valley of HVDC there is a minimum of current VISEMSE' This results in the "ripple" appearance of V,,,,,, in Fig. 4.

V ISERSE 'S fed back to the input of on-time modulator 15 to force the ripple of V ISENSE to be as small as possible. This i's accoXaplished by having a maximum on-time for switch 19 during the valleys of IMC, and a minimum on-time for switch 19 during the peaks.of HVDC. A maximum fifty percent duty cycle is indicated in the expanded time scale portion of the GATE signal at the valleys of HVDC in Fig. 4. The much smaller duty cycle. corresponds to the peaks of HVDC. The duty cycle of GATE during the high charging current mode operation varies continuously between these extremes over every half cycle of the line voltage. This has the effect of maximizing the total power output of the attery charger circuit 1 while preventing the drain-to-source 1-7 breakdown voltage of MOSFET 19 from being exceeded.

It should be appreciated that the "flyback" voltage VCR on conductor 17 (Fig. 1) can be approximately one thousand volts or more when switch 19 is turned off while a large current is flowing in primary winding 7A. More specifically, at the peaks of KVDC, the drain-to-source breakdown voltage of MOSFET 19, which typically might be 1000 volts, would be exceeded if the on time of MOSPET 19 has a 50 percent duty cycle value at that time. It should be appreciated that if the on time of MOSFET 19 is set to a constant smaller value which avoids the condition of VCR exceeding a thousand volts, then less power wouldbe delivered to secondary winding 7B, rectifier 10, and battery 11 during the "valleys" of HVDC than if MOSFET 19 is on for a long time.

In accordance with the present invention, the on time of MOSFET 19 is continuously modulated by V,,,,,, in order to achieve imaximum power coupled across transformer 7 without exceeding 'the breakdown voltage of MOSFET 19. Furthermore, continuous modulation of the on time of MOSFET 19 provides a mechanism to keep the charger output current constant as the battery voltage rises and as transformer inductance and/or loss changes with ambient temperature. Furthermore, the current control provides a maximum current limit to protect the charger from defective (e.g., shorted) cells in the battery pack.

Error amplifier 63 amplifies the difference voltage between V conductor 21 and the divided-down reference voltage VSENSE-D on conductor 22A. Its output goes to an input of comparator 62 1.9 and completes a feedback 100P in such a way as to minimize the difference in voltage between conductors 21 and 22A. An increase in this difference results in an increase in the output voltage of amplifier 63 such that the ramp generator voltage takes longer (i.e., greater switch on time) before causing comparator 62 to switch. Thus, the longer on time of switch 19 increases the average primary current which opposes the initial difference voltage.

Ramp generator circuit 64 produces a ramp signal at a rate of about 500 to 1000 kilohertz to provide a modulating signal that is used to convert the voltage produced by,rror amplifier 63 into a time delay that actuates one-shot 70 and also represents the on time of MOSPET 19. One-shot circuit 70 determines the widths of the 11011 level portions of the GATE waveform and hence the "off time" of MOSFET switch 19. The off time of MOSFET switch 19 is constant regardless of what the mbdulator circuit 15 does to the "on time" of MOSFET switch 19. The point at which the 500 kilohertz ramp signal produced on conductor 64A exceeds the output voltage produced by error amplifier 63 determines the width of the I'll, portions of the GATE waveform and hence the "on time" of 140SFET 19. When one-shot 70 times ont,-the signal on conductor 70A resets the output of ramp generator 54 as explained above and the ramp signal is repeated.

The timeout duration of one-shot 70, which is equal to the coff time of MOSPET 19, is designed to be equal to one-half of the period of the resonant frequency established by the transformer 101 primary winding inductance LR and the resonant capacitor CR. The primary flyback voltage VCR therefore has a half sine waveform returning to zero before MOSFET 19 is turned on for the next cycle. Thus, the power loss in MOSFET switch 19 is minimized, and noise generated by the flyback waveform VCR is concentrated at the resonant frequency of about 500 kilohertz, with less energy at higher multiples of the frequency than would be the case for a flyback voltage with a non-sinusoidal shape. This results in "zero voltage switching" of MOSFET 19, so it is turned on when there is zero voltage (drain-to-source) across it.

The on tine of MOSPET 19 is modulated by t.he feedback voltage V ISENSE which represents the amount of current flowing in primary winding 7A. The in odulation of the on time of MOSFET 19 by means of the feedback

voltage V,,,,,,, (which represents the current in primary winding 7A) results in minimum power dissipation in MOSFET ig, And,essentially eliminates switching transients, which, if present, would produce undesirable electrical noise that might interfere with operation of communications equipment connected to battery 11 or in its vicinity while it is being charged.

The V ISENSE waveform contains several components, including a DC component that represents the average power in primary winding 7A, and an AC component that represents the switching frequency (about 500 to 1000 kilohertz) of MOSFET 19, and another AC.component at the 60 hertz line frequency that appears as ripple, as an envelope of V,,,,,,. This envelope signal is compared by comparator 62 with the ramp signal on conductor 64A of Fig. 3 to produce the on time modulation of the GATE waveform.

The intervals during which MOSFET switch 19 is off is related by the expression T,)ffr,TLRCR.

to primary winding inductance L. and resonant capacitance C..

(Although during the off time of MOSPET 19, the primary winding circuit oscillates for half a cycle at the resonant frequency, when MOSFET 19 is on, the primary winding circuit does not resonate, so the an tine Of MOSPET 19 can be varied independently of the resonant frequency.) % HVDC energizes the primary winding of the transformer. The power to the modulator is supplied from the YSENSE line.

RESET signal 8 is used to reset flip-flop 56, the ripple counter for the ratchet DAC, and the hour timer that generates te time-out signal To.. 1 The technique of using ratchet DAC 50 and associated circuitry might be replaced by a peak detect and hold circuit in combination with circuitry that would compare the peak detect and hold circuit output voltage with the instantaneous battery voltage to determine whether the "droop" characteristic of achieving a fully charged battery condition has occurred; the results of that comparison then could be used to establish a low current charging mode.

The V ISERSE voltage alternatively could be implemented by means of an additional transformer, the primary winding of which b 12-1 conducts the current also flowing in primary winding 7A. A secondary winding of the additional transformer would generate a signal indicative of current flowing through primary winding 7A. An alternate embodiment of the invention is shown in Figs. 5-7. In many respects, the low noise, high rate battery charger 1A of Fig. 5 is similar to the one shown in Fig. 1. However, in the circuit of Fig. 51 the battery voltage is detected by circuit 5A, which, although similar to the AV detector circuit 5 of Fig. 1, is located on the "battery side" rather than the "line side" of the isolation transformer 7. The second secondary winding 26 1 and rectifier 28 are used in the circuit of Fig.,5 to produce power for the modulation and control circuit 15, but are not used to generate a signal indicative of tle battery voltage. A signal LVDC (analogous to V,,, ,, of Fig. 1) produced by rectifier 28 provides an indication as to whether the battery connection terminals 10A and 10B are open-circulted or effectively shortcircuited- In the circuit of Fig. 5, the condition of the battery is indicated by frequency-modulated signals coupled across isolation barrier capacitors 104A and 104B and then applied to inputs of modulation and control circuit 15A. A voltage to frequency converter 112 produces two different frequency signals F and F which are coupled across isolation barrier capacitors 104A and 104B to produce signals P and 'P on conductors 114A and 114B which indicate the presence of a droop AV of, for example, at least 100 Millivolts.

2- AV detector/LBD driver circuit 5A also produces an output signal L/O (LED Output) on conductor 103 connected to the cathode of a light emitting diode 101A that is illuminated when the charger is in a trickle charge mode and to the anode of a light emitting diode 101B that is illuminated when the battery charger is in a fast charge mode.

In Fig. 5, the LED driver signal L/O on conductor 103 is connected such that when L/O is at a 11011 level corresponding to the trickle charge mode, LED 101A is forward-biased and therefore illuminated, and LED 101B is reverse-biased and therefore off.

The opposite condition exists when L/O is a 11111 and the battery charger is in the fast charge mode. This configuration allows the indicator LEDs 101A and 101B to be located either on the battery charger or a battery location between its terminals simply by running conductor 103--to the battery along with the attery cable lines 10A and 10B_ I Rectifier 3 of Fig. 5 functions essentially the same as rectifier 3 in Fig. I to produce the full-wave rectified signal HVDC an conductor 4. The signal SYNC produced on conductor 23 in Fig. 7 is produced by differentiation circuitry in sync circuit 40A in Fig. 7 in a manner entirely similar to that accomplished by circuitry 40 in Fig. 2. Modulation and control circuit 15A in Fig. 7 responds to 1) the presence or absence of detection of a 100 millivolt droop AV communicated across isolation barrier capacitors 104A,B by AV detector circuitry SA, 2) an open circuit or short-circuit condition between output lines 10A and 23 10B, and 3) to the RMS (root mean square) value of the current in primary winding 7A, indicated by the voltage V, on conductor 1 21A developed across resistor R..

In accordance with the present invention, the current flowing through primary Winding 7A (Fig. 5) is controlled by modulating the on time of switch 19 in response to the difference between VREF and V, with the off time being constant, as previously described. This precisely regulates the output current driven into battery 11. The battery charging circuit 1A therefore appears to be a current source as seen by battery 11.

Referring mainly to Fig. 7, sync circuit 40A, functions entirely similarly to the corresponding circuitry in Fig. 2. The frequency divider circuit 42 functions essentially similarly to the corresponding circuitry in Fig. 2 to limit TO (Time Out) on conductor 132 to the amount of time that battery charger circuit 15A can operate in the fast charge mode to one hour, to therdby prevent overcharging battery 11 in the event of a AV detector malfunction.

Frequency divider circuit 42 also produces an "initial" hold signal HD on conductor 131 that causes battery charger 15A to operate in its fast charge mode for at least the first two minutes after battery charger 15A begins charging, because otherwise the battery terminal characteristics could indicate a false droop condition during the first two minutes of charging.

Frequency divider circuit 42 also produces a signal F/44 on conductor 12. 8 that divides SYNC by a (rather arbitrary) factor of 4 44. This circuit is used to cause battery charger 15A to continue to detect a AV droop signal of at least:100 millivolts for 22 consecutive SYNC pulses before allowing battery charger 15A to switch from its fast charge mode to its low charge mode. This reduces the likelihood of a noise condition being erroneously detected as a droop condition that switches the battery charger 15A into a trickle charge mode. control logic 115, in cooperation with driver timer circuit 122, determines in response to the signals SYNC, HD, TO, F/44, VDC, NL (no load), SC (short circuit), and DROOPI, whether the an time of switch 19 during each cycle of operation, hould be its maximum value corresponding to the fast charge mode, or at a minimum on time for each cycle of operation, corresponding to a trickle charge mode. Control logic 115 is, in essence, simply a state machine that responds to 1) a high level of HD to produce a f ast charge mode for two minutes regardless of the condition'of any of the other inputs, 2) a high condition of TO which occurs an hour after commencement of the fast charge mode independently of any of the other inputs, 3) presence of the DROOP1 signal on conductor 123 for 22 consecutive sync pulses before allowing switching from the fast charge inode to a trickie charge mode, and responds to a high condition of the NL or SC signals to switch from a fast charge mode to a trickle charge mode after the HD signal has elapsed. This avoids wasting power when NL is a '1111 and avoids possible damage to the battery charger outputcircuitry when sc is a "I".

During the high current charging mode, IHI,is a 11111, and driver timer circuit 122 synchronizes TGATE, and hence the signal GATE produced by WC (voltage to frequency converter) circuit 121 with HVDC, thereby synchronizing the turning on of switch 19 and hence also the current flow in the primary winding 7A with HVDC.

Z (VFC circuit 121 can be implemented in various ways, for example in essentially the same manner as the circuitry of Fig. 3.) This synchronization results in switching the primary winding current off near the zero crossing points of the AC line current. This is compatible with a small filter capacitor in the line voltage rectifier 3, and eliminates power dissipation in, the circuitry driving switch 19 during that time, resulting in maxi-mum efficiency of battery charger operation in the fast charge mode. The battery voltage droop voltage AV also is sensed during this period of zero battery charging current, eliminating inaccuracy caused by resistive voltage drops across battery charger calles and, connection terminals.

The control logic 115 ignores DROOP1 except for the time following the trailing edge of the TGATE pulses. IHI changes state only when DROOP1 is a 11111 during the low state of TGATE, and switch 19 is turned off. In the trickle charge mode,. the efficiency of the battery charger is not critical because very little power is being delivered to the battery. The duty cycle of TGATE is increased during trickle mode operation in order to improve operation of the peak detector 106A in detecting a trickle output current magnitude.

26 During the fast charge mode of battery charger 1A, the 0.5 to 1.0 megahertz bursts of GATE are enabled by TGATE for approximately 50 percent of each line voltage cycle, during the times that HVDC experiences its peak values. The primary winding current, and hence the secondary winding current and the current supplied to charge battery 11 is a function of the magnitude of HVDC and the turns ratio of transformer 7. To accomplish this, driver timer 122 responds to the absolute value of HVDC to determine when it should be supplying charging current to battery 11, and the TGATE waveform in Fig. 8 clearly shows this relationship.

Battery charger 1A of Fig. 5 charges battery 11 at a pulsed rate equal to twice the AC line voltage frequency, and avoids generating noise that inay interfere with external circuitry, such as cellular telephone circuitry, connected to the battery cliarger. Battery charger 1 of Fig. 1 accomplishes trickle M6de charging by producing GATE pulses during only one out of every 11 line voltage cycles. That results in associated noise having very low frequency, approximately 12 hertz, which is so low that it inay be difficult to remove by filter circuitry in a cellular telephone or the like powered by the battery being charged. Similar noise produced in battery charger 1A Of Fig. 5 produces 120 hertz, rather than 12 hertz noise, which is much easier to filter out.

In Fig. 7, resistor 93 connected between IHI and conductor 124 changes the voltage V,, on conductor 20 which modulates the 7-7 z on tine of switch 19 produced by GATE, but the frequency GATE is 0.5 to 1. 0 megahertz, pulsed at twice the 60 hertz line frequency. It should be noted that the duty cycle of TGATE is modified between the fast and trickle charging modes so as to enable peak detector 106 in Pig. 6 to more easily detect the trickle charge mode and accordingly change the L/O signal on conductor 103.

Referring to Fig. 8, each pulse 137 of the F/44 signal on conductor 128 is a "I" for durations of 22 cycles of the HVDC signal. When such a pulse coincides with the portion 138 of the V BATT (the, signal representing voltage of battery, 11) that is more than AV volts below the sampled and held voltage VO, battery charger 1A switches to the trickle charge mode, and the duty cycle of TGATE is modified or increased as indicated by numeral 141.to indicate the trickle chargenode. IHM and L/O changes state at the same time, as indicated by numerals 140 and 143.

- The V,,, voltage on conductor 120 is converted to an on time of switch 19. The signal GATE has a frequency of one-half to one megahertz, and TGATE gates this high frequency carrier at the AC line frequency, producing variable width high frequency bursts constituting the signal GATE, as previously described with reference to Fig. 4.

Droop demodulatorcircuit 117 is a frequency-to-voltage converter that detects whether the pulses constituting the signals P and are of a "low" frequency or a "high" frequency as shown by numeral 142 in Fig. 8 and produces a logic signal DROOP1 indicating whether a droop voltage &V of at least 100 millivolts has been detected.

Reference voltage generator circuit 116 generates a reference voltage VREF that is used by control logic 115 and driver timer 122. Block 116 also includes comparators that determine from the level of LVDC (which is analogous to V SENSE in Pigs. 1 and 3) whether a no load (NL) or short circuit (sc) condition appears between the battery charger output lines 10A and 10B.

Referring particularly to Fig. 6, AV detector/LED driver circuit 5A includes ratchet DAC 50 which function's in essentially the same manner as in the circuit of Fig. 1 to produce an output V. that increases as RCHT continues to be produced by gate 53 to clock ripple counter 55 until VO equals the voltage V BATT 1 on conductor 44A, which is a scaled down representation of the battery voltage produced by voltage divider 86A,86B. Since'DAC 50 functions as a sample and hold circuit. when V8ATT1 falls or "droops" by AV, this is detected by w indow comparator 110, producing a signal DROOP2 on conductor 111 indicating whether the droop AV is at least 100 inillivolts. If DROOP2 is a 111111, this causes VFC (voltage-tofrequency converter) driver circuit 112 to produce complementary high frequency or low frequency signals F and F on conductors 113A and 113B to be coupled across isolation barrier capacitors 104A and 104B to modulation and control circuit 15A.

Window comparator circuit 110 causes DROOP2 to have a high 29 level only if the droop voltage AV is between an upper limit and a lower limit of, for example, 100 inillivolts to,200 millivolts. The voltage ripple signal (V, ,p) produced on conductor 102 by rectifier 10 of Fig. 5 contains a large a-mount of high frequency switching noise at the 500 KHz to 1 MHz frequency of the GATE signal. Inductor 107 filters out a substantial portion of such high frequency noise. The SYNC2 circuit included in block 106 iases the difference between the unfiltered VRIP signal on conductor 102 and the filtered B+ voltage on conductor IOA to produce the signal SYNC2 on conductor 135- (It is necessary to generate the SYNC2 signal because a signal synchr'onized with the HVDC signal is required on both sides of isolation transformer 7.) The SYNC2 circuit in block 106 consists of a comparator that compares the unfiltered V'RIP signal with the filtered B+ voltage to generate pulse signals with edges that coincide with the peaks and valleys of the current that charges battery 11. 1 The peak detector circuit included in block 106 produces the LED output control signal L/O on conductor 103. The peak detector circuit in block 106 is simply a rectifier and capacitor. The average voltage across that rectifier and capacitor indicates whether battery 11 is being charged ir the f ast charge inode or in the trickle charge mode. When the battery charger circuit is in its fast charge mode, the high frequency noise components of VRIP have a higher average value than in the trickle charge mode. This higher average value produces a high level of L/O.

Comparator los generates a signal RESET2 to reset ripple counter 55 when battery 11 is disconnected from terminals 10A and 10B, thereby resetting V. of DAC 50 to its minimum output level.

It should be appreciated that although battery charger 1A of Fig. 5 communicates a signal that represents only the presence or absence of detection of a AV voltage droop which indicates a fully charged N1Cad battery across the capacitive isolation barrier 104A,104B to modulation and control circuit 15A, it would be possible to linearly change the frequency of the signal coupled across isolation barrier capacitors 104A and 104B to linearly represent the present battery voltage. ' ' The AV detection then could be performed as in the battery.charger 1 of Figs. 13 on the AC line voltage side of transformer 7. That approach, however, requires very accurate modulation and demodulation of the frequency representing the battery voltage. Battery charger 1 of Figs. 5-7 does not require such accurate modulation and' demodulation.

The foregoing approach is illustrated in Fig. 9, in which battery charger IB is very similar to battery charger 1A of Fig. 5, except that the AV detecting circuit in block SA of Fig. 5. instead is included in block 15B of Fig. 9. Fig. 10 show! more specifically which components in the &V detector circuit shown in Fig. 6 have been moved to the opposite side of isolation barrier capacitors 104A and 104B. The same reference numerals, followed by the letter "All, have been used to designate components which have been moved from block SA of Fig. 5 to block 15B of Fig. 9 - 3 The battery condition voltage produced in battery charger IB of Fig. 9 is provided as an input to a voltage-to-frequency/ driver circuit 112A, as shown in Fig. 11, to produce the signals F and on conductors 113A and 113B, respectively. As shown in Fig. 10, the AV detector circuitry in block 15B includes a conventional battery voltage demodulator circuit 117A, which receives the signals P and '9 coupled across the capacitive isolation barrier on conductors 114A and 114R, respectively.

Battery charger 1A of Figs. 5-7 has the important ad-vantage over the embodiment of Fig. 1 that large changes in amplitude of the AC line voltage are much less likely to cau.-,,e a "false droop" condition that prematurely switches battery charger IA from the fast charge mode to the trickle charge mode. This is because the measurement of the battery voltage condition on the "battery side" of transformer 7 and transmitting thereof across isolation Iarrier capacitors 104A,104B in the embodiment of Figs. 5-7 is more accurate than rectifying the.output of the secondary winding 7C in the embodiment of Fig. 1.

Battery charger IA of Fig. 5 and battery charger 1B of Fig. 9 also have the advantage of high efficiency, producing a maximum amount of charging current-to battery 11 without undergoing excessive temperature increases. This is important since the battery charger circuit in some. embodiments is housed in a very small package, such as in a male plug of a power cord.

it has been discovered that although the average AC line voltage amplitude rarely undergoes larger variations, the 32 amplitude variation between adjacent cycles of the line voltage frequently is very large, for example, 10 to 20 percent. The utilization of the F/44 signal on conductor 133 in cooperation with the circuitry in driver time-r circuit 122 requires 22 consecutive AV droop detections before modifying the TGATE voltage on conductor 134 switch from, the fast charge mode to the trickle charge mode. This avoids false trickle charge mode changes due to amplitude variations of one or a small number of cycles of the AC line voltage.

The pulses conducted across isolation barrier capacitors 104A and 104B are only demodulated during interv;-,s of time during which the switch 19 is open and the primary winding is not energized. The TGATE signal enables or disables the GATE signal on conductor 16 to switch 19 every cycle of the AC line voltage. Thi!sk avoids the ef fects of noise being coupled from the primary winding to the isolation barrier capacitors 104A and 104B, allowing more accurate demodulation.

By performing the AV voltage droop detection during times when no current is flowing in the primary winding 7A, the effect of voltage drops across the battery cable conductors 10A and 10B are avoided, resulting in more accurate AV measurements. This is important in applications in which a long cable is required between the battery and the charger.

Claims (12)

WHAT TS CLAIMED IS

1. A battery charger comprising in combination:

(a) a first rectifier [3] receiving a line voltage and producing a rectified sinusoidal voltage [HVDC];.

(b) a transformer [7] having a primary winding coupled to receive the rectified sinusoidal voltage an a secondary winding, a second rectifier [101 being coupled between terminals of the secondary winding and terminals of a battery; (c) a switch [19] coupled to a terminal of the primary winding; (d) means (26] coupled to the switch for producing a signal indicative of current flowing through the switch and primary winding; (e) battery condition means (7C,28 in Fig. 1; 86A,B in Fig.. 6; IOA in Pig. 11] for producing a battery condition voltage iepresentative of a voltage between the terminals of the battery; (f) peak detect and hold means [50,53,55] coupled to receive the voltage proportional to the battery condition voltage and detect and hold a peak value thereof; (g) voltage droop measuring means (52 in Fig. 1; 110 in Fig. 6; 110A in Fig. 111 for comparing an output voltage of the peak detect and hold means with the voltage proportional to the battery condition voltage to produce a voltage droop signal [AV] when the voltage proportional to the battery condition voltage falls a predetermined threshold voltage below the output voltage of the peak detect and hold means; and 34 (h) modulating means [15] coupled to receive a signal representative of the voltage droop signal [FULL-in Fig. 2; DROOPI in Fig. 7; DROOP in Fig. 101 and the signal indicative of current flowing through the primary winding for producing a control signal [GATE] applied to the switch [19) to control flow of current through the primary winding in accodance, with the battery condition voltage, the modulating means including means [70 in Fig. 3] for producing a constant turn off time for the switch [19] and means [26,63,64,62 in Fig. 31 for varying turn on time for the switch in response to the signal indicative of current flowing through the primary winding.

2 (Fig. 1). The battery charger of Claim 1 wherein the battery condition means includes isolation barrier means [7,7C] doupled between the terminals of the battery and having an otLtput V SENSE 1 that is DC isolated from the battery for producing the battery condition voltage 1 v SENSE]

3 (Embodiment of Fig. 5). The battery charger of Claim 1 wherein the battery condition means C86A,B of Fig. 61 is coupled between the terminals of the battery, the battery charger further including isolation barrier means [104A,B of Fig. 5] for coupling the voltage droop signal from the voltage droop ineasuring means to the modulating means.

4 (Fig. 5). The battery charger of Claim 3 including means [112 of Fig. 6] coupled to one port of the isolation barrier means for converting the voltage droop signal CDROOP2] to a digital signal [P] having a first frequency if the voltage droop signal is present and a second frequency if the voltage droop signal is not present, and means [117 in Fig. 7] coupled to another port of the isolation barrier means for demodulating the digital signal to produce the signal representative (DROOP1] of the voltage droop signal.

1 (Fig. g). The battery charger of Claim 1 wherein the battery condition means [10A in Fig. 11) is coupled between the terminals of the battery, the battery charger further including isolation barrier means for coupling the battery condition voltage from the battery condition means to the peak detect 'and hold means.

6 (Fig. g). The battery charger of Claim 5 wherein the battery condition means includes voltage-to-frequency converting means [112A in Fig. 11] for producing a digital signal IF] the frequency of which represents the voltage of the battery, the isolation barrier means coupling the digital signal (P] from the voltage-to-frequency converting means 1112A] to the peak detect and hold means.

1 :7:> C,

7 (Fig. g). The battery charger of Claim 6 wherein the peak detect and hold means includes means [117A in Fig. 101 for receiving the digital signal coupled by the isolation barrier means and converting it to an analog signal EV BATT 1 representing the battery voltage.

8. The battery charger of Claim 1 including means (40 in Fig. 2] responsive to the rectified sinusoidal voltage for producing a timing signal (SYNC), wherein the peak detect and hold means includes a DAC [50] having an output F.'oupled to a first input of a comparator [511, a ripple counter [55] having outputs coupled to digital inputs of the DAC and a gate circuit 153] having an output coupled to a toggle input of the ripple couiter, an output of the comparator (51] being coupled to a first input of the gate circuit [53], a second input of the jate circuit (53] being coupled to receive the timing signal (SYNC].

9. The battery charger of Claim 1 wherein the means for varying the turn on time continuously varies the turn on time between a maximum turn on time during a valley of the rectified sinusoidal voltage and a minimum turn on time during a peak of the rectified sinusoidal voltage during each half cycle of the line voltage to thereby maximize power delivered to the battery.

Z1

10. The battery charger of claim 9 wherein the means for varying the turn on time includes means (122 inFig. 7] for synchronizing the control signal [GATE] with the rectified sinusoidal voltage (HVDC] in order to synchronize the current flowing through the primary winding with the rectified sinusoidal voltage.

11. The battery charger of Claim 10 wherein the battery condition sensing circuit includes means for producing the battery condition voltage when the current flowing through the primary winding is essentially equal to zero to avoid inaccuracy in the voltage droop signal due to resistive voltage drops in connections coupling the battery to the second rectifier.

1 8 9 10 11

12. A method of charging a battery using a battery charger, comprising the steps of:

(a) rectifying an AC line voltage to produce a sinusoidal rectified voltage and applying it to a primary winding of a transformer, a rectifier [10] being coupled between terminals of a secondary winding of the transformer and terminals of a battery to supply a rectified charging current to the battery; (b) operating a switch [19] coupled between a terminal of the primary winding to control current through the primary winding (c) producing a signal IVISENSE in Fig. 1 Figs. 5 and 9] indicative of primary winding current; LVDC in 1 1 _ b - 14 15 1-6 17 1 is 24 25 26 27 28 29 1 (d) producing a battery condition voltage [V BATT representative of voltage between the terminals of the battery; (e) detecting and storing a peak value [MAX VALUE OF VO] of a reference voltage proportional to the battery condition voltage; (f) comparing the stored peak value with the voltage proportional to the battery condition voltage to produce a charging mode signal [IL0=11111 in Fig. 1; IHI=11011 in Fig. 7] with a low charging mode state when the voltage falls a predetermined threshold voltage below the peak value; and (g) controlling flow of current through the switch [19] by turning the switch off for times which are equal to a predetermined proportion of a resonant period associated with the primary winding and turning the switch on for times which vary in response to the signal indicative of the primary winding current 1..1

11. The battery charger of Claim 10 wherein the battery condition means includes means for producing the battery condition voltage when the current flowing through the primary 1 winding is essentially equal to zero to avoid ingaccuracy in the voltage droop.signal due to resistive voltage drops in connections coupling the battery to the second rectifier.

12. A method of charging a battery using a battery charger, comprising the steps of:

(a) rectifying an AC line voltage to prodmce a sinusoidal rectified voltage and applying it to a pri-mary winding of a transformer, a rectifier [103 being coupled between terminals of a secondary winding of the transformer and terminals of a battery to supply a rectified charging current to th!a battery; (b) operating a switch [19] coupled between a terminal of the primary winding to control current through the primary winding; LVDC in Figs.

producing a signal (v ISENSE in Fig. 1 SIZ and 9] indicative of primary winding current; (d) producing a battery condition voltage EVEATT3 representative of voltage between the terminals of the battery; (e) detecting and storing a peak value (MAX VALUE OF Vt)] of a reference voltage proportional to the battery condition voltage; (f) comparing the. stored peak value with the voltage proportional to the battery condition voltage to produce a charging mode signal [ILO=111" in Fig. 1; M1=11011 in Fig. 7] with a low charging mode state when the voltage falls a predetermined threshold voltage below the peak value; and 1 1 (g) controlling flow of current through the switch E19] by turning the switch off for constant times and turning the switch on for times which vary in response to the signal indicative of the primary winding current.

13. A battery charger substantially as herein described with reference to and as illustrated in the accompany drawings.

14. A method of charging a battery substantially as herein described with reference to the accompany drawings.

-501 -- Amendrnents to the clairns have been filed as follows 1 4 6 7 8 11 12 13 14 is 16 17 1. A battery charger comprising in combination:

(a) a first rectifier [3] receiving a line voltage and producing a rectified sinusoidal voltage [HVDC]; (b) a transformer [7] having a primary winding [7A] coupled to receive the rectified sinusoidal voltage and a secondary winding [7B], a second rectifier [10] being coupled between terminals of the secondary winding and terminals of a battery [11]; (c) a switch [19] coupled in series relation with a terminal of the primary winding; (d) a circuit [20,26] coupled to the switch and producing a signal [v ISENSE-DI indicative of current flowing through the switch [10] and primary winding [7A]; (e) a battery condition sensing circuit [7C,28 in Fig. 1; 86A,B in Fig. 6; 10A in Fig. 11] for producing a battery condition voltage V SENSE representative of a voltage between the terminals of the battery; (f) a peak detect and hold circuit [50,53,55] 4-0 - 19 21 34 36 37 38 39 coupled to receive the voltage proportional to the battery condition voltage and detect and hold a peak value thereof; (g) voltage droop measuring circuit [52 in Fig. 1; 110 in Fig. 6; 110A in Fig. 11] comparing an output voltage of the peak detect and hold circuit with the voltage proportional to the battery condition voltage to produce a voltage droop signal [AV] when the voltage proportional to the battery condition voltage falls a predetermined threshold voltage below the output voltage of the peak detect and hold circuit; and (h) a modulating circuit [15] coupled to receive a signal representative of the voltage droop signal [FULL in Fig. 2; DROOP1 in Fig. 7; DROOP in Fig. 10] and the signal indicative of current flowing through the primary winding for producing a control signal [GATE] applied to the switch [19] to control flow of current through the primary winding in accordance with the battery condition voltage, the modulating circuit including means [70 in Fig. 3] for producing off times for the switch [19] equal to a predetermined proportion of a resonant period associated with the primary winding and means [26,63,64,62 in Fig. 3] for varying on times for the switch in response to the signal indicative of current flowing through the primary winding.

1 _ k --, 1 2 3 1 4 6 1 4 6 1) h:1 1:1;:

2 (Fig. 1). The battery charger of Claim 1 wherein the battery condition sensing circuit includes an isolation barrier [7,7C] coupled between the terminals of the battery and having an output [V SENSE] that is DC isolated from the battery producing the battery condition voltage [V SENSE] 3 (Embodiment of Fig. 5). The battery charger of Claim 1 wherein the battery condition sensing circuit [86A,B of Fig. 6] is coupled between the terminals of the battery, the battery charger further including an isolation barrier [104A,B of Fig. 5] coupling the voltage droop signal from the voltage droop measuring circuit to the modulating circuit.

4 (Fig. 5). The battery charger of Claim 3 including means [112 of Fig. 6] coupled to one port of the isolation barrier for converting the voltage droop signal [DROOP2] to a digital signal [F] having a first frequency if the voltage droop signal is present and a second frequency if the voltage droop signal is not present, and a demodulation circuit [117 in Fig. 7] coupled to another port of the isolation barrier means and demodulating the digital signal to produce the signal representative [DROOP1] of the voltage droop signal.

j 1 1 -4Q, - 1 2 3 4 5 6 1 2 3 4 5 6 7 (Fig. 9). The battery charger of Claim 1 wherein the battery condition sensing circuit [10A in Fig. 111 is coupled between the terminals of the battery, the battery charger further including an isolation barrier coupling the battery condition voltage from the battery condition sensing circuit to the peak detect and hold circuit.

6 (Fig. 9). The battery charger of Claim 5 wherein the battery condition sensing circuit includes a voltageto-frequency converter [112A in Fig. 11] producing a digital signal [F] the frequency of which represents the voltage of the battery, the isolation barrier coupling the digital signal [F] from the voltage-to-frequency converting means [112A] to the peak detect and hold circuit.

7 (Fig. 9). The battery charger of Claim 6 wherein the peak detect and hold circuit includes means [117A in Fig. 10] for receiving the digital signal coupled by the isolation barrier means and converting it to an analog signal IVSATT] representing the battery voltage.

--)L F-) 1 7 8 9 1 2 3 4 6 1 2 3 4 5 6 8. The battery charger of Claim 1 including means [40 in Fig. 2] responsive to the rectified sinusoidal voltage for producing a timing signal [SYNC], wherein the peak detect and hold circuit includes a DAC [50] having an output coupled to a first input of a comparator [51], a ripple counter [55] having outputs coupled to digital inputs of the DAC and a gate circuit [53] having an output coupled to a toggle input of the ripple counter, an output of the comparator [51] being coupled to a first input of the gate circuit [53], a second input of the gate circuit [53] being coupled to receive the timing signal [SYNC].

9. The battery charger of Claim 1 wherein the means for varying the on times continuously varies the on times between a maximum on time during a valley of the rectified sinusoidal voltage and a minimum on time during a peak of the rectified sinusoidal voltage during each half cycle of the line voltage to thereby maximize power delivered to the battery.

10. The battery charger of Claim 9 wherein the means for varying the on times includes means [122 in Fig. 7] for synchronizing the control signal [GATE] with the rectified sinusoidal voltage [HVDC] in order to synchronize the current flowing through the primary winding with the rectified sinusoidal voltage.