GB2256768A

GB2256768A - Method and apparatus for separating synchronising signals from a composite television signal.

Info

Publication number: GB2256768A
Application number: GB9112651A
Authority: GB
Inventors: Robert Parsons
Original assignee: Individual
Current assignee: Individual
Priority date: 1991-06-12
Filing date: 1991-06-12
Publication date: 1992-12-16
Also published as: GB9112651D0

Abstract

A synchronising signal separator for television signals has a first small value capacitor which is charged to the peak voltage of a synchronising signal, and a second small value capacitor which is charged to black level voltage; the first and second capacitors, after being charged, being connected to share their charges with a third capacitor of much greater value than the first and second capacitors. The third capacitor becomes charged to a voltage intermediate between the synchronising signal peak voltage and black level voltage, which intermediate voltage is used as the threshold voltage of a comparator to which the composite video signal of the television signal is applied. <IMAGE>

Description

HETHOD AND APPARATUS FOR SEPARATING SYNCHRONISING SIGNALS FROM A COMPOSITE TELEVISION SIGNAL This invention relates to the separation of synchronising signals from a composite television signal.

In a television signal synchronising signals are transmitted in combination with the video waveform representing the image for the purpose of synchronising the generation of the display raster with the video waveforms so that the image is reproduced correctly. In order to distinguish the synchronising signals from the video waveforms they are of opposite polarity relative to black level to the video waveforms. The separation of the synchronising signals from the television signal is achieved by detecting the leading edge transients of the synchronising signals, usually negative-going and producing pulses at the instants of those transients. A comparator circuit having a threshold set to the mid-height of the synchronising signals is the usual apparatus employed for the separation.

Difficulties can arise in performing the synchronising signal separation reliably because of the variation in signal amplitude particularly in areas where reception of television is unsatisfactory. Another problem that can occur is that spurious noise pulses which can be interpreted as synchronising signals can distort the display of the received image by interfering with the generation of the scanning raster.

It is an object of the present invention to provide an improved synchronising signal separator.

According to one aspect of the present invention there is provided apparatus for separating synchronising signals from a composite television signal including an input circuit for the television signal, a first switched capacitor circuit connected to the input circuit and operated to store in its capacitor voltages representing the tips of synchronising signals, a second switched capacitor circuit connected to the input circuit and operated to store in its capacitor voltages representing black level, a third switched capacitor circuit connected to the first and second switched capacitor circuits and operated to accumulate in its capacitor a voltage intermediate between the mean voltage of the tips of the synchronising signals and the mean black level voltage, the third switched capacitor circuit having a capacitor of larger capacitance than the first and second switched capacitor circuits, and a comparator connected to the input circuit and the third switched capacitor circuit for comparing the television signal with the intermediate voltage and producing an output consisting of the synchronising signals.

The first and second switched capacitor circuits may each include a capacitor having one electrode grounded and switch means connected from the other electrode of the capacitor to the input circuit for the television signal.

The switch means is normally open circuit and is only closed to connect the respective capacitors to the input circuit when the television signal voltage has the values to be stored in the capacitors. The third switched capacitor circuit may include a capacitor with one electrode grounded and first and second switch means respectively connected from the other electrode of the capacitor of the third circuit to the other electrodes of the capacitors of the first and second circuits. The first and second switch means of the third circuit are also normally open circuit and only closed after the capacitors of the first and second circuits have been charged from the television signal and are disconnected again from the input circuit.The connection of the third circuit to the comparator may take the form of a direct connection from the other electrode of the capacitor of the third circuit to an input of the comparator.

The input circuit may include a series-connected capacitor through which the television signal is received and a clamping circuit operated to set the tips of the synchronising signals to a reference voltage level.

The operation of the switched capacitor circuits may be timed relative to the leading edges of preceding synchronising signals.

The apparatus may include start-up means using the capacitor of the third switched capacitor circuit to cause the comparator to produce an output on the occurrence of a negative-going portion of the input television signal.

The switch means may comprise MOS transistors and compensating switch means may be provided to counteract components of the switching signals which are capacitively coupled through the MOS transistors. The apparatus may be constructed as an integrated circuit with the switch means formed by MOS transistors and the capacitors formed by the gate to channel capacitances of MOS transistors having their source and drain electrodes grounded. The integrated circuit may include means for generating switching signals for the switch means. Means may also be provided in the integrated circuit for enabling both the analogue and digital parts of the apparatus to be tested.

According to a second aspect of the present invention there is provided a method of separating synchronising signals from a composite television signal including the steps of: connecting a first capacitor to the television signal for part of the duration of each synchronising signal so as to charge it to a voltage substantially equal to that of the tip of the synchronising signal, connecting a second capacitor to the television signal for part of the time for which that signal is at black level so as to charge it to a voltage substantially equal to black level voltage, connecting the first and second capacitors to a third capacitor of larger capacitance than the first and second capacitors, so as to accumulate in the third capacitor a voltage intermediate between that at the tips of the synchronising signal and the black level voltage, and comparing the composite television signal with the voltage on the third capacitor to provide an output consisting of the synchronising signals.

The timing of the connection of the television signal to the first and second capacitors may be based on previous occurrences of synchronising signals, the connection of the first and second capacitors to the third capacitor may take place after each charging of the first and second capacitors.

The invention will now be described with reference to the accompanying drawings, of which: FIGURE 1 is the circuit diagram of one example of a synchronising signal separator; FIGURE 2 shows one example of a switch of the kind which may be used in the circuit of Figure 1; and FIGURE 3 shows an example of the logic unit used in Figure 1.

Referring now to Figure 1, a composite video signal is applied to terminal 1 which is connected through to a capacitor 2 and a resistor 3 to a first, the upper, input of a comparator 5, that input also being connected to ground through a capacitor 4. The junction of the capacitor 2 and resistor 3 is also connected through a switch S1 and a resistor 6 to a conductor 7 maintained at a reference voltage level BIAS. In parallel with the switch S1 and the resistor 6 is a second switch S2 in series with a resistor 8. A switch S3 is connected from the junction of the capacitor 2 and resistor 3 to a switch S4 which is connected to a capacitor 9 having one terminal grounded and to a switch S5.The switch S3 is also connected through a switch S6 to switches S7 and S9. The switch S7 is connected to one terminal of a capacitor 10, the other terminal of which is grounded, and also to a switch S8.

The switches S5 and S8 are connected to the second, the lower, input of the comparator 5 and to a capacitor 11, the other terminal of which is grounded. The capacitor 11 is also connected through a resistor 12 and a switch S10 to the first input of the comparator 5 and through the switch S9 to the switch 56. The output of the comparator 5 is connected to a terminal 13 where the separated synchronising signals appear as an output and also to a logic unit 14 which drives the switches S1 to S12. The junction of the switches S3 and S6 is connected through a switch S11 to a terminal 15 to which a voltage A is applied.The junction of switches S6 and S9 is connected through a switch S12 to a terminal 16 to which a voltage B is applied. The voltages A and B are used in the test mode only and will be referred to later.

The switches S3, S6, S9, S11 and S12, which are enclosed in circles, take no part in the normal operation of the circuit, but are used in the testing of the circuit which will be described later. These switches are normally in the positions shown in Figure 1, that is to say switches S3 and S6 are normally closed and switches S9, Sil and S12 are normally open.

The operation of the circuit of Figure 1 will be described first in its normal running mode when switches S1, S4, S5, S7 and S8 are operated, the other switches being in the positions shown in Figure 1. The timing of the operations of the switches is derived from the leading edges of the synchronising signals as they appear at the output of the comparator 5 and which are fed to the logic unit 14 to provide the switching signals at the appropriate times as described below For simplicity in the description the composite video input signal is assumed to have negative-going synchronising signals, although the circuit will operate equally well with signals of either polarity.Following the leading edge of a synchronising pulse, the switch S1 is closed for a period of 1.5 ps thereby tending to move the voltage of the tip of the synchronising signal to the reference voltage BIAS.

After a few scan lines the voltage of the tip of the synchronising signal reaches and is maintained at BIAS.

Shortly after the opening of the switch S1 the switch S4 is closed for a period of about 150 ns also during the tip of the synchronising signal. While S4 is closed the switch S5 is open and the capacitor 9 is charged to a voltage corresponding to that of the tip of the synchronising signal, that is to say substantially equal to the reference voltage BIAS. Just after switch S4 is opened, the switch S5 is closed for about 150 ns and then opened again, so that the charge on the capacitor 9 is shared with the capacitor 11.After the end of the synchronising signal the composite video signal changes to black level at a part of the television signal known as a back porch, and, as soon as the black level voltage is stabilised after the level change, after a period of, say, 4ups, the switch S7 is closed charging the capacitor 10 to a voltage representing black level, the switch S8 being open. After 150 ns, the switch S7 is opened again and shortly afterwards the switch S8 is closed for about 150 ns and then opened again, so that the charge on the capacitor 10 is shared with the capacitor 11. Preferably the transfers of charges from the sampling capacitors (9,10) to the integrating capacitor (11) are made as soon as possible after each sampling, thus reducing the effects of leakage across the sampling capacitors.The capacitors 9 and 10 are of substantially the same capacitance, about 1 pf, and the capacitor 11 is of about 300 pf. At this time, the voltage stored on the capacitor 11 is maintained midway between that of the tip of the synchronising signal and the black level voltage.

The voltage on the capacitor 11 is applied to the lower input of the comparator 5. The voltage on capacitor 11 can change only relatively slowly; that reduces the influence of spurious noise pulses on that voltage and hence on the operation of comparator 5.

To the upper input of the comparator 5 is applied the composite video waveform from the capacitor 2 through a low-pass filter formed by the resistor 3 and the capacitor 4. The function of the low-pass filter is to attenuate the colour burst which appears on the back porch so that it does not appear to be additional synchronising signals.

The comparator 5 produces an output when the composite video signal applied to its upper input passes the voltage from the capacitor 11 at the start of a synchronising signal, so that the signals at the output of the comparator 5 represent the leading edges of the synchronising signals and are fed to the terminal 13 for synchronising the scanning and other circuits which use the synchronising signals, and to the logic unit 14.

The capacitor 11 is maintained at a voltage midway between the tip of the synchronising signal and black level by the transfer of small amounts of charge from the capacitors 9 and 10 by the operation of the switches S4, S5, S7 and S8, as described above. The level to which the voltage on the capacitor 11 is charged may be altered by changing the ratio between the values of the capacitors 9 and 10. Because the operation of the switches S1, S4, S5, S7 and S8 is timed with reference to the leading edge of a synchronising signal, it follows that the circuit as described can only operate when synchronising signals are appearing at the output of the comparator 5. When the circuit is first turned on, no synchronising signals will appear and it is necessary to establish some voltage levels on the capacitors 2 and 11 so that the circuit can operate.

The logic unit 14 is arranged to respond to the lack of synchronising signals from the comparator 5 for about three line periods, say 190-200 ps, by implementing a start-up procedure. For that procedure the switches S1, S4, S5 S7 and S8 remain open and the switches S2 and S10 are closed.

The closure of the switch S2 causes the voltage at the junction of the capacitor 2 and the resistor 3 to change relatively slowly to the reference voltage BIAS as determined by the time constant of the capacitor 2 and the resistor 8. The closure of the switch S10 connects the upper terminal of the comparator 5 through resistor 12 to the capacitor 11 which is connected to the lower terminal of the comparator 5. The composite video signal is applied more or less unaffected (apart from the colour burst) by the resistor 3 and the capacitor 4 to the upper terminal of the comparator 5 but it is subjected to considarable lowpass filtering by the combination of the resistor 12 and the capacitor 11 when it is applied to the lower terminal of the comparator 5.As a result of that low-pass filtering the comparator 5 produces an output signal similar to that produced by the leading edge of a synchronising signal in normal operation whenever the composite video signal includes a steeply negative-going transition because the upper terminal can follow the transition, whereas the lower terminal can only sluggishly follow the same transition so that it will remain more positive than the upper terminal for the duration of the transition.

The output of the comparator 5 resulting from the negative-going transition is applied to the logic unit 14 which responds to it in the same way as it does to the leading edge of a synchronising pulse, so that shortly afterwards the switch S1 is closed which has the effect of clamping the junction of the capacitor 2 and the resistor 3 to the reference voltage BIAS as described above. The reception of a synchronising signal by the logic unit 14 causes it to open the switches 52 and S10 again immediately and resume normal running of the circuit for at least three line periods even if no more synchronising signals are received.If the negative-going transition to which the comparator 5 responded was in fact the leading edge of a synchronising signal, then the normal operation of the circuit would continue and the charging of the capacitor 11 to the voltage intermediate between the tip of the synchronising signal and the black level will quickly be established.

If, however, the negative-going transition detected by the comparator 5 was not the leading edge of the synchronising signal but was part of the picture waveform, the fact that the switch S1 is still closed for a time after the detection of the transition by the comparator 5 means that the composite waveform would be raised to a more positive voltage level, assuming that the negative-going transition continues. The voltage on the capacitor 11 at this time is likely to be close to the reference voltage BIAS because that is the mean level of the composite signal from the capacitor 2.During the next two cycles of normal operation the voltage level of the composite waveform from the capacitor 2 becomes more positive and the voltage on the capacitor 11 is likely to become more negative because the voltage samples on the capacitors 9 and 10 are likely to be more negative than the voltage on capacitor 11. If at the end of the three line periods the voltage on capacitor 11 lies between black level and the tips of the synchronising signals then the normal operation of the circuit can continue. On the other hand, if synchronising signals are not appearing regularly at the output of the comparator 5 at the end of the three line periods, the logic unit 14 reverts to the start-up procedure again and the operations described above recommence. The cycle described is repeated until the apparatus operates normally.

Figure 2 shows the circuit diagram of one of the switches used in the separator shown in Figure 1. The switch is connected between an input terminal 20 and an output terminal 23 and consists of two MOS transistors 21 and 22 connected with their channels in parallel. The transistor 21 has a channel of N-type conductivity and the transistor 22 a channel of P-type conductivity. A switching signal is applied to a terminal 24 which is connected directly to the gate of the transistor 21 and through an inverter 25 to the gate of the transistor 22.

In the operation of the switch shown in Figure 2, either both transistors 21 and 22 are non-conducting or both are conducting as a result of a switching signal applied to the terminal 24. Because the channels of the transistors 21 and 22 are of different conductivity types, the switch can conduct readily in either direction between the terminals 20 and 23 with either input near ground or the supply voltage.

Since there is capacitance between the gate and the channel of each of the transistors 21 and 22, the switching signal can induce a voltage spike into the signal path between the terminals 20 and 23 and that voltage spike could be detected by the comparator 5 (Figure 1) and interfere with the operation of the circuit. In order to overcome that problem for those switches used in the apparatus of Figure 1 where the voltage spike could upset the operation, that is S4, S5, S7 and S8, a compensating switch consisting of transistors 26 and 27 may be provided.

Transistor 26 has a channel of P-type conductivity and the transistor 27 has a channel of N-type conductivity, the channels of the transistors being connected in parallel and having both source and drain connected to the output terminal 23. The gate of the transistor 26 is connected to the gate of the transistor 21 and the gate of the transistor 27 is connected to the gate of the transistor 22.Because the gate of the transistor 21 is connected to the gate of the transistor 26 and the transistor 26 has a channel of the opposite conductivity type to that of the channel of transistor 21, and the transistors 22 and 27 similarly have channels of the opposite conductivity type, the voltage errors due to charge injection through the gate-channel capacitances of the transistors 26 and 27 are of the opposite polarity to those induced through the gate channel capacitances of the transistors 21 and 22. It follows therefore that the effect of the transistors 26 and 27 is to counteract the charge injection through the transistors 21 and 22. For the same conductivity the P-channel transistors need to be about 2.7 times the size of the N-channel transistors because of the lower mobility of holes compared to that of electrons.Because of the difference in the sizes of the transistors it is desirable to have transistors of both types in the compensating switch, although it would be possible to get some compensation with a single transistor.

An alternative to switching transistors 26 and 27 simultaneously with transistors 21 and 22 is to delay the switching of transistors 26 and 27 by some interval.

The separator may be mainly constructed as a single integrated circuit using switches made as described with reference to Figure 2. The capacitors, especially capacitors 9, 10 and 11, may be formed by the gate to channel capacitances of MOS transistors having both source and drain connected to ground, such capacitances having a high value per unit area. It follows that the switches and the capacitors can be made by the same process steps. It will probably be necessary to use several MOS transistors to provide the values of capacitance required and in order to facilitate the testing of the construction and the parallel connection of the gates of those transistors the connection may join the gates in a series path, going in at one corner of each gate and leaving at the opposite corner; failure in the construction or the connection would then be revealed as a break in the series circuit which could be tested for.

The construction of the separator as an integrated circuit has the following advantages: 1) signal sampling, integration, and voltage subtraction and division are performed on the integrated circuit without any external components.

2) Critical performance areas of voltage differencing and division depend on capacitor ratios that can be accurately controlled during the manufacture of the integrated circuit. The performance is not dependent on absolute values of components, temperature or process parameters.

3) Long integration time constants, of the order of several hundred lines of a television scan, are used without the need for high value resistors which would use relatively large areas of an integrated circuit substrate.

The use of a long time constant reduces the effects of noise pulses and errors that can arise from the sampling of the broad field synchronising pulses.

4) All capacitors on the integrated circuit have one terminal connected to ground with the other terminal at a voltage above the MOSFET threshold; that enables gate oxide enhancement capacitors to be used which have a high specific capacitance.

5) The video signal is sampled for short intervals under the control of digital logic so that regions of the signal likely to be distorted can be avoided.

6) Digital logic is also used to determine the timing of the interval for clamping the tips of the synchronising signals, which renders the clamping operation independent of external factors.

Figure 3 shows the construction of the logic unit 14 of Figure 1 and has a terminal 30 to which the synchronising signal from the comparator 5 is applied.

The terminal 30 is connected to an input of counter latches 31 which are connected to combinational gate logic 33. Clock pulses are also applied to the latches 31 on conductor 32. In the operation of the separator circuit, the latches 31 combine with logic in the block 33 to form a counter which counts clock pulses received along conductor 32 following the input of a signal edge via the terminal 30. The logic 33 responds to the different states of the counter including the latches 31 and produces output signals which are received by decoder latches 34 and transmitted by transparent buffer latches 35 and conductors 37 to operate the switches Sl, S4, S5, S7 and S8. The timing of the operating of the switches is determined by the counter and the clock pulses.

The counter and the combinational gate logic 33 also detect when signal edges are not received via the conductor 30 for about three line periods and implement the start-up procedure described above, operating the switches S2 and S10 as described and resuming normal operation as soon as another signal edge is received on conductor 30.

The logic unit 14 also has a test mode of operation for assessing the functionality of the integrated circuit, that is to say the operation of the synchronising signal separator in the test mode, in normal running, and when starting up together with the operation of the digital part of the apparatus in the logic unit 14. The techniques used in the test mode include those commonly employed to test digital integrated circuits, using combinations of digital signals which are carried serially along dedicated shift register paths to establish input conditions for parts of the circuit and, after normal running of the circuit, using similar dedicated shift register paths to convey the resulting digital output signals to an output part of the circuit for examination.

In the present instance the test mode also includes facilities for monitoring the operation of the analogue part of the apparatus and testing the components. In Figure 1, the switches S3, S6, S9, S11 and S12 are used in the test mode, in conjunction with the other switches where necessary, to feed test voltages, including A and B applied to the terminals 15 and 16 respectively, to the capacitors and resistors and to the comparator 5. The testing of the capacitors as described earlier may also be done. The signals for operating the switches in the test mode are generated by the logic unit 14.

Referring again to Figure 3, the counter latches 31 and decoder latches 34 also operate as shift registers when switched to the test mode by means not shown. Further latches 38, termed scan latches are provided for use in the test mode and receive serial outputs from the latches 34 on conductor 40 and from the latches 31 via conductor 39, latches 34 and conductor 40. Clock signals are applied at 41 to the latches 38 which also act as a shift register and the serial output from those latches appears at a terminal 42. The operation of the buffer latches 36 can also be tested by the connection of the conductors 37 through the conductors 43 to individual ones of latches 38.

In the test mode, test data is fed serially along conductor 44 into the latches 31, acting as a shift register. The latches 31 may now be arranged to operate as a counter and the result fed out to the latches 38 via latches 34 or the test data may test the logic 33 and feed the outputs to latches 34, the output being fed serially to latches 38. The latches 36 may also be tested by the data in latches 34 using the parallel connections 43. In all cases of testing the digital circuitry the resulting data is fed out serially at the terminal 42.

Claims

CLAIMS:

1. Apparatus for separating synchronising signals from a composite television signal including an input circuit for the television signal, a first switched capacitor circuit connected to the input circuit and operated to store in its capacitor voltages representing the tips of synchronising signals, a second switched capacitor circuit connected to the input circuit and operated to store in its capacitor voltages representing black level, a third switched capacitor circuit connected to the first and second switched capacitor circuits and operated to accumulate in its capacitor a voltage intermediate between the mean voltage of the tips of the synchronising signals and the mean black level voltage, the third switched capacitor circuit having a capacitor of larger capacitance than the first and second switched capacitor circuits, and a comparator connected to the input circuit and the third switched capacitor circuit for comparing the television signal with the intermediate voltage and producing an output consisting of the synchronising signals.

2. Apparatus according to claim 1 wherein the first and second switched capacitor circuits each include a capacitor having one electrode grounded and switch means connected from the other electrode of the capacitor to the input circuit for the television signal, the switch means of the first and second switched capacitor circuits being normally open circuit and only closed to connect the respective capacitors to the input circuit when the television signal voltage has the values to be stored in the capacitors and the third switched capacitor circuit includes a capacitor with one electrode grounded and first and second switch means respectively connected from the other electrode of the capacitor to the other electrodes of the capacitors of the first and second switched capacitor circuits, the other electrode of the capacitor of the third switched capacitor also being connected directly to the comparator, and the first and second switch means of the third switched capacitor circuit being normally open circuit and only closed after each of the capacitors of the first and second switched capacitor circuits have been charged from the television signal and are disconnected again from the input circuit.

3. Apparatus according to claim 2 wherein each switch means is connected to a respective compensating switch which is operated simultaneously with or after the particular switch means and is such as to apply to the output of the particular switch means a pulse of opposite polarity to that induced in the output of particular switch means by a switching signal.

4. Apparatus according to claim 2 or 3 wherein the switch means of the switched capacitor circuits are MOS transistors and the capacitors of the switched capacitor circuits are formed by the gate to channel capacitances of a plurality of MOS transistors having their source and drain electrodes connected to ground.

5. Apparatus according to any one of the preceding claims wherein the input circuit includes a series connected capacitor through which the television signal is received and a clamping circuit which is operated to set the tips of the synchronising signals to a reference voltage level.

6. Apparatus according to claim 5 including start-up means for connecting the input circuit to an input of the comparator through a low-pass filter so that the comparator produces an output in response to a negative-going transition in the television signal, the start-up means being disabled by the production from the comparator of a regular series of separated synchronising signals at the line frequency of the television signal.

7. Apparatus according to any one of the preceding claims including timing means responsive to the synchronising signals produced by the comparator for operating the switched capacitor circuits at times related to the leading edges of the synchronising signals.

8. Apparatus according to any one of the preceding claims formed as a single integrated circuit.

9. Apparatus according to claim 8 including means for enabling the testing of the switched capacitor circuits, the comparator and the timing circuits.

10. Apparatus for separating synchronising signals from a composite television signal substantially as herein described and as illustrated by the accompanying drawings.

11. A method of separating synchronising signals from a composite television signal including the steps of: connecting a first capacitor to the television signal for part of the duration of each synchronising signal so as to charge it to a voltage substantially equal to that of the tip of the synchronising signal, connecting a second capacitor to the television signal for part of the time for which that signal is at black level so as to charge it to a voltage substantially equal to black level voltage, connecting the first and second capacitor to a third capacitor of larger capacitance than the first and second capacitors, so as to accumulate in the third capacitor a voltage intermediate between that at the tips of the synchronising signal and the black level voltage, and comparing the composite television signal with the voltage on the third capacitor to provide an output consisting of the synchronising signals.

12. A method according to claim 11 wherein the timing of the connection of the television signal to the first and second capacitors is based on previous occurrences of synchronising signals.

13. A method according to claim 11 or 12 wherein the connection of the first and second capacitors to the third capacitor is timed to take place after each charging of the first and second capacitors.

14. A method according to any one of claims 11 to 13 wherein in order to start operation of the circuit the third capacitor forms part of a low-pass filter to which the composite television signal is applied, the television signal being compared with that appearing across the third capacitor so that the comparing operation results in an output in response to a negative-going transition in a television signal.

15. A method of separating synchronising signals from a composite television signal substantially as herein described and as illustrated by the accompanying drawings.