GB2252465A - Flicker elimination system - Google Patents

Abstract

A flicker elimination system contains a receiver/ demodulator 9/10 which feeds frame stores 12, 17. Two consecutive incoming interlaced fields are written in one store and are subsequently read out in progressive scan format whilst the next fields are written in the other store. Preferably each progressive frame is read out at least twice whilst the next frame is stored. Interline flicker (and large area flicker) are thus removed. <IMAGE>

Description

Flicker Elimination in Visual DisDlavs This invention relates to the elimination of flicker in visual displays.

Visual displays are well known and understood in the fields of television receivers, radar displays and computer terminals. They all may suffer from an effect referred to as flicker. This is an effect caused by the display being refreshed at a fixed rate, e.g. every 20 msecs (50Hz) in a television receiver, and the repetition being perceived by a human observer.

It is well known that large area flicker is hard to perceive at frequencies greater than 70Hz. Television has the added drawback of interline flicker as it uses an interlaced scan system.

According to the present invention a system can be produced which accepts currently broadcast interlaced television transmissions and displays them with the interlace removed. The repetition rate of the displayed picture can be any integer multiple of the incoming picture.

A specific embodiment of the invention will now be described by way of example with reference to the accompanying drawing in which:figure 1 shows a block diagrams of the electronic system.

The broadcast signal is received 9 and demodulated 10, in a manner well known to those practised in the art. The demodulated signal is sampled and stored in memory. This may involve analogue to digital conversion 11 and digital storage 12. At the end of the first field, the system stores the second field in a convenient form for retrieval. This is controlled by the write synchronizer 13. An example is to store the first field in odd addresses and the even field in even addresses. When two fields are present, the read synchronization circuit 14 retrieves the store samples and displays them on the screen digital to analogue conversion 16 is required when analogue to digital conversion has taken place before storage 15. In a demonstration system two fields one frame, are read and displayed in the time it takes to store one field and the frame is displayed twice whilst a new pair of fields is being written to a separate store 17. The displayed picture has the same content as the original but the interlace has been removed. A full frame is displayed in a single sequential scan. A typical system would display the same number of lines as the original. A frame can be displayed twice for every incoming frame. By alternating between store A 12 and store B17 the sequence of incoming and displayed frames would always be the same. The combination of interlace elimination and multiple frame display eliminates inter-line and large area flicker.

Claims (6)

Claims

1. A system for the conversion of interlaced television signals to signals which may be displayed on a sequential scanned visual display unit.

2. A system as claimed in Claim 1 which incorporates a means for storing at least one frame of the signal.

3. A system according to Claims 1 to which displays a reconstructed frame two or more times for each incoming frame.

4. A system as claimed in Claims 1 to 3 which has means to convert between analogue and digital signals at the store input and output.

5. A system as claimed in Claim 1 to 4 which has means to synchronize the store write sequence to the received signal and means to synchronize the store read sequence to the requirements of the visual display.

6. A system as claimed in Claims 1 to 5 which stores an even field in alternate positions and an odd field in the inter leaved alternate position creating a sequentially stored frame from two fields.