GB2249217A

GB2249217A - Semiconductor device planarisation

Info

Publication number: GB2249217A
Application number: GB9122517A
Authority: GB
Inventors: Kyu-Pil Lee; Inho Nam
Original assignee: Samsung Electronics Co Ltd
Current assignee: Samsung Electronics Co Ltd
Priority date: 1990-10-23
Filing date: 1991-10-23
Publication date: 1992-04-29
Also published as: JPH04282832A; DE4135443A1; GB9122517D0; KR920008841A; KR940007070B1

Abstract

A semiconductor device includes a silicon substrate (5) in which an element region is separated from field oxide (31) films on the substrate and active elements are selectively formed on an element region. Undulations are flattened by planarisation materials forming a two-layered structure (35, 38) having an etching rate similar to each other and extending between the two-layered flattening materials is a conductive pattern (36) for contacting active elements. <IMAGE>

Description

224 -)-217 SEMICONDUCTOR DEVICES 9 The present invention relates to a

method for flattening undulations occurring during the manufacture in a semiconductor device and a semiconductor device fabricated by the method. more particularly, the present invention provides in such a method a first flattening process for undulations due to the multi-layered construction using a thermal fluidic insulating film such as a boro-phosphosilicate glass doped with boron-phosphorus and then forming a conductive layer and a second process of flattening the 0 conductive layer with a boron -phosphorus having a good thermal fluidity instead of capping the conductive layer with a thermal oxide f ilm.

A disclosure of a conventional dynamic random access memory,

DRAM, having a low integrity is found in U.S. Patent No.

4,782,037, grated in the name of A. Tomozawa et al.

c 3L c As disclosed conventional DRAM is fabricated according to the steps of:

forming on a semiconductor substrate of first type conductivity a gate electrode comprised of a polycrystalline silicon layer and a layer formed on the polycrystalline silicon layer and containing a silicide of a refractory metal such as molybdenum silicide (MoSi2), forming semiconductor regions of second conductivity type for providing source or drain regions t in the semiconductor substrate at at least one side of the gate electrode, forming a first insulating film having an initial thickness, by chemical vapor deposition, covering the gate electrode and the semiconductor regions, forming a second insulating film over the first insulating film, heating the second insulating film so as to cause glass flow of the second insulating film, the first insulating filmhaving suchan initial 1 thickness that, after the step of heating the second insulating film, the thickness of the first insulating film that has not been subjected to glass flow is at least 600k, whereby peeling 2 1 of the layer containing a silicide of a refractory metal from the polycrystalline silicon layer is substantially avoided, and forming a conductive layer, which comprises an aluminum film, over the second insulating film.

An object of the conventional prior art technology is to prevent the layer including a refractory metal from peeling off the semiconductor integrated circuit device, which is formed of 1 a conductive layer of two-layered construction having a layer containing a refractory metal layer or a silicide layer of the refractory metal. Such a technology, however, is applicable just to a low integrated DRAM of less than lm bit, and is not applicable to a DRAM of more than 1M bit, because the vertical 1 step structure is deteriorated due to the trend toward high density of elements. Therefore, because it is difficult to make follow-up metal line patterning processes with the conventional 1 mono-flattening process, it is inevitable to use a multi-step flattening process.

A heretofore undisclosed earlier development by the inventor 3 1 of the present invention provides a multi -flattening process shown in FIGS. 2A and 2B. Thus forming part of the accompanying drawings is FIG. 1A which is a plan view of a general DWA11 cell.

9 FIG. 1B is a plan view of a peripheral circuit of DRAM Cell, FIG.

2A is a section taken along line A - A' of FIG. 1; and FIG. 2B is a sectional view taken along line C - C' of FIG. 1B.

After field oxide films 21 and capacitor electrodes 23 are

0 formed on a substrate S, a word line WL and a gate electrode G are formed. An N± type impurity region 22 forming a metal-oxidesemiconductor transistor is formed, and non-fluidic insulating films 24 are then formed by chemical vapor deposition (CVD). A layer of boro-phosphosilicate glasses 25 are formed on the whole exposed surface to complete a first flattening process.

Thereafter, conductive layer 26 made of a polycide pattern is 1 formed so as to make contact with the impurity region 22. An oxide film 27 is then formed by chemical vapor deposition and the film 27 is annealed. A boro-phosphosilicate glass layer 28 is then formed as shown in FIG. 2A.

4 1 After the second flattening process is carried out by forming the layer 28, thus producing the two-layered borophosphosilicate glass construction, a contact hole H is formed, and metal films 29 are formed. When the oxide film 27 is annealed, the conductive layer 26 is prevented from being lifted, and at the same time, the electrically resistance of the conductive layer 26 and the electrical resistance in contact with t region 22 can be reduced.

The number of treatment steps is increased by forming the non-fluidic insulating film 27 by chemical vapor deposition such as high temperature oxide films or low temperature oxide films.

in addition, as the contact hole H is formed after flattening the undulations caused by the multi-layered construction with the boro-phosphosilicate glass 25 and 28, a differential step occurs t in the side walls of the contact hole H because of the difference of etching rates between the materials forming the high temperature oxide films 24 and 27 and the boro-phosphosilicate glass 25 and 28. As a result a problem occurs because the metal 1 films 29 are broken, i.e., become discontinuous.

More specifically, side wall stepping occurs when the thermal oxide films 27 situated between the boro-phosphosilicate glass 25 and 28 has an etching rate different from the etching rates of layers of first and second boro-phosphosilicate glass.

Also film 27 forms a cap over the conductive layer 26. Wet chemical etching is required for removing a natural silicon oxide 1 film having a thickness of many angstrom. This natural silicon oxide film occurs on the bottom of the contact hole and must be removed so as to obtain the stable electrical characteristics of the contact hole before the metal films 29 are formed. Electrical continuity is destroyed when projection parts of layers formed on the side walls of the contact hole occur due to etching rate difference between the thermal oxide films 27 and the second 4 boro-phosphosilicate glass 28. Areas of metal films are destroyed by irregular projection parts of the side walls of the contact holes.

Furthermore, since non-fluidic films such as insulating 6 1 layers 27 must be formed by chemical vapor deposition in such a multi-flattening process, processing steps are necessarily increased. For example, in the event conductive layer 26 is not capped with the insulating films 27, the silicide film is oxidized and lifted thereby causing electrical disconnection.

Therefore, in the multi -flattening process by thermal flow, the present invention avoids and eliminates non-fluidic and 1 inter-layer insulating films between fluidic f lattened- insulating layers in order to solve the above problems.

According to the present invention there is provided a method for making a semiconductor device, the method including the steps of:

forming a capacitor and access transistors on a silicon 4 substrate where field oxide films are formed; forming inter-layer insulating layers on the substrate; applying and reflowing a first layer of flattening material on the inter-layer insulating layers to carry out the firs t t flattening by reflowing of the first flattened layer; forming a first conductive pattern by chemical vapor deposition on the first flattened layer; applying and reflowing a second layer of flattening material on the first conductive pattern to carry out the second flattening by reflowing the first conductive pattern according to nitrogen annealing, and forming a contact hole and a metal film to form an electrically connection with the transistor.

According to a further aspect of the present invention there is provided a semiconductor device having silicon substrate of a first type conductivity, an element region separated from field oxide films on the substrate, active elements -selectively formed on the element region, flattening materials of a two-layered structure having etching rates similar to each other, and a conductive pattern extending between the two-layered 1 flattening materials for contacting the active elements.

Theses features and advantages of the present invention as well as others will be more fully understood when read in light 8 1 of the accompanying drawings in which FIG. IA is a DRAM cell lay -Out typically illustrating a DRAM cell of the type that can be constructed as shown in FIGS.

2A and 2B as well as according to the present invention shown in FIGS. 3A, 3B and 4A - 4E.

FIG. 1B is a DRAM cell lay-out of a region of a peripheral 1 circuit; FIG. 2A is a sectional view as typically taken along lines A - A' of FIG. 1 and showing semiconductor construction developed by the inventors prior to the present invention; FIG. 2B is a sectional view as typically taken along lines B - B' of FIG. 1 and showing semiconductor construction developed 1 by the inventors prior to the present invention; 1 FIG. 3A is a sectional view as typically taken along lines A - A' of FIG. 1 and showing semiconductor construction according to the present invention; FIG. 3B is a sectional view as typically taken along lines B - B' of FIG. 1 and showing semiconductor construction according 9 to the present invention; FIGS. 4A, 4B, 4C, 4D and 4E are sectional views typically taken along lines C C' of FIG. 1B and illustrating manufacturing sequence including flattening processes for undulations in a semiconductor device according to the present invention.

A preferred embodiment of the present invention will now be described in reference to FIGS. 3A and 3B. A P-type silicon substrate is selected on which field oxide films 31 are formed.

A cell capacitor, a word line WL and a gate electrode G are formed on the silicon substrate S. Impurity regions are then formed, and after inter-layer insulating films 34 are deposited 1 on the gate electrodes G of the access transistors, first flattened layers 35 made of a boro-phosphosilicate glass are deposited. Thereafter, a first conductive pattern 36 made of a silicide film with contacts to an impurity region 32 is deposited on the first flattened layers 35. This first conductive pattern X 0 36 is used as a bit line. A second flattened layer 38 made of a boro-phosphosilicate glass is deposited on the conductive pattern 36 and metal films 39 are formed thereon.

FIG. 3B, similar to FIG. 3A, is a typical section taken along lines B - B' of FIG. 1 and illustrates the first and second flattened layers 35 and 38 in contact with each other without 0 any intermediate or interleaving layer between them as found for example in the semiconductor configuration shown in FIGS. 2A and 2B. However, the conductive pattern 36 is situated as shown in FIGS. 3A and 3B between the layers 35 and 38 for extending into electrical conductivity with impurity region 32.

Turning now to FIGS. 4A, 4B, 4C, 4D and 4E which are sectional views of a manufacturing sequence that includes 1 flattening processes for the manufacture of a DRAM cell according to the present invention.

First, field oxide films 31 are formed on the P-type substrate S, and elements such as a capacitor or MOS transistors are then formed on the substrate. More particularly, capacitor I- X A 9 electrodes 33 are formed (shown only in FIGS.3A and 3B) and a gate oxide film GO and gate electrode G are then formed. An N± type impurity region 32 is then formed by ion-implanting N-type impurities. Thereafter, an inter-layer insulating film 34 is formed by chemical vapor deposition so as to prevent the peeling phenomenon occurred by the glass flow of the flattened layers c made of boro-phosphosilicate glass as shown in FIG. 4A.

To facilitate the deposition processes, a first flattened layer 35 is formed, and the first flattening is performed by reflowing the first flattened layer as shown in FIG. 4B. The first flattened layer 35 may be made from one of a silicon oxide film (boro-phosphosilicate glass) doped with an impurity selected from the group consisting of boron-phosphorus and phosphorus.

1 Thereafter a first conductive layer is formed by chemical vapor deposition on the first flattened layer 35, and a first conductive pattern 36 used as a bit line is formed by carrying out a photo-etching process as shown in FIG. 4C. The conductive pattern 36 is a polycide film made of a polycrystalline silicon X 2 t film and a silicide film that is formed on the polycrystalline silicon film. This silicide film maybe made of refractory metals having low electrical resistance such as molybdenum, tungsten, tantalum or titanium. In addition, the silicide film is composed of a refractory metal and silicon. This refractory metal will 0 endure the thermal treatment required in a manufacturing process of a-DRAM.

After forming a second flattened layer 38 on the first flattened layer 35 where the first conductive pattern 36 is formed, the second flattening is carried out by annealing in a nitrogen atmosphere (FIG. 4D). In such annealing there is one method where the N2 gas-annealing is additionally carried out so as to low the electrical resistance of the first conductive t pattern 36 after the first conductive pattern 36 is formed.

Another method of N2 gas-annealing provides that the first conductive pattern 36 is annealed simultaneously with annealing the second flattened layer 38. The latter annealing method is preferred over the former because the later method reduces the :L 3 1 1 number of treatment steps. The second flattened layer 38 is made from the same material as the first flattened layer 35.

After a photo-sensitive material is deposited on such a second flattened layer 38, a contact hole H is formed by photo- etching, and the photo-sensitive material is then removed. A c me tal f i lm 3 9 i s f o rmed in contact hole H whe reby a semi conducto r device according to the present invention is obtained (FIG. 4E).

According to the present invention, instead of capping a conductive pattern with a high temperature or low temperature oxide film, the flattening is carried out with thermal fluidic insulating films thereby preventing the generation of projection parts on side walls of a contact hole which is caused different t etching rates of the first and second layers. Therefore the method of the present invention prevents breakage of the metal films that maybe caused by a step-like difference between layers during etching for the forming of metal films.

At the same time, after forming the conductive pattern, the flattening is directly carried out with a thermal fluidi X 4 q a insulating film without capping the conductive pattern with a high temperature oxide film or low temperature one, thereby reducing the number of the treatment steps.

while the present invention has been described in connection with the preferred embodiments of the various figures, it is to 1 be understood that other similar embodiments may be used or modifications and additions may be made to- the described embodiment for performing the same function of the present invention without deviating therefrom. Therefore, the present invention should not be limited to any single embodiment, but rather construed in breadth and scope in accordance with the recitation of the appended claims.

c 3-5 q

Claims

1. A method for making a semiconductor device said method including the steps of:

forming a capacitor and access transistors on a silicon substrate where field oxide films are formed; forming inter-layer insulating layers on the surface of the substrate; applying and reflowing first layer of flattening material on the inter-layer insulating layers to the first flattening by the reflowing of the first flattened layer; forming a first conductive pattern by chemical vapor deposition on the first flattened layers; t applying and reflowing a second layer of flattening material on said first conductive pattern to carry out the second flattening by reflowing said first conductive pattern according to,trcir-n -annealing; and forming a contact hole and a metal film to form an electrically connection with said transistor.

16 1 k

2. The method according to claim 1 wherein the materials comprising the first and second layers of flattening material have substantially the same etching rate.

3. The method according to claim 2 wherein the materials e comprising the first and second layers of flattening material have substantially the same thermal fluidic characteristics.

4. The method according to claim 3 wherein the materials comprising said first and second layer of flattening material are each silicon oxide doped with a material selected from the group consisting of boron-phosphorous.

5. The method according to claim 1 wherein said first conductive pattern is further defined to comprise a polycide t f ilm.

6. The method according to claim 1 wherein said first conductive pattern is further defined to comprise a polysilicon f ilm.

7. The method according to claim 1 wherein said nitrogen is carried out to reduce the electrical resistance of the first IL -7 4 X conducting pattern.

8. A semiconductor device including the combination of a silicon substrate of a first type conductivity, an element region R separated from field oxide films on said substrate, active t elements selectively formed on said element region, flattening materials of a two-layered structure having the etching rate similar to each other, and a conductive pattern extending between said two-layered flattening materials for contacting said active elements.

9. A method for making a semiconductor device, which method is substantially as hereinbefore described with reference to, and as illustrated by, the accompanying drawings.

10. A semiconductor device substantially as hereinbefore described with reference to, and as illustrated by, the accompanying drawings.

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