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GB2247965B - Dual-port memory device - Google Patents

Dual-port memory device

Info

Publication number
GB2247965B
GB2247965B GB9020183A GB9020183A GB2247965B GB 2247965 B GB2247965 B GB 2247965B GB 9020183 A GB9020183 A GB 9020183A GB 9020183 A GB9020183 A GB 9020183A GB 2247965 B GB2247965 B GB 2247965B
Authority
GB
United Kingdom
Prior art keywords
transfer
memory
redundant
sam
dual
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
GB9020183A
Other versions
GB2247965A (en
GB9020183D0 (en
Inventor
Jang-Kyu Lee
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Priority to GB9020183A priority Critical patent/GB2247965B/en
Priority to FR9011389A priority patent/FR2666917B1/en
Priority to DE19904029247 priority patent/DE4029247C2/en
Publication of GB9020183D0 publication Critical patent/GB9020183D0/en
Publication of GB2247965A publication Critical patent/GB2247965A/en
Application granted granted Critical
Publication of GB2247965B publication Critical patent/GB2247965B/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/80—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout
    • G11C29/816—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout for an application-specific layout
    • G11C29/818—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout for an application-specific layout for dual-port memories
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1075—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for multiport memories each having random access ports and serial ports, e.g. video RAM
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/86—Masking faults in memories by using spares or by reconfiguring in serial access memories, e.g. shift registers, CCDs, bubble memories

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Dram (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

A dual-port memory device for split data transfer comprises: a first normal memory pan comprising a first RAM 20, a first SAM 22 and a first transfer gate 24 connected for memory data transfer between them, a second normal memory pan comprising a second RAM 30, a second SAM 32 and a second transfer gate 34 connected for memory data transfer between them; a transfer memory signal generator 40 for providing first and second transfer signals to the first and second transfer gates respectively; and a redundant memory 50 comprising a redundant RAM 60, a redundant SAM 62, a redundant transfer gate 64 and a redundant transfer signal generator 70 for selecting one of the first and second transfer signals so that if a defect arises in either memory pan the redundant memory can substitute therefor. <IMAGE>
GB9020183A 1990-09-14 1990-09-14 Dual-port memory device Expired - Lifetime GB2247965B (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
GB9020183A GB2247965B (en) 1990-09-14 1990-09-14 Dual-port memory device
FR9011389A FR2666917B1 (en) 1990-09-14 1990-09-14 DUAL ACCESS STORAGE DEVICE.
DE19904029247 DE4029247C2 (en) 1990-09-14 1990-09-14 Dual port storage device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB9020183A GB2247965B (en) 1990-09-14 1990-09-14 Dual-port memory device

Publications (3)

Publication Number Publication Date
GB9020183D0 GB9020183D0 (en) 1990-10-24
GB2247965A GB2247965A (en) 1992-03-18
GB2247965B true GB2247965B (en) 1994-08-24

Family

ID=10682252

Family Applications (1)

Application Number Title Priority Date Filing Date
GB9020183A Expired - Lifetime GB2247965B (en) 1990-09-14 1990-09-14 Dual-port memory device

Country Status (3)

Country Link
DE (1) DE4029247C2 (en)
FR (1) FR2666917B1 (en)
GB (1) GB2247965B (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5646896A (en) * 1995-10-31 1997-07-08 Hyundai Electronics America Memory device with reduced number of fuses

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0172016A2 (en) * 1984-08-14 1986-02-19 Fujitsu Limited Semiconductor memory device having a redundancy circuit

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60501878A (en) * 1983-07-14 1985-10-31 アドバンスト・マイクロ・ディバイシズ・インコ−ポレ−テッド Byte-wide memory circuit with column redundancy circuit
DE3588156T2 (en) * 1985-01-22 1998-01-08 Texas Instruments Inc., Dallas, Tex. Semiconductor memory with serial access
US4719601A (en) * 1986-05-02 1988-01-12 International Business Machine Corporation Column redundancy for two port random access memory
JPH0283899A (en) * 1988-09-20 1990-03-23 Fujitsu Ltd Semiconductor memory
JPH0289299A (en) * 1988-09-27 1990-03-29 Nec Corp Semiconductor storage device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0172016A2 (en) * 1984-08-14 1986-02-19 Fujitsu Limited Semiconductor memory device having a redundancy circuit

Also Published As

Publication number Publication date
GB2247965A (en) 1992-03-18
DE4029247A1 (en) 1992-03-19
DE4029247C2 (en) 1994-04-14
GB9020183D0 (en) 1990-10-24
FR2666917A1 (en) 1992-03-20
FR2666917B1 (en) 1994-02-18

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Legal Events

Date Code Title Description
PE20 Patent expired after termination of 20 years

Expiry date: 20100913