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GB2245763B - Process for reducing program disturbance in eeprom arrays - Google Patents

Process for reducing program disturbance in eeprom arrays

Info

Publication number
GB2245763B
GB2245763B GB9113571A GB9113571A GB2245763B GB 2245763 B GB2245763 B GB 2245763B GB 9113571 A GB9113571 A GB 9113571A GB 9113571 A GB9113571 A GB 9113571A GB 2245763 B GB2245763 B GB 2245763B
Authority
GB
United Kingdom
Prior art keywords
program disturbance
reducing program
eeprom arrays
eeprom
arrays
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
GB9113571A
Other versions
GB9113571D0 (en
GB2245763A (en
Inventor
Jyh-Cherng J Tzeng
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US07/455,510 external-priority patent/US5215934A/en
Application filed by Intel Corp filed Critical Intel Corp
Priority to GB9113571A priority Critical patent/GB2245763B/en
Publication of GB9113571D0 publication Critical patent/GB9113571D0/en
Publication of GB2245763A publication Critical patent/GB2245763A/en
Application granted granted Critical
Publication of GB2245763B publication Critical patent/GB2245763B/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B41/00Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10D64/01346
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/68Floating-gate IGFETs
    • H10D30/681Floating-gate IGFETs having only two programming levels
    • H10D30/684Floating-gate IGFETs having only two programming levels programmed by hot carrier injection
    • H10D30/685Floating-gate IGFETs having only two programming levels programmed by hot carrier injection from the channel
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/68Floating-gate IGFETs
    • H10D30/6891Floating-gate IGFETs characterised by the shapes, relative sizes or dispositions of the floating gate electrode
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00Electrodes of devices having potential barriers
    • H10D64/01Manufacture or treatment
    • H10D64/031Manufacture or treatment of data-storage electrodes
    • H10D64/035Manufacture or treatment of data-storage electrodes comprising conductor-insulator-conductor-insulator-semiconductor structures
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00Electrodes of devices having potential barriers
    • H10D64/60Electrodes characterised by their materials
    • H10D64/66Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/661Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation
    • H10P14/6309
GB9113571A 1989-12-21 1991-06-21 Process for reducing program disturbance in eeprom arrays Expired - Lifetime GB2245763B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
GB9113571A GB2245763B (en) 1989-12-21 1991-06-21 Process for reducing program disturbance in eeprom arrays

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US07/455,510 US5215934A (en) 1989-12-21 1989-12-21 Process for reducing program disturbance in eeprom arrays
GB9113571A GB2245763B (en) 1989-12-21 1991-06-21 Process for reducing program disturbance in eeprom arrays

Publications (3)

Publication Number Publication Date
GB9113571D0 GB9113571D0 (en) 1991-08-14
GB2245763A GB2245763A (en) 1992-01-08
GB2245763B true GB2245763B (en) 1993-11-03

Family

ID=26299117

Family Applications (1)

Application Number Title Priority Date Filing Date
GB9113571A Expired - Lifetime GB2245763B (en) 1989-12-21 1991-06-21 Process for reducing program disturbance in eeprom arrays

Country Status (1)

Country Link
GB (1) GB2245763B (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2234834A (en) * 1989-08-07 1991-02-13 Intel Corp A novel architecture for virtual ground high-density eproms
GB2239347A (en) * 1989-12-21 1991-06-26 Intel Corp Process for reducing program disturbance in EEPROM arrays

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2234834A (en) * 1989-08-07 1991-02-13 Intel Corp A novel architecture for virtual ground high-density eproms
GB2239347A (en) * 1989-12-21 1991-06-26 Intel Corp Process for reducing program disturbance in EEPROM arrays

Also Published As

Publication number Publication date
GB9113571D0 (en) 1991-08-14
GB2245763A (en) 1992-01-08

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