[go: up one dir, main page]

GB2244176B - Method and apparatus for forming a conductive pattern on an integrated circuit - Google Patents

Method and apparatus for forming a conductive pattern on an integrated circuit

Info

Publication number
GB2244176B
GB2244176B GB9108848A GB9108848A GB2244176B GB 2244176 B GB2244176 B GB 2244176B GB 9108848 A GB9108848 A GB 9108848A GB 9108848 A GB9108848 A GB 9108848A GB 2244176 B GB2244176 B GB 2244176B
Authority
GB
United Kingdom
Prior art keywords
integrated circuit
pads
photoresist
exposed
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
GB9108848A
Other versions
GB9108848D0 (en
GB2244176A (en
Inventor
Melissa D Boyd
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
HP Inc
Original Assignee
Hewlett Packard Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hewlett Packard Co filed Critical Hewlett Packard Co
Publication of GB9108848D0 publication Critical patent/GB9108848D0/en
Publication of GB2244176A publication Critical patent/GB2244176A/en
Application granted granted Critical
Publication of GB2244176B publication Critical patent/GB2244176B/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H10W72/20—
    • H10W72/01255—
    • H10W72/251—
    • H10W72/252—
    • H10W72/923—
    • H10W72/9445—
    • H10W72/952—

Landscapes

  • Wire Bonding (AREA)
  • Electroplating Methods And Accessories (AREA)

Abstract

In a method for processing an integrated circuit of the type having conductive die bond pads thereon the fabricated IC is coated with a layer of photoresist (16) which is exposed to create a pattern which includes windows (18-29) over the pads and a connection between at least two of the pads. The exposed photoresist is dissolved and the exposed portions are plated with gold to a depth sufficient for creating a bump over each die bond pad suitable for bonding a conductive lead thereto. The remaining photoresist is dissolved thus leaving a plurality of bumps for attaching conductive leads thereto and an electrical connection (24, 26, 28) between at least two of the bumps. <IMAGE>
GB9108848A 1990-05-18 1991-04-24 Method and apparatus for forming a conductive pattern on an integrated circuit Expired - Fee Related GB2244176B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US52593590A 1990-05-18 1990-05-18

Publications (3)

Publication Number Publication Date
GB9108848D0 GB9108848D0 (en) 1991-06-12
GB2244176A GB2244176A (en) 1991-11-20
GB2244176B true GB2244176B (en) 1994-10-05

Family

ID=24095225

Family Applications (1)

Application Number Title Priority Date Filing Date
GB9108848A Expired - Fee Related GB2244176B (en) 1990-05-18 1991-04-24 Method and apparatus for forming a conductive pattern on an integrated circuit

Country Status (2)

Country Link
GB (1) GB2244176B (en)
HK (1) HK22295A (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2263018B (en) * 1991-03-23 1995-06-21 Sony Corp Static random access memories
GB2254487B (en) * 1991-03-23 1995-06-21 Sony Corp Full CMOS type static random access memories
KR100335875B1 (en) * 1998-07-03 2002-05-08 아오야기 모리키 Wiring board for bump bonding, semiconductor device assembled from the wiring board and manufacturing method of wiring board for bump bonding

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1567808A (en) * 1976-07-15 1980-05-21 Nippon Telegraph & Telephone Semiconductor devices and method of manufacturing the same
US4394678A (en) * 1979-09-19 1983-07-19 Motorola, Inc. Elevated edge-protected bonding pedestals for semiconductor devices
GB2180991A (en) * 1985-08-28 1987-04-08 Mitsubishi Electric Corp Silicide electrode for semiconductor device
US4927505A (en) * 1988-07-05 1990-05-22 Motorola Inc. Metallization scheme providing adhesion and barrier properties

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1567808A (en) * 1976-07-15 1980-05-21 Nippon Telegraph & Telephone Semiconductor devices and method of manufacturing the same
US4394678A (en) * 1979-09-19 1983-07-19 Motorola, Inc. Elevated edge-protected bonding pedestals for semiconductor devices
GB2180991A (en) * 1985-08-28 1987-04-08 Mitsubishi Electric Corp Silicide electrode for semiconductor device
US4927505A (en) * 1988-07-05 1990-05-22 Motorola Inc. Metallization scheme providing adhesion and barrier properties

Also Published As

Publication number Publication date
GB9108848D0 (en) 1991-06-12
GB2244176A (en) 1991-11-20
HK22295A (en) 1995-02-24

Similar Documents

Publication Publication Date Title
US6291271B1 (en) Method of making semiconductor chip package
JP2962586B2 (en) Semiconductor device, method of manufacturing the same, and joined body used therefor
US6294824B1 (en) Bonding support for leads-over-chip process
US5561328A (en) Photo-definable template for semiconductor chip alignment
JP3069010B2 (en) Multi-chip module with interconnect decals manufactured on mandrel
EP0720232A4 (en) MULTICHIP CIRCUIT
EP0875935A3 (en) Semiconductor device having a projecting electrode
MY118146A (en) Flexible thin film ball grid array containing solder mask
EP0887851A3 (en) Method of forming interconnections on electronic modules
EP2053655A3 (en) Chip scale package using large ductile solder balls
US6271057B1 (en) Method of making semiconductor chip package
EP0852395A3 (en) Method of multiplexed joining of solder bumps to a substrate during assembly of an integrated circuit package
SG73389A1 (en) Method of connecting tab tape to semiconductor chip and bump sheet and bumped tape used in the method
EP0892274A3 (en) A system and method for easily inspecting a bonded state of a BGA/CSP type electronic part to a board
GB2137807B (en) A semiconductor component and method of manufacture
GB2244176B (en) Method and apparatus for forming a conductive pattern on an integrated circuit
MY120334A (en) Bump formation method
US5709336A (en) Method of forming a solderless electrical connection with a wirebond chip
JP2845218B2 (en) Electronic component mounting structure and method of manufacturing the same
JPH08236665A (en) Resin-sealed semiconductor device and manufacturing method thereof
KR0152559B1 (en) Manufacturing method of solder bump
DE3278301D1 (en) Tape for tape-automated-bonding of integrated circuits and method of producing the tape
MY116530A (en) Process and apparatus for forming ball bumps
KR200275422Y1 (en) Fluxing apparatus for BGA package
JPS595639A (en) Hybrid integrated circuit

Legal Events

Date Code Title Description
732E Amendments to the register in respect of changes of name or changes affecting rights (sect. 32/1977)
PCNP Patent ceased through non-payment of renewal fee