GB2243469A

GB2243469A - Digital signal processor

Info

Publication number: GB2243469A
Application number: GB9022567A
Authority: GB
Inventors: Makio Yamaki
Original assignee: Pioneer Electronic Corp
Current assignee: Pioneer Corp
Priority date: 1990-04-27
Filing date: 1990-10-17
Publication date: 1991-10-30
Anticipated expiration: 2010-10-17
Also published as: DE4036995C2; DE4036995A1; GB2243469B; GB9022567D0

Abstract

A digital signal processor having first and second arithmetic operating sections (11-15, 16-20) each comprising a digital multiplier (13, 18) for multiplying values of two digital signal data and a digital accumulator (15, 20) for accumulating an output value of the multiplier (13, 18), wherein an output of the multiplier (18) in the second arithmetic operation section (16-20) is connected to one input of the digital signal data of the multiplier (13) in the first arithmetic operating section (11-15). There is also provided a digital signal processor in which the output of the multiplier (18) in the second arithmetic operating section (16-20) is connected to one input of each of both of the multipliers (13, 18) in the first and second arithmetic operating sections (11-15, 16-20), respectively. Thus, the processing time can be reduced in the case of an arithmetic operation such that a plurality of coefficients are multiplied to a signal data value or an approximate value calculation. <IMAGE>

Description

DIGITAL SIGNAL PROCESSOR DIGITAL SIGNAL PROCESSOR The present invention

relates to a digital signal processor (hereinafter, referred to as a DSP).

There has been well known an audio signal processing apparatus for executing signal processes for a sound field control to audio signals so as to give presence in a home or vehicle by producing a sound field which is obtained by simultaing the sound field in an acoustic space of a concert hall or a theater. For instance, such an apparatus has been disclosed in JP-A-64-72615. Such an audio signal processing apparatus has a DSP to execute a sound field control by digital operation processing the audio signals which were output from an audio signal source such as a tuner or the like. The DSP has: an operating section to execute operating processes such as four arithmetical operations or the like; and memories such as data RAM to store digital audio signal data to be supplied to the operating section, a coefficient RAM to -2store digital coefficient signal data (hereinafter, simply referred to as coeficient data) which is multiplied to the audio signal data, and the like. In the DSP., the signal data is transferred among the memories and from the memories to the operating section and operating processes of the signal data can be repetitively executed at a high speed in accordance with predetermined programs. On the other hand, the programs have been written in a writable program memory such as an RAM or the like in the DSP. Each time a sound field mode is switched by a switching operation, the program is changed by a microcomputer provided on the outside of the DSP. That is, every acoustic space can be produced by changing the program.

As shown in Fig. 1, the conventional DSP comprises buffer memories 1 and 2, a multiplier 3, an ALU 4, and an accumulator 5. On the other hand, the DSP also has a signal data RAM 6 to store input digital signal data and a coefficient data RAM 7 to store a plurality of coefficient data. Upon operation, the signal data is read out of the signal data RAM 6 and is supplied and held into the buffer memory 1 through a bus 8. The coefficient data is sequentially read out of the coefficient data RAM 7 at predetermined timings and suupplied and held into the buffer memory 2. Values -3which are indicated by the data held in the buffer memories 1 and 2 are multiplied by the multiplier 3. The result of the multiplication by the multiplier 3 is added to a value held in the accumulator 5 by the ALU 4 and the resultant addition data is held in the accumulator 5. The ALU 4 and accumulator 5 form accumulating means. The output terminal of the accumulator 5 is connected to the buffer memory 1 and the signal data RAM 6 through the bus 8 and therefore the data held in the accumulator 5 is transferred to the buffer memory 1 or the signal data RAM 6 via the bus 8.

There is a case where an arithmetic operation E anbnxn in which two coefficient data values are multiplied to the signal data value and the multiplication results are accumulated is performed by using such a conventional DSP. an denotes a coefficient which changes in accordance with the progress of the program. bn indicates a fixed coefficient. In this case, al.xl is first calculated by the multiplier 3. The result of the calculation al.xl is transferred to the buffer memory 1 via the ALU 4, accumulator 5, and bus 8 and al.xl.bl is calculated by the multiplier 3. At this time, the ALU 4 executes an operation such that 0 is added to the result of the multiplication by the multiplier 3. The calculated result al.bl.xl is held in -4the accumulator 5. Then, a2x2 is calculated by the multiplier 3. The calculated result a2'x2 is transferred to the buffer memoroy 1 via the ALU 4, accumulator 5, and bus 8. a2'x2.b2 is calculated by the multiplier 3. The value of al.bl-xl held in the accumulator 5 and the value of the calculated a2-b2x2 are added by the ALU 4 and the addition result is held in the accumulator 5. By r\ repeating the above operations, E a bnxn is calculated. rj-, n However, in such a conventional DSP, in the case of the arithmetic operation such as E anbnxn in which a plurality of coefficients are multiplied to the signal data value, there are problems such that the number of steps of the program is large and it takes a long processing time. on the other hand, there is a case where it is desired to calculate an approximate value in the DSP by using, for instance, n cnx as an approximate equation of a non-linear functon. Cn denotes coefficient data and x indicates signal data. However, such DSP in which only the coefficient data is supplied to the buffer memory 2 as shown in Fig. 1, cannot calculate the power of the signal data value x by the multiplier 3 and cannot n obviously calculate 7_ cnx nzo The approximate value can be calculated by constructing in such a manner that the buffer memory 2 is -5connected to the bus 8 and the signal data from the signal data RAM 6 is supplied to the buffer memories 1 and 2 and the power of the signal data value x can be calculca,ted by the multiplier 3.

However, it is necessary to hold the result of the calculation by the multiplier 3 into-the accumulator and to transfer to the buffer memory 1 or 2 through the bus 8. For instance, to calculate c2'x 2, after x2 was multiplied by the multiplier 3, the value of the multiplication result is supplied and held into the accumulataor 5 via the ALU 4 and transferred to the buffer memory 1 through the bus 8 and, thereafter, C2 and x2 are multiplied. Therefore, new multiplication and accumulation cannot be performed until the data is transferred and there are problems such that the number of steps of the program increases and it takes a long processing time.

It is an object of the invention to provide a DSP which can reduce a processing time in the case of an arithmetic operation to multiply a plurality of coefficients to a signal data value and a calculation of an approximate value.

According to a DSP of the invention, there is -6provided a digital signal processor having first and second arithmetic operating sections each comprising: digital multiplying means for multiplying values of two digita:k signal data; and digital accumulating means for accumulating an output value of the multiplying means, wherein the output of the multiplying means in the second arithmetic operating section is connected to one input of the digital signal data of the multiplying means in the first arithmetic operating section.

on the other hand, according to a DSP of the invention, there is provided a digital signal processor having first and second arithmetic operating sections each comprising: digital multiplying means for multiplying values of two digital signal data; and digital accumulating means for accumulating an output value of the multiplying means, wherein the output ofthe multiplying means in the second arithmetic operating section is connected to one input of each of both of the multiplying means in the first and second arithmetic operating sections.

Embodiments of the invention will now be described by way of example only with reference to the accompanying drawings, in which:- Fig. 1 is a diagram showing a construction of a conventional DSP; Fig. 2 is a block diagram showing an embodiment of -7the present invention; Fig. 3 is a block diagram showing another embodiment of the invention; and Fig. 4 is a diagram showing a progressing state of the calculation of an approximate value.

A DSP according to the present invention shown in Fig. 2 has two arithmetic operating sections. The first arithmetic operating section comprises: buffer memories 11 and 12; a multiplier 13; an ALU 14; and an accumulator 15. Outputs of the buffer memories 11 and 12 are connected to the multiplier 13, respectively. An output of the multiplier 13 is connected to one input of the ALU 14. An output of the ALU 14 is connected to the accumulator 15. The accumulator 15 has two outputs and one of the outputs is connected to the other input of the ALU 14 and the other output is connected to a bus 10. The buffer memory 12 has three inputs.

on the other hand, the second arithmetic operating section comprises buffer memories 16 and 17, a multiplier 18, an ALU 19, and an accumulator 20 and is constructed in a manner similar to the first arithmetic operating section.

However, the multiplier 18 in the second arithmet ic -8operating section has two outputs and one output is connected to one input of the ALU 19 and the other output is connected to one input of the buffer memory 12.

Coefficient data bl, b2f..., bn are stored into a coefficient data RAM 21. An output of the RAM 21 is connected to the buffer memory ll.' A signal data RAM 22 is connected to the other input of the buffer memory 12. on the other hand, coefficient data al, a2r..., an are stored into a coefficient data RAM 23 and an output of the RAM 23 is connected to the buffer memory 16. A signal data RAM 24 is connected to the buffer memory 17. The signal RAMs 22 and 24 and the buffer memories 12 and 17 are also connected to the bus 10.

For the three inputs of the buffer memory 12, two inputs of the bufer memory 17, two outputs of each of the multiplier 18 and the accumulator 15 and 20, and two outputs of each of the signal data RAMs 22 and 24, either one of them is selectively made effective. They are constructed by a switching circuit comprising, for instance, a plurality of 3-state buffers and the like.

The operations such as reading operations of the coefficient data from the RAMs 21 and 23. reading operations of the signal data from the RAMs 22 and 24, arithmetic calculating operations of the ALUs 14 and 19, output selecting operations of the holding data of the -9accumulators 15 and 20, output selecting operation of the mulitplier 18, and the like are controlled by a sequence controller (not shown) in the DSP. The sequence controller operates in accordance with programs written in a program memory (not shown) in the DSP.

In the DSP having such a construction, audio signal data xn supplied from the outside is written into a predetermined area in the signal data RAM 24. In the case of executing an arithmetic operation E an.bnxn in which two coefficient data values are multiplied to the signal data value and the results of the multiplications are accumulated, first, signal data xl is read out of the signal data RAM 24 and supplied to the buffer memory 17 in the first step. On the othe hand, the coefficient data al is read out of the coefficient data RAM 23 and supplied to the buffer memory 16. Therefore, the multiplier 18 multiplies the values of the signal data xl and coefficient data al. The value xl.al of the result of the multiplication by the multiplier 18 is supplied from the other output to the buffer memory 12 in the second step which is one step after the first step. In the second step, the coetficient data bl is read out of the coefficient data RAM 21 and supplied to the buffer memory 11. Therefore, the multiplier 13 multiplies xl.al and the coefficient data value bl. The value al.bl.xl of -10the multiplication result by the multiplier 13 is held in the accumulator 15 via the ALU 14 in the third step.

In the second step, signal data x2 is read out of the sigpal data RAM 24 and supplied to the buffer memory 17. On the other hand, the coefficient data a2 is read out of the coefficient data RAM 23 and supplied to the buffer memory 16. Since the signal data and coefficient data are sequentially read out every step, the reading operations Of x2 and a2 are executed in the next step of the reading step of xl and al. The multiplier 18 multiplies the signal data value x2 and the coefficient data value a2. The value x2-a2 of the multiplication result by the multiplier 18 is supplied from the other output of the multiplier 18 to the buffer memory 12 in the third step. In the third step, the coefficinet data b2 is read out of the coefficient data RAM 21 and supplied to the buffer memory 11. Therefore, the multiplier 13 multiplies x2-a2 and the coefficient data value b2. The value a2-b2'x2 of the multiplication result by the multiplier 13 is supplied to the other input of the ALU 14. Synchronousyly with the supply of the value a2-b2'x2, the data value al-bl-xl held in the accumulator 15 is supplied to one input of the ALU 14. Therefore, in the fourth step, the ALU 14 executes the accumulation of al-bl-xl + a2-b2x2 and the value of the 21 1 accumulation result is held in the accumulator 15. By repeating the above operations, Z an-bn'xn is calculated. For example, when n = 6, the value Fb, an-bnxn Of the accumulation result is held in the accumulator 15 in the eighth step. The coefficient data al, a2,.... an are sequentially read out of the coefficient data RAM 23 every step from the first step. The coefficient data bl, b2f..., bn are sequentially read out of the coefficient data RAM 21 every step from the second step in accordance with this order.

Although the above embodiment has been described with respect to the calculation of an-bnxnr the invention is not limited to such a calculation but can be also applied to the case of other calculations.

Fig. 3 shows another embodiment of the invention. A DSP of Fig. 3 also has two arithmetic operating sections similarly to the DSP shown in Fig. 2. The buffer memory 11 in the first arithmetic operating section has two inputs and one input is connected to the coefficient data RAM 21 and the other input is connected to the bus 10.

on the other hand, the buffer memory 16 in the second arithmetic operating section has two inputs and one input is connected to the coefficient data RAM 23 and the other input is connected to the bus 10. The buffer memory 17 has three inputs and the first input is -12connected to the signal data RAM 24 and the second input is connected to bus 10. The multiplier 18 in the second arithmetic section has three outputs. The first output is connected to one input of the ALU 19, the second output is connected to the remaining third input of the buffer memory 12, and the third output is connected to the third input of the buffer memory 17.

The coefficient data RAMs 21 and 23 are also connected to the bus 10. The other inputs of the ALU 14 have two inputs. The first input is connected to an output of the multiplier 13 and the second input is connected to the bus 10.

On the other hand, with respect to the three inputs of the buffer memory 12, two inputs of each of the other buffer memories, three outputs of the multiplier 18, two outputs of each of the accumulators 15 and 20, two outputs of each of the RAMs 21 to 24, and the other two inputs of the ALU 14, only either one of them or two or more of them are selectively made effective. For instance, they are constructed by a switching circuit comprising a plurality of 3-state buffers and the like.

The operations such as reading operatinons of the coefficient data from the RAMs 21 and 23, reading operations of the signal data from the RAMs 22 and 24, arithmetic calculating operations of the ALUs 14 and 19, 1 output selecting operations of the holding data of the accumulators 15 and 20, output selecting operation of the multiplier 18, and the like are controlled by a sequence controler (not shown) in the DSP. The sequence controller operates in accordance with programs written in a program memory (not shown) in the DSP.

The other construction is similar to that shown in Fig. 2.

In the DSP having the above construction, when an xn is executed, the approximate value calculation of Cn nzo coefficient data values co, clt C2,... P % are written into the coefficient data RAM 21 before the start of the arithmetic calculating operation. On the other hand, the audio signal data x supplied from the outside is written into the signal data RAM 22.

When the arithmetic calculatiang operation is started, first, the signal data x is read out of the signal data RAM 24 and supplied to the buffer memories 12, 16, and 17 in the first step. On the other hand, the coefficient data cl is read out of the coefficient data RAM 21 and supplied to the buffer memory 11. Therefore, the multiplier 13 multiplies the values of the signal data x and the coefficient data al. The value cl. x of the multiplication result by the multiplier 13 is supplied and held into the accumulatoar 15 through the -14ALU 14 in the second step which is one step after the first step. The multiplier 18 executes a square calculation by mutually multiplying the signal data x. The value x2 of the multiplication result by the multiplier 18 is supplied to the buffer memories 12 and 17 in the second step.

In the second step, the coefficient data C2 is read out of the coefficient data RAM 21 and supplied to the buffer memory 11. Therefore, the multiplier 13 multiplies x2 and the coefficient data value c2. The value c2x 2 of the multiplication result by the multiplier 13 is supplied to the other first input of the ALU 14. Synchronously with the supply of the value c2x 2, the data value cl.x held in the accumulataor 15 is supplied to one input of the ALU 14. Therefore, in the third step, the ALU 14 executes an accumulation of cl-x + c2x 2 and the value of the accumulation result is held in the accumulator 15. On the other hand, the multiplier 18 multiplies the signal data x held in the buffer memory 16 and the signal data x2 held in the buffer memory 17. The value x3 of the multiplication result by the multiplier 18 is supplied to the buffer memories 12 and 17 in the third step.

In the third step, the coefficient data c3 is read out of the coefficient data RAM 21 and supplied to the i -15buffer memory 11. Therefore, the multiplier 13 multiplies x3 and the coefficient data value c3. value c3 x3 of the multiplication result by the multiplier 13 is supplied to the other first input of the ALU 14. Synchronously with the supply of the value c3'x 3, the accumulation data value cl.x + c2x 2 held in the accumulator 15 is supplied to one input of the ALU 14. Therefore, in the fourth step, the ALU 14 executes an accumulation of clx + c2 x2 + c3 x3 and the value of the accumulation result is held in the accumulator 15. on the other hand, the multiplier 18 multiplies the signal data x held in the buffer memory 16 and the signal data x3 held in the buffer memory 17. The value x4 of the multiplication result by the multiplier 18 is supplied to the buffer memories 12 and 17 in the fourth step.

By repeating the above operations, J,cnx n is calculated. In the step after n was held in the E, cn x accumulator 15, the coefficient data co is read out of the coefficient data RAM 21 and supplied to the other second input of the ALU 14. Synchronously with the supply of the coefficient data co, the accumulation data n held in the accumulator 15 is supplied to value E cnx A,- 1 one input of the ALU 14. Therefore, the ALU 14 executes r\ ri an accumulation of co + n and the value E c n of ,E, % n.O 1 -16the accumulation result is held in the accumulator 15.

For instance, when n = 4, as shown in Fig. 4, in the %J.', cn'x sixth step, the value E n of the accumulation result is held.in the accumulator 15 and obtained. The coefficient data cl, c2, ---, cni co are sequentially read out of the coefficient data RAM 21 every step in accordance with this order.

n In the above embodiment, the calculation of Z cn'x has been shown as an approximate value calculation. However, the invention is not limited to such a calculation but can be also applied to the case of other approximate value calculations.

As mentioned above, in the DSP according to the invention, there are provided the first and second arithmetic operating sections each comprising: the digital multiplying means for multiplying the values of two digital signal data; and the digital accumulating means for accumulating the output value of the multiplying means, wherein the output of the multiplying means in the second arithmetic operating section is connected to one input of the digital signal data of the multiplying means in the first arithmetic operating section. Therefore, in the case of an arithmetic operation such that a plurality of coefficients are 0 multiplied to the signal data value like Z an-bn'xnr n= I -17there is no need to transfer the part-way resultant data from the output of the accumulating means to the multiplying means through the bus in the way of the calculation. In addition, the data processes can be efficiently executed because the signal data or coefficient data as digital signal data is read out of the memory every step. Thus, the number of steps of the program can be reduced as compared with the conventional one. Therefore, the processing time can be reduced.

On the other hand, in the DSP according to the invention, there are provided the first and second arithmetic operating sections each comprising the digital multiplying means for multiplying the values of two digital signal data and the digital accumulating means for accumulating the output value of the multiplying means, wherein the output of the multiplying means in the second arithmetic operating section is connected to one input of each of both of the multiplying means in the first and second arithmetic operating sections. Therefore, in the case of executing an approximate value calculation such as n by the DSP, there is no need n7-o % x to transfer the part-way resultant data from the output of the accumulating means to the multiplying means through the bus in the way of the calculation. Thus, the data processes can be efficiently performed because the -18signal data and the coefficient data are read out of the memory every step. Therefore, the number of steps of the program can be reduced than the conventional one. Consequgntly, the processing time can be reduced.

tl

Claims

CLAIMS: -19-

1. A digital signal processor having first and second arithmetic operating sections each comprising: digital.multiplying means for multiplying values of two digital signal data; and digital accumulating means for accumulating an output value of said multiplying means, wherein an output of said multiplying means in said second arithmetic operating section is connected to one input of the digital signal data of said multiplying means in said first arithmetic operating section.

2. A digital signal processor having first and second arithmetic operating sections each comprising: digital multiplying means for multiplying values of two digital signal data; and digital accumulating means for accumulating an output value of said multiplying means, wherein an output of said multiplying means in said second arithmetic operating section is connected to one input of each of both of said multiplying means in said first and second arithmetic operating sections, respectively.

3. A digital signal processor according to claim 2, wherein said multiplying means in said second arithmetic operating section supplies data indicative of the result 1 -20of the multiplication to an input of said accumulating means in said second arithmetic operating section and one input of each of both of said multiplying means in said first and second arithmetic operating sections.

4. A digital signal Processor substantially as hereinbefore described with reference to and as illustrated in figure 2 of the accompanying drawings.

5. A digital signal Processor substantially as hereinbefore described with reference to and as illustrated in figure 3 of the accompanying drawings.

Published 1991 at The Patent Office. Concept House. Cardiff Road, Newport. Gwent NP9 1 RH. Further copies mkv be obtained from Sales Branch, Unit

6. Nine Mile Point. Cwmfelinfach, Cross Keys. Newport, NPI 7HZ. Printed by Multiplex techniques ltd, St Mary Cray, Kent.

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