GB2240242A

GB2240242A - Exponential multiplier

Info

Publication number: GB2240242A
Application number: GB9001303A
Authority: GB
Inventors: Michael Edwin Barnard; Bryan David Young
Original assignee: Philips Electronic and Associated Industries Ltd
Current assignee: Philips Electronics UK Ltd
Priority date: 1990-01-19
Filing date: 1990-01-19
Publication date: 1991-07-24
Also published as: GB9001303D0

Description

1

DESCRIPTION

EXPONENTIAL MULTIPLIER This invention relates to an exponential multiplier whose inputs and outputs are bi-level or single bit signals, having particular but not exclusive application to the removal of any residual carrier frequency present after down conversion to nominal zero frequency in a digital direct sequence spread spectrum radio receiver.

When a mixer or modulator is used.in conjunction with a local oscillator to perform a frequency conversion, the output of the mixer or modulator contains both sum and difference frequencies, some of which are normally regarded as spurious and which have to be removed by filtering. There are instances, however, such as when the input signal and local oscillator are close in frequency, when such filtering is not always practicable. An exponential multiplier (EM) can perform frequency conversions without generating such spurious frequency components although it does require that the input signals are each available in both their In-phase and Quadrature forms. As a background to the understanding of the present invention the operation of a conventional analogue EM is now briefly described.

Consider an input signal S1 which consists of data A(t) modulated onto a sinusoid of angular frequency w, thus:

Si = AMeJ14)t To recover the data A(t) from S1 the rotating component of the signal has to be removed. This is achieved by multiplying S1 with another rotating phasor of unit magnitude and frequency Q to give an output signal SO, thus:

SO A(t)ej4)t.ei-Qt = A(t)e(w+2)t When 11 -w the two phasors are rotating at the same rate but in opposite directions and the exponential term in the above expression is equal to 1, which gives:

So = AM 1 1 $ 2 PHB33614 Exponential multiplication can be performed by operating on the input signals as follows. Il and Q, are the In-phase and Quadrature components of one of the inputs to the EM. C and S are the In-phase and Quadrature components of the second input to the EM. The input components Il and Q1 are each multiplied by C and S. The products I1C and Q1S are added to produce an In-phase output component I. and the product I1S is subtracted from the product Q1C to produce a Quadrature output component Q0. The 10 and QO outputs of the EM are represented thus:- = Il.C + Q1.S ' QO = Q1.C Il.S Representing the input signals trigonometrically:

I0 = A(t) [cos wt. ' cos 1Qt + sin wt.sin 2t] QO = A(t) [sin wt.cos Ot cos wt.sin Qt] which simplify to; = A(t) cos (wg)t QO = AM sin (w-12)t Exponential multiplication has thus been performed albeit with a change in the polarity of one of the input signal frequencies. A schematic block diagram of a standard EM is shown in Figure 1 of the accompanying drawings and is described in greater detail later.

In the case of exponential multiplication of digital or sampled signals, it is possible to simplify the circuitry of an EM using a read only memory (ROM). If both the signal inputs and the local oscillator inputs to the EM can be represented by either single or multibit binary signals then these inputs can be fed to the address lines of a ROM which has been programmed with the appropriate output data for all possible combinations of inputs. The EM In-phase and Quadrature outputs are taken from two or more of the data lines of the ROM. The size of the ROM is dependant upon the number of input and output lines, and hence upon the resolution required in these signals.

UK patent specification 2153177A describes a radio receiver in which a programmable read only memory (PROM) is used in the manner described above to down convert a pair of quadrature related

3 PHB33614 signals from an intermediate frequency (IF) to baseband. This prior specification is concerned with the reception of signals from NAVSTAR global positioning system (GPS) satellites. Signals from GPS satellites are spread in frequency by a pseudo random noise (PRN) sequence prior to transmission and are typically received with a signal to noise ratio (SIN) of -20dB. Since these received signals have a negative SIN, sampling them with a small number of bits causes only small deteriorations in SIN. For example, sampling with a two-bit analogue to digital converter (ADC) causes a SIN deterioration of 0.6dB and sampling with a one-bit ADC (or comparator) causes a deterioration of MB. Such deteriorations in the SIN of the digitised signals are usually negligible and allow significant simplifications in the subsequent receiver circuitry. In the receiver disclosed in UK patent specification 2153177A the counter phasor rotation applied to the input signals is provided by a variable rate clock that increments a digital counter. The 6 most significant bits of the output of this counter are used as a partial address and are fed directly to the address lines of a PROM. The PROM can be programmed so that either one or two bit quadrature outputs can be taken from its data lines. This receiver has the disadvantage that it requires a large amount of memory; with two-bit inputs and outputs and a six-bit clock, 4k bytes of PROM are required.

It is an object of the present invention to simplify the process of exponential multiplication of bi-level or single-bit signals.

According to a first aspect of the present invention there is provided an exponential multiplier (EM) comprising first and second inputs for receiving a first pair of quadrature related bi-level or single bit input signals, third and fourth inputs for receiving a second pair of bi-level or single bit input signals and first and second outputs for providing quadrature related output signals, characterised in that each of the four possible distinct output 4 PHB33614 states comprise a pair of bi-level or single bit signals.

When the conventional analogue EM described in the opening paragraphs has purely bi-level input signals, taking for example only the values 1, each of the two quadrature related output signals can take any one of three values. namely 2, 0 and -2. The present invention is based on the realisation that with only four different combinations of input signals, only four separate output combinations can exist. By performing a known vector transformation on the output of the EM, these four separate outputs can be uniquely represented by two bi-level signals. Further, if the EM is being used for frequency translation in conjunction with a digital local oscillator, no trigonometric look-up table is required between the oscillator and the EM.

An EM in accordance with the present invention may be implemented as a read only memory, wherein the first, second, third and fourth inputs comprise single bit address lines and the first and second outputs comprise data lines.

Alternatively an EM in accordance with the present invention may be implemented by a circuit comprising first, second, third and fourth multipliers, each said multiplier having first and second inputs and an output, summing means connected to receive outputs from the first and fourth multipliers and a subtracting means having inputs connected to receive outputs from the second and third multipliers, first and second signal inputs for a first pair of quadrature related bi-level or single bit signals, the first signal input being connected to the first inputs of the first and second multipliers, the second signal input being connected to the first inputs of the third and fourth multipliers, third and fourth signal inputs for a second pair of quadrature related bi-level or single bit signals, the third signal input being connected to the second inputs of the first and third multipliers and the fourth input being connected to the second inputs of the second and fourth multipliers, characterised in that the outputs of the summing and the subtracting means are encoded as a pair of bi-level or single 1 PHB33614 bit signals and denote four distinct output states.

In one embodiment of the present invention the four possible output states are derived by multiplying one output phasor by 11,,f2and rotating the product by at least z/4 radian.

In another embodiment of the present invention the four possible output states are derived by rotating an output phasor by an odd integer multiple of z/4 radian.

According to a second aspect of the present invention there is provided a radio receiver comprising means for producing a pair of quadrature related signals at an intermediate frequency and an exponential multiplier (EM) for frequency converting these quadrature related signals to baseband signals, characterised in that the EM is of a type in accordance with the first aspect of the present invention.

One important field of application for the present invention is in a radio receiver for direct sequence spread spectrum signals. The reason for this is that these signals are received with a negative SIN and the sampling of such signals using a small number of quantization steps carries a relatively low penalty in SIN deterioration.

The present invention will now be explained and described by way of example, with reference to the accompanying drawings, wherein:

Figure 1 is a block schematic diagram of a conventional analogue exponential multiplier, - Fi; gure 2 is a table of all the possible input and output states when a conventional analogue EM is fed with purely bi-level input signals, Figure 3 is a phasor diagram showing the phasor transformation used in an EM in accordance with the present invention, Figure 4 is a block schematic diagram'of a read only memory (ROM) implementation of the invention, and Figure 5 is a block schematic'diagram of a spread spectrum X- 6 PHB33614 radio receiver that uses a single bit exponential multiplier to remove the residual carrier frequency that remains after a first down-conversion.

Referring to Figure 1, an In-phase input I, is connected to one input of each of a pair of multipliers 11 and 12 and a Quadrature input Q1 is connected to one input of each of a further pair of multipliers 13 and 14. A local oscillator (L0) In-phase input C (co.5ine)'is connected to the second inputs of the multipliers 11 and 13 and a LO Quadrature input S (sine) is connected to the second inputs of the multipliers 12 and 14. The outputs of the multipliers 11 and 14 are added in a summer 17 to provide an In-phase output I.. The output of the multiplier 12 is subtracted from the output of the multiplier 13 in a subtractor 18 to provide a Quadrature output Q0. The case is now considered where this conventional analogue EM is fed with only bi-level inputs of magnitude +1 or -1 at each of its four inputs I,, Q1, C, S.

Figure 2 of the accompanying drawings shows all the possible input signal combinations and their corresponding outputs when the analogue EM shown in Figure 1 is fed with purely bi-level signals of amplitude 1. Each of the outputs, given in the two rightmost columns, can take any one of three values, namely 2, 0, and -2. A digital implementation of an EM will thus require a greater number of bits to represent the outputs than the number of bits representing the inputs because three distinct output values occur at each output line for inputs having only two distinct values. No mention of this problem has been made in UK patent specification 2153177A. A closer inspection of Figure 2 shows that although each output can assume any one of three values, there are only only four distinct output states of the circuit, namely (2,0), (0,2), (-2, 0), (0,-2), and it is thus possible to represent these states without ambiguity by use of two bi-level signals. To represent these four states by a pair of signals that can each take for example only the lk- 7 PHB33614 values +1 and -1, some assignment of the four distinct output states has to be made. The output states corresponding to those given above could be assigned as (1,1), (-1,1), (-1,-1) and (1,-1) respectively. This selection of outputs of the EM corresponds to a multiplication of the output phasor by 11.,,.'2 and a rotation of w/4 in the positive direction.

Figure 3 of the accompanying drawings shows this multiplication and rotation on a phasor diagram. The output states of the EM could be assigned to correspond to a rotation of any odd integer multiple of z14. They could even be assigned in such a way that they did not conform to one single phasor transformation, in other words the assignment could be arbitrary, should such an assignment be desired.

To interface an EM with digital circuitry it is convenient for its input and output signals to be binary signals and to achieve this a decision has to be made as to how the binary signals should be allocated. In this example binary zero is chosen to represent -1 and binary one is chosen to represent +1, although the converse allocation could also be used. Being able to use two bits to encode the four states allows the EM to be implemented using digital circuitry such as a read only memory (ROM).

Figure 4 of the accompanying drawings shows an embodiment of the invention in which ao to a3 are the address lines and do and dl are the data lines of a ROM. Inw-phase input Il is fed to address line ao. Quadrature input Q1 is fed to address line al. In-phase input C is fed to address line a2. Quadrature input S is fed to address line a3. In-phase output 10 is fed from data line do and Quadrature output QO is fed from data line dj. The memory locations of the ROM, programmed assuming an output phase shift and a binary assignment as described above, are shown in the table below, together with a brief description of the meaning of each EM output state. The table assumes that the Input signals are fed to Il and Q1 and that the Local Oscillator (L0) signals are fed to C and S.

1 kl 8 is PHB33614 ADDRESS LINES DATA LINES DESCRIPTION a c) al a2 a3 do dl Q, c S I. QO 1 1 1 1 1 IN PHASE 1 1 1 0 0 1 INPUT LEADING LO BY w/4 1 1 0 1 1 0 INPUT LAGGING LO BY ir/4 1 1 0 0 0 0 INPUT AND LO IN ANTI-PHASE 0 1 1 1 0 INPUT LAGGING LO BY w/4 1 0 1 0 1 1 IN PHASE 1 0 0 1 0 0 INPUT AND LO IN ANTI-PHASE 0 0 0 0 1 1 INPUT LEADING LO BY %14 o 1 1 1 0 1 INPUT LEADING LO BY z/4 0 1 1 0 1 0 0 INPUT AND LO IN ANTI-PHASE 0 1 0 1 IN PHASE 0 1---10 0 1 1 0 1 INPUT LAGGING LO BY z/4 0 0 1 1 1 0 1 0 1 INPUT AND LO IN ANTI-PHASE 0 0 1 0 1 1 0 1 INPUT LAGGING LO BY ir/4 0 0 1 0 1 0 1 INPUT LEADING LO BY z/4 0 0 0 0 1 1 IN PHASE A single bit exponential multiplier as described above only has an output phase resolution of w/2 so that at any instant the output could be in error by z/4. This error is in addition to the fixed. known phase offset of w/4. The output phase resolution of the single bit EM can be improved by use of accumulation of its outputs. With a pair of hard limited or substantially square wave quadrature inputs, the output of the EM will alternate between two or more of its I- A C 1 9 PHB33614 possible states. By averaging the outputs over time a more accurate measure of the phase difference between the input signals can be obtained although the accumulation process should take account of the fact that in this case binary 0 represents -1.

Figure 5 of the accompanying drawings shows a block schematic diagram of a direct sequence spread spectrum receiver using an exponential multiplier in accordance with the invention to remove residual carrier frequency components that are still present after an initial down-conversion. The signals to be received have been spread in frequency by a pseudo random noise (PRN) code prior to transmission and are typically received with a SIN of -20dB.

Incoming signals are received by an antenna 20 and fed to an amplification and bandpass filtering means 21. In some cases the bandpass filtering means 21 may be replaced by a more complex circuit performing frequency translation as well as bandpass filtering. The output of the means 21 is fed to one input each of mixers 22 and 23Y the second input of mixer 22 is fed directly from a local oscillator 24 and the second input of mixer.23 is fed from the local oscillator 24 via a 900 phase shifter 25. The outputs of mixers 22 and 23 are filtered separately in low pass filters 26 and 27, respectively. The output of filter 26 is digitised in analogue to digital converter (ADC) 30 and the output of filter 27 is digitised in ADC 31. These two ADCs have single bit outputs and can be driven by a common clock 32 which runs at a rate that is sufficient to satisfy the Nyquist sampling criterion with respect to the incoming signal bandwidth. The outputs of ADCs 30 and 31 are now to he despread, which means that the PRN code used to spread the signal originally is generated locally and multiplied with the incoming signals. If the two codes are correlated (that is, have no relative delay) the spreading code is effectively multiplied by itself and the product is 1, in other words a DC level. This despreading allows the original data to be recovered.

The output of ADC 30 is fed to one input of a mixer 33 and the output of ADC 31 is fed to one input of a mixer 34. The remaining inputs of mixers 33 and 34 are provided by a pseudo random noise (PRN) generator 35 which is controlled by a receiver 1 C PB333614 controller 42. The outputs of mixers 33 and 34 are fed to the I1 and Q, inputs respectively of an exponential multiplier 36. The C input of EM 36 is provided by a local oscillator (L0) 37 and the S input of EM 36 is provided by LO 37 via a 900 phase shifter 38. If the EM is to be realised using ROM circuitry some means (not shown) of signal level adjustment will be required after the mixers 33 and 34 to ensure that I, and Q, are binary signals. In a ROM based implementation, the LO inputs to the EM will be the two most significant bits of a counter which is driven by LO 37 and the ROM programming takes account of the fact that they are not quadrature waveforms in this case. LO 37 is controlled by the receiver controller 42.

The 10 and Q. outputs of the exponential multiplier 36 are fed separately to low pass filters 40 and 41 respectively and the outputs of these filters are fed to the receiver controller 42.

Low pass filters 40 and 41 remove noise which is present outside the signal bandwidth, accumulate the outputs of the EM and reduce the rate of the data fed to the receiver controller 42. In this embodiment filters 40 and 41 are decimation filters. The receiver controller monitors the outputs of the filters 40 and 41 and controls the frequency and phase of the local oscillator 37, and the rate of generation of the PRN code used to despread the incoming data signals. The purpose of the receiver controller is to recover the data from the incoming signals and to this end it can correlate the locally generated and incoming PRN codes and use EM 36 in conjunction with LO 37 to cancel any residual intermediate frequencies based on the outputs from low pass filters 40 and 41.

The receiver controller could also perform other functions dictated by a particular receiver application.

From reading the present disclosure, other modifications will be apparent to persons skilled in the art. Such modifications may involve other features which are already known in the design, manufacture and use of exponential multipliers and component parts thereof and which may be used instead of or in addition to features already described herein. Although claims have been formulated in F 11 PHB33614 this application to particular combinations of features, it should be understood that the scope of the disclosure of the present application also includes any novel feature or any novel combination of features disclosed herein either explicitly or implicitly or any generalisation thereof, whether or not it relates to the same invention as presently claimed in any claim and whether or not it mitigates any or all of the same technical problems as does the present invention. The applicants hereby give notice that new claims may be formulated to such features andlor combinations of such features during the prosecution of the present application or of any further application derived therefrom.

1 35 4 k_ 12 PHB33614

Claims

1. An exponential multiplier (EM) comprising first and second inputs for receiving a first pair of quadrature related bi-level or single bit input signals, third and fourth inputs for receiving a second pair of bi-level or single bit input signals and first and second outputs for providing quadrature related output signals. characterised in that each of the four possible distinct output states comprise a pair of bi-level or single bit signals.

2. An EM as claimed in Claim 1. characterised in that the EM is implemented as a read only memory, wherein the first, second, third and fourth inputs comprise single bit address lines and the first and second outputs comDrise data lines.

3. An EM comprising first, second, third and fourth multipliers, each said multiplier having first and second inputs and an output, summing means connected to receive outputs from the first and fourth multipliers and a subtracting means having inputs connected to receive outputs from the second and third multipliers, first and second signal inputs for a first pair of quadrature related bi-level or single bit signals, the first signal input being connected to the first inputs of the first and second multipliers. the second signal input being connected to the first inputs of the third and fourth multipliers, third and fourth signal inputs for a second pair of quadrature related bi- level or single bit signals, the third signal input being connected to the second inputs of the first and third multipliers and the fourth input being connected to the second inputs of the second and fourth multipliers, characterised in that the outputs of the summing and the subtracting means are encoded as a pair of bi-level or single bit signals and denote four distinct output states.

4. An EM as claimed in any one of Claims 1, 2 or 3, characterised in that the four possible output states are derived by multiplying an output phasor by 11rZ and rotating the product by at least w/4 radian.

5. An EM as claimed in any one of Claims 1, 2 or 3, characterised in that the four possible output states are derived L ( k, p 13 PHB33614 by rotating an output phasor by an odd integer multiple of z/4 radian.

6. An exponential multiplier constructed and arranged to operate substantially as hereinbefore described with reference to and as shown in Figures 3, 4 and 5 of the accompanying drawings.

7. A radio receiver comprising means for producing a pair of quadrature related signals at an intermediate frequency and an exponential multiplier (EM) for frequency converting these quadrature related signals to baseband signals, characterized in that the EM is of a type as claimed in any one of Claims 1 to 6.

8. A radio receiver as claimed in Claim 7, characterised in that the quadrature related signals are spread spectrum signals.

9. A radio receiver constructed and arranged to operate substantially as hereinbefore described with reference to and as shown in Figures 3, 4 and 5 of the accompanying drawings.

Published 199 1 at The Patent Office. State House. 66171 High Holborn, Londj., WC 1 R 4TP. Further copies may be obtained from Sales Branch. Unit 6. Nine Mile Point. CUnfach. Cross Keys, Newport. NPI 7HZ. Printed by Multiplex technique& lid. St Mary Cray, Kent.

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